src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75 #if GEN_GEN <= 11
  76    [ISL_TILING_W]       = WMAJOR,
  77 #endif
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 12
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94 };
  95 #elif GEN_GEN >= 9
  96 static const uint32_t isl_to_gen_aux_mode[] = {
  97    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  98    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  99    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
 100    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
 101    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
 102 };
 103 #elif GEN_GEN >= 8
 104 static const uint32_t isl_to_gen_aux_mode[] = {
 105    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 106    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 107    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 108    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 109 };
 110 #endif
 111
 112 static uint8_t
 113 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 114 {
 115    switch (dim) {
 116    default:
 117       unreachable("bad isl_surf_dim");
 118    case ISL_SURF_DIM_1D:
 119       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 120       return SURFTYPE_1D;
 121    case ISL_SURF_DIM_2D:
 122       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 123           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 124          /* We need SURFTYPE_CUBE to make cube sampling work */
 125          return SURFTYPE_CUBE;
 126       } else {
 127          /* Everything else (render and storage) treat cubes as plain
 128           * 2D array textures
 129           */
 130          return SURFTYPE_2D;
 131       }
 132    case ISL_SURF_DIM_3D:
 133       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 134       return SURFTYPE_3D;
 135    }
 136 }
 137
 138 /**
 139  * Get the horizontal and vertical alignment in the units expected by the
 140  * hardware.  Note that this does NOT give you the actual hardware enum values
 141  * but an index into the isl_to_gen_[hv]align arrays above.
 142  */
 143 UNUSED static struct isl_extent3d
 144 get_image_alignment(const struct isl_surf *surf)
 145 {
 146    if (GEN_GEN >= 9) {
 147       if (isl_tiling_is_std_y(surf->tiling) ||
 148           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 149          /* The hardware ignores the alignment values. Anyway, the surface's
 150           * true alignment is likely outside the enum range of HALIGN* and
 151           * VALIGN*.
 152           */
 153          return isl_extent3d(4, 4, 1);
 154       } else {
 155          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 156           * of surface elements (not pixels nor samples). For compressed formats,
 157           * a "surface element" is defined as a compression block.  For example,
 158           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 159           * format (ETC2 has a block height of 4), then the vertical alignment is
 160           * 4 compression blocks or, equivalently, 16 pixels.
 161           */
 162          return isl_surf_get_image_alignment_el(surf);
 163       }
 164    } else {
 165       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 166        * units of surface samples.  For example, if SurfaceVerticalAlignment
 167        * is VALIGN_4 and the surface is singlesampled, then for any surface
 168        * format (compressed or not) the vertical alignment is
 169        * 4 pixels.
 170        */
 171       return isl_surf_get_image_alignment_sa(surf);
 172    }
 173 }
 174
 175 #if GEN_GEN >= 8
 176 static uint32_t
 177 get_qpitch(const struct isl_surf *surf)
 178 {
 179    switch (surf->dim_layout) {
 180    default:
 181       unreachable("Bad isl_surf_dim");
 182    case ISL_DIM_LAYOUT_GEN4_2D:
 183       if (GEN_GEN >= 9) {
 184          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 185             /* This is rather annoying and completely undocumented.  It
 186              * appears that the hardware has a bug (or undocumented feature)
 187              * regarding stencil buffers most likely related to the way
 188              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 189              * stencil buffer normally, and use texelFetch on it, the z or
 190              * array index will get implicitly multiplied by 2 for no obvious
 191              * reason.  The fix appears to be to divide qpitch by 2 for
 192              * W-tiled surfaces.
 193              */
 194             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 195          } else {
 196             return isl_surf_get_array_pitch_el_rows(surf);
 197          }
 198       } else {
 199          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 200           *
 201           *    "This field must be set to an integer multiple of the Surface
 202           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 203           *    ETC*, and EAC* Surface Formats), this field is in units of
 204           *    rows in the uncompressed surface, and must be set to an
 205           *    integer multiple of the vertical alignment parameter "j"
 206           *    defined in the Common Surface Formats section."
 207           */
 208          return isl_surf_get_array_pitch_sa_rows(surf);
 209       }
 210    case ISL_DIM_LAYOUT_GEN9_1D:
 211       /* QPitch is usually expressed as rows of surface elements (where
 212        * a surface element is an compression block or a single surface
 213        * sample). Skylake 1D is an outlier.
 214        *
 215        * From the Skylake BSpec >> Memory Views >> Common Surface
 216        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 217        *
 218        *    Surface QPitch specifies the distance in pixels between array
 219        *    slices.
 220        */
 221       return isl_surf_get_array_pitch_el(surf);
 222    case ISL_DIM_LAYOUT_GEN4_3D:
 223       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 224        * different pitch at each LOD.  Also, the QPitch field is ignored for
 225        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 226        *
 227        *    This field specifies the distance in rows between array slices. It
 228        *    is used only in the following cases:
 229        *     - Surface Array is enabled OR
 230        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 231        *       Surface Storage Format set to MSFMT_MSS OR
 232        *     - Surface Type is SURFTYPE_CUBE
 233        *
 234        * None of the three conditions above can possibly apply to a 3D surface
 235        * so it is safe to just set QPitch to 0.
 236        */
 237       return 0;
 238    }
 239 }
 240 #endif /* GEN_GEN >= 8 */
 241
 242 void
 243 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 244                             const struct isl_surf_fill_state_info *restrict info)
 245 {
 246    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 247
 248    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 249
 250    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 251       assert(isl_format_supports_rendering(dev->info, info->view->format));
 252    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 253       assert(isl_format_supports_sampling(dev->info, info->view->format));
 254
 255    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 256     *
 257     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 258     *    format if the Surface Type is SURFTYPE_1D
 259     */
 260    if (info->surf->dim == ISL_SURF_DIM_1D)
 261       assert(!isl_format_is_compressed(info->view->format));
 262
 263    if (isl_format_is_compressed(info->surf->format)) {
 264       /* You're not allowed to make a view of a compressed format with any
 265        * format other than the surface format.  None of the userspace APIs
 266        * allow for this directly and doing so would mess up a number of
 267        * surface parameters such as Width, Height, and alignments.  Ideally,
 268        * we'd like to assert that the two formats match.  However, we have an
 269        * S3TC workaround that requires us to do reinterpretation.  So assert
 270        * that they're at least the same bpb and block size.
 271        */
 272       ASSERTED const struct isl_format_layout *surf_fmtl =
 273          isl_format_get_layout(info->surf->format);
 274       ASSERTED const struct isl_format_layout *view_fmtl =
 275          isl_format_get_layout(info->surf->format);
 276       assert(surf_fmtl->bpb == view_fmtl->bpb);
 277       assert(surf_fmtl->bw == view_fmtl->bw);
 278       assert(surf_fmtl->bh == view_fmtl->bh);
 279    }
 280
 281    s.SurfaceFormat = info->view->format;
 282
 283 #if GEN_GEN <= 5
 284    s.ColorBufferComponentWriteDisables = info->write_disables;
 285 #else
 286    assert(info->write_disables == 0);
 287 #endif
 288
 289 #if GEN_IS_HASWELL
 290    s.IntegerSurfaceFormat =
 291       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 292 #endif
 293
 294    assert(info->surf->logical_level0_px.width > 0 &&
 295           info->surf->logical_level0_px.height > 0);
 296
 297    s.Width = info->surf->logical_level0_px.width - 1;
 298    s.Height = info->surf->logical_level0_px.height - 1;
 299
 300    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 301     * (Surface Arrays For all surfaces other than separate stencil buffer):
 302     *
 303     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 304     *  calculated in the equation above , for every other odd Surface Height
 305     *  starting from 1 i.e. 1,5,9,13"
 306     *
 307     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 308     * input for the rendering surface to achieve the same qpitch. For the
 309     * affected heights, we increment the height by 1 for the rendering
 310     * surface.
 311     */
 312    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 313        info->surf->samples > 1 &&
 314        (info->surf->logical_level0_px.height % 4) == 1)
 315       s.Height++;
 316
 317    switch (s.SurfaceType) {
 318    case SURFTYPE_1D:
 319    case SURFTYPE_2D:
 320       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 321        *
 322        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 323        *    must be set to zero if this surface is used with sampling engine
 324        *    messages."
 325        *
 326        * This restriction appears to exist only on Ivy Bridge.
 327        */
 328       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 329           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 330           info->surf->samples > 1)
 331          assert(info->view->base_array_layer == 0);
 332
 333       s.MinimumArrayElement = info->view->base_array_layer;
 334
 335       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 336        *
 337        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 338        *    by one for each increase from zero of Minimum Array Element. For
 339        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 340        *    the range of this field is reduced to [0,1023].
 341        *
 342        * In other words, 'Depth' is the number of array layers.
 343        */
 344       s.Depth = info->view->array_len - 1;
 345
 346       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 347        *
 348        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 349        *    This field must be set to the same value as the Depth field.
 350        */
 351       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 352                                ISL_SURF_USAGE_STORAGE_BIT))
 353          s.RenderTargetViewExtent = s.Depth;
 354       break;
 355    case SURFTYPE_CUBE:
 356       s.MinimumArrayElement = info->view->base_array_layer;
 357       /* Same as SURFTYPE_2D, but divided by 6 */
 358       s.Depth = info->view->array_len / 6 - 1;
 359       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 360                                ISL_SURF_USAGE_STORAGE_BIT))
 361          s.RenderTargetViewExtent = s.Depth;
 362       break;
 363    case SURFTYPE_3D:
 364       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 365        *
 366        *    If the volume texture is MIP-mapped, this field specifies the
 367        *    depth of the base MIP level.
 368        */
 369       s.Depth = info->surf->logical_level0_px.depth - 1;
 370
 371       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 372        *
 373        *    For Render Target and Typed Dataport 3D Surfaces: This field
 374        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 375        *    the LOD currently being rendered to.
 376        *
 377        * The docs specify that this only matters for render targets and
 378        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 379        * Depth field has more bits than RenderTargetViewExtent so we can have
 380        * textures with more levels than we can render to.  In order to prevent
 381        * assert-failures in the packing function below, we only set the field
 382        * when it's actually going to be used by the hardware.
 383        *
 384        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 385        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 386        * Since it's already initialized to 0, we can just leave it alone for
 387        * texture surfaces.
 388        */
 389       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 390                                ISL_SURF_USAGE_STORAGE_BIT)) {
 391          s.MinimumArrayElement = info->view->base_array_layer;
 392          s.RenderTargetViewExtent = info->view->array_len - 1;
 393       }
 394       break;
 395    default:
 396       unreachable("bad SurfaceType");
 397    }
 398
 399 #if GEN_GEN >= 7
 400    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 401 #endif
 402
 403    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 404       /* For render target surfaces, the hardware interprets field
 405        * MIPCount/LOD as LOD. The Broadwell PRM says:
 406        *
 407        *    MIPCountLOD defines the LOD that will be rendered into.
 408        *    SurfaceMinLOD is ignored.
 409        */
 410       s.MIPCountLOD = info->view->base_level;
 411       s.SurfaceMinLOD = 0;
 412    } else {
 413       /* For non render target surfaces, the hardware interprets field
 414        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 415        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 416        */
 417       s.SurfaceMinLOD = info->view->base_level;
 418       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 419    }
 420
 421 #if GEN_GEN >= 9
 422    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 423     * Start LOD" to 15 to prevent the hardware from trying to use them.
 424     */
 425    s.TiledResourceMode = NONE;
 426    s.MipTailStartLOD = 15;
 427 #endif
 428
 429 #if GEN_GEN >= 6
 430    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 431    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 432 #if GEN_GEN >= 7
 433    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 434 #endif
 435 #endif
 436
 437    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 438       /* For gen9 1-D textures, surface pitch is ignored */
 439       s.SurfacePitch = 0;
 440    } else {
 441       s.SurfacePitch = info->surf->row_pitch_B - 1;
 442    }
 443
 444 #if GEN_GEN >= 8
 445    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 446 #elif GEN_GEN == 7
 447    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 448                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 449 #endif
 450
 451 #if GEN_GEN >= 8
 452    assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
 453    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 454 #else
 455    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 456    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 457                                                       TILEWALK_XMAJOR,
 458 #endif
 459
 460 #if GEN_GEN >= 8
 461    s.RenderCacheReadWriteMode = WriteOnlyCache;
 462 #else
 463    s.RenderCacheReadWriteMode = 0;
 464 #endif
 465
 466 #if GEN_GEN >= 11
 467    /* We've seen dEQP failures when enabling this bit with UINT formats,
 468     * which particularly affects blorp_copy() operations.  It shouldn't
 469     * have any effect on UINT textures anyway, so disable it for them.
 470     */
 471    s.EnableUnormPathInColorPipe =
 472       !isl_format_has_int_channel(info->view->format);
 473 #endif
 474
 475    s.CubeFaceEnablePositiveZ = 1;
 476    s.CubeFaceEnableNegativeZ = 1;
 477    s.CubeFaceEnablePositiveY = 1;
 478    s.CubeFaceEnableNegativeY = 1;
 479    s.CubeFaceEnablePositiveX = 1;
 480    s.CubeFaceEnableNegativeX = 1;
 481
 482 #if GEN_GEN >= 6
 483    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 484 #if GEN_GEN >= 7
 485    s.MultisampledSurfaceStorageFormat =
 486       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 487 #endif
 488 #endif
 489
 490 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 491    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 492       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 493
 494    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 495    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 496    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 497    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 498 #else
 499    assert(isl_swizzle_is_identity(info->view->swizzle));
 500 #endif
 501
 502    s.SurfaceBaseAddress = info->address;
 503
 504 #if GEN_GEN >= 6
 505    s.MOCS = info->mocs;
 506 #endif
 507
 508 #if GEN_GEN > 4 || GEN_IS_G4X
 509    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 510       /* There are fairly strict rules about when the offsets can be used.
 511        * These are mostly taken from the Sky Lake PRM documentation for
 512        * RENDER_SURFACE_STATE.
 513        */
 514       assert(info->surf->tiling != ISL_TILING_LINEAR);
 515       assert(info->surf->dim == ISL_SURF_DIM_2D);
 516       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 517       assert(info->surf->levels == 1);
 518       assert(info->surf->logical_level0_px.array_len == 1);
 519       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 520
 521       if (GEN_GEN >= 8) {
 522          /* Broadwell added more rules. */
 523          assert(info->surf->samples == 1);
 524          if (isl_format_get_layout(info->view->format)->bpb == 8)
 525             assert(info->x_offset_sa % 16 == 0);
 526          if (isl_format_get_layout(info->view->format)->bpb == 16)
 527             assert(info->x_offset_sa % 8 == 0);
 528       }
 529
 530 #if GEN_GEN >= 7
 531       s.SurfaceArray = false;
 532 #endif
 533    }
 534
 535    const unsigned x_div = 4;
 536    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 537    assert(info->x_offset_sa % x_div == 0);
 538    assert(info->y_offset_sa % y_div == 0);
 539    s.XOffset = info->x_offset_sa / x_div;
 540    s.YOffset = info->y_offset_sa / y_div;
 541 #else
 542    assert(info->x_offset_sa == 0);
 543    assert(info->y_offset_sa == 0);
 544 #endif
 545
 546 #if GEN_GEN >= 7
 547    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 548       /* The docs don't appear to say anything whatsoever about compression
 549        * and the data port.  Testing seems to indicate that the data port
 550        * completely ignores the AuxiliarySurfaceMode field.
 551        */
 552       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 553
 554       struct isl_tile_info tile_info;
 555       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 556       uint32_t pitch_in_tiles =
 557          info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 558
 559       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 560       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 561
 562 #if GEN_GEN >= 8
 563       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 564       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 565        * doesn't expect our definition of the compression, it expects qpitch
 566        * in units of samples on the main surface.
 567        */
 568       s.AuxiliarySurfaceQPitch =
 569          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 570
 571       if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
 572          /* The number of samples must be 1 */
 573          assert(info->surf->samples == 1);
 574
 575          /* The dimension must not be 3D */
 576          assert(info->surf->dim != ISL_SURF_DIM_3D);
 577
 578          /* The format must be one of the following: */
 579          switch (info->view->format) {
 580          case ISL_FORMAT_R32_FLOAT:
 581          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 582          case ISL_FORMAT_R16_UNORM:
 583             break;
 584          default:
 585             assert(!"Incompatible HiZ Sampling format");
 586             break;
 587          }
 588       }
 589
 590       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 591 #else
 592       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 593              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 594       s.MCSEnable = true;
 595 #endif
 596    }
 597 #endif
 598
 599 #if GEN_GEN >= 8 && GEN_GEN < 11
 600    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 601     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 602     *
 603     *    This bit must be set for the following surface types: BC2_UNORM
 604     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 605     */
 606    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 607       switch (info->view->format) {
 608       case ISL_FORMAT_BC2_UNORM:
 609       case ISL_FORMAT_BC3_UNORM:
 610       case ISL_FORMAT_BC5_UNORM:
 611       case ISL_FORMAT_BC5_SNORM:
 612       case ISL_FORMAT_BC7_UNORM:
 613          s.SamplerL2BypassModeDisable = true;
 614          break;
 615       default:
 616          /* From the SKL PRM, Programming Note under Sampler Output Channel
 617           * Mapping:
 618           *
 619           *    If a surface has an associated HiZ Auxilliary surface, the
 620           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 621           *    must be set.
 622           */
 623          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 624             s.SamplerL2BypassModeDisable = true;
 625          break;
 626       }
 627    }
 628 #endif
 629
 630    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 631       if (info->use_clear_address) {
 632 #if GEN_GEN >= 10
 633          s.ClearValueAddressEnable = true;
 634          s.ClearValueAddress = info->clear_address;
 635 #else
 636          unreachable("Gen9 and earlier do not support indirect clear colors");
 637 #endif
 638       }
 639
 640 #if GEN_GEN == 11
 641       /*
 642        * From BXML > GT > Shared Functions > vol5c Shared Functions >
 643        * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
 644        *
 645        *   Project: Gen11
 646        *
 647        *   "Enables Pixel backend hw to convert clear values into native format
 648        *    and write back to clear address, so that display and sampler can use
 649        *    the converted value for resolving fast cleared RTs."
 650        *
 651        * Summary:
 652        *   Clear color conversion must be enabled if the clear color is stored
 653        *   indirectly and fast color clears are enabled.
 654        */
 655       if (info->use_clear_address) {
 656          s.ClearColorConversionEnable = true;
 657       }
 658 #endif
 659
 660 #if GEN_GEN >= 12
 661       assert(info->use_clear_address);
 662 #elif GEN_GEN >= 9
 663       if (!info->use_clear_address) {
 664          s.RedClearColor = info->clear_color.u32[0];
 665          s.GreenClearColor = info->clear_color.u32[1];
 666          s.BlueClearColor = info->clear_color.u32[2];
 667          s.AlphaClearColor = info->clear_color.u32[3];
 668       }
 669 #elif GEN_GEN >= 7
 670       /* Prior to Sky Lake, we only have one bit for the clear color which
 671        * gives us 0 or 1 in whatever the surface's format happens to be.
 672        */
 673       if (isl_format_has_int_channel(info->view->format)) {
 674          for (unsigned i = 0; i < 4; i++) {
 675             assert(info->clear_color.u32[i] == 0 ||
 676                    info->clear_color.u32[i] == 1);
 677          }
 678          s.RedClearColor = info->clear_color.u32[0] != 0;
 679          s.GreenClearColor = info->clear_color.u32[1] != 0;
 680          s.BlueClearColor = info->clear_color.u32[2] != 0;
 681          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 682       } else {
 683          for (unsigned i = 0; i < 4; i++) {
 684             assert(info->clear_color.f32[i] == 0.0f ||
 685                    info->clear_color.f32[i] == 1.0f);
 686          }
 687          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 688          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 689          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 690          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 691       }
 692 #endif
 693    }
 694
 695    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 696 }
 697
 698 void
 699 isl_genX(buffer_fill_state_s)(void *state,
 700                               const struct isl_buffer_fill_state_info *restrict info)
 701 {
 702    uint64_t buffer_size = info->size_B;
 703
 704    /* Uniform and Storage buffers need to have surface size not less that the
 705     * aligned 32-bit size of the buffer. To calculate the array lenght on
 706     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 707     * added to the surface, so we can calculate latter the original buffer
 708     * size to know the number of elements.
 709     *
 710     *  surface_size = isl_align(buffer_size, 4) +
 711     *                 (isl_align(buffer_size) - buffer_size)
 712     *
 713     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 714     */
 715    if (info->format == ISL_FORMAT_RAW  ||
 716        info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
 717       assert(info->stride_B == 1);
 718       uint64_t aligned_size = isl_align(buffer_size, 4);
 719       buffer_size = aligned_size + (aligned_size - buffer_size);
 720    }
 721
 722    uint32_t num_elements = buffer_size / info->stride_B;
 723
 724    if (GEN_GEN >= 7) {
 725       /* From the IVB PRM, SURFACE_STATE::Height,
 726        *
 727        *    For typed buffer and structured buffer surfaces, the number
 728        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 729        *    surfaces, the number of entries in the buffer is the number of bytes
 730        *    which can range from 1 to 2^30.
 731        */
 732       if (info->format == ISL_FORMAT_RAW) {
 733          assert(num_elements <= (1ull << 30));
 734          assert(num_elements > 0);
 735       } else {
 736          assert(num_elements <= (1ull << 27));
 737       }
 738    } else {
 739       assert(num_elements <= (1ull << 27));
 740    }
 741
 742    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 743
 744    s.SurfaceType = SURFTYPE_BUFFER;
 745    s.SurfaceFormat = info->format;
 746
 747 #if GEN_GEN >= 6
 748    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 749 #if GEN_GEN >= 7
 750    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 751    s.SurfaceArray = false;
 752 #endif
 753 #endif
 754
 755 #if GEN_GEN >= 7
 756    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 757    s.Width = (num_elements - 1) & 0x7f;
 758    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 759 #else
 760    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 761    s.Width = (num_elements - 1) & 0x7f;
 762    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 763 #endif
 764
 765    s.SurfacePitch = info->stride_B - 1;
 766
 767 #if GEN_GEN >= 6
 768    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 769 #endif
 770
 771 #if (GEN_GEN >= 8)
 772    s.TileMode = LINEAR;
 773 #else
 774    s.TiledSurface = false;
 775 #endif
 776
 777 #if (GEN_GEN >= 8)
 778    s.RenderCacheReadWriteMode = WriteOnlyCache;
 779 #else
 780    s.RenderCacheReadWriteMode = 0;
 781 #endif
 782
 783    s.SurfaceBaseAddress = info->address;
 784 #if GEN_GEN >= 6
 785    s.MOCS = info->mocs;
 786 #endif
 787
 788 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 789    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
 790    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
 791    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
 792    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 793 #endif
 794
 795    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 796 }
 797
 798 void
 799 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 800 {
 801    struct GENX(RENDER_SURFACE_STATE) s = {
 802       .SurfaceType = SURFTYPE_NULL,
 803       /* We previously had this format set to B8G8R8A8_UNORM but ran into
 804        * hangs on IVB. R32_UINT seems to work for everybody.
 805        *
 806        * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
 807        */
 808       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 809 #if GEN_GEN >= 7
 810       .SurfaceArray = size.depth > 1,
 811 #endif
 812 #if GEN_GEN >= 8
 813       .TileMode = YMAJOR,
 814 #else
 815       .TiledSurface = true,
 816       .TileWalk = TILEWALK_YMAJOR,
 817 #endif
 818 #if GEN_GEN == 7
 819       /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
 820        * Functions"
 821        *
 822        * RENDER_SURFACE_STATE::Surface Vertical Alignment
 823        *
 824        *    "This field must be set to VALIGN_4 for all tiled Y Render Target
 825        *     surfaces."
 826        *
 827        * Affect IVB, HSW.
 828        */
 829       .SurfaceVerticalAlignment = VALIGN_4,
 830 #endif
 831       .Width = size.width - 1,
 832       .Height = size.height - 1,
 833       .Depth = size.depth - 1,
 834       .RenderTargetViewExtent = size.depth - 1,
 835 #if GEN_GEN <= 5
 836       .ColorBufferComponentWriteDisables = 0xf,
 837 #endif
 838    };
 839    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 840 }