src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75 #if GEN_GEN <= 11
  76    [ISL_TILING_W]       = WMAJOR,
  77 #endif
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 12
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94    [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
  95    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
  96    [ISL_AUX_USAGE_STC_CCS] = AUX_CCS_E,
  97 };
  98 #elif GEN_GEN >= 9
  99 static const uint32_t isl_to_gen_aux_mode[] = {
 100    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 101    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 102    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
 103    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
 104    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
 105 };
 106 #elif GEN_GEN >= 8
 107 static const uint32_t isl_to_gen_aux_mode[] = {
 108    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 109    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 110    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 111    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 112 };
 113 #endif
 114
 115 static uint8_t
 116 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 117 {
 118    switch (dim) {
 119    default:
 120       unreachable("bad isl_surf_dim");
 121    case ISL_SURF_DIM_1D:
 122       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 123       return SURFTYPE_1D;
 124    case ISL_SURF_DIM_2D:
 125       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 126           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 127          /* We need SURFTYPE_CUBE to make cube sampling work */
 128          return SURFTYPE_CUBE;
 129       } else {
 130          /* Everything else (render and storage) treat cubes as plain
 131           * 2D array textures
 132           */
 133          return SURFTYPE_2D;
 134       }
 135    case ISL_SURF_DIM_3D:
 136       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 137       return SURFTYPE_3D;
 138    }
 139 }
 140
 141 /**
 142  * Get the horizontal and vertical alignment in the units expected by the
 143  * hardware.  Note that this does NOT give you the actual hardware enum values
 144  * but an index into the isl_to_gen_[hv]align arrays above.
 145  */
 146 UNUSED static struct isl_extent3d
 147 get_image_alignment(const struct isl_surf *surf)
 148 {
 149    if (GEN_GEN >= 9) {
 150       if (isl_tiling_is_std_y(surf->tiling) ||
 151           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 152          /* The hardware ignores the alignment values. Anyway, the surface's
 153           * true alignment is likely outside the enum range of HALIGN* and
 154           * VALIGN*.
 155           */
 156          return isl_extent3d(4, 4, 1);
 157       } else {
 158          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 159           * of surface elements (not pixels nor samples). For compressed formats,
 160           * a "surface element" is defined as a compression block.  For example,
 161           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 162           * format (ETC2 has a block height of 4), then the vertical alignment is
 163           * 4 compression blocks or, equivalently, 16 pixels.
 164           */
 165          return isl_surf_get_image_alignment_el(surf);
 166       }
 167    } else {
 168       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 169        * units of surface samples.  For example, if SurfaceVerticalAlignment
 170        * is VALIGN_4 and the surface is singlesampled, then for any surface
 171        * format (compressed or not) the vertical alignment is
 172        * 4 pixels.
 173        */
 174       return isl_surf_get_image_alignment_sa(surf);
 175    }
 176 }
 177
 178 #if GEN_GEN >= 8
 179 static uint32_t
 180 get_qpitch(const struct isl_surf *surf)
 181 {
 182    switch (surf->dim_layout) {
 183    default:
 184       unreachable("Bad isl_surf_dim");
 185    case ISL_DIM_LAYOUT_GEN4_2D:
 186       if (GEN_GEN >= 9) {
 187          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 188             /* This is rather annoying and completely undocumented.  It
 189              * appears that the hardware has a bug (or undocumented feature)
 190              * regarding stencil buffers most likely related to the way
 191              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 192              * stencil buffer normally, and use texelFetch on it, the z or
 193              * array index will get implicitly multiplied by 2 for no obvious
 194              * reason.  The fix appears to be to divide qpitch by 2 for
 195              * W-tiled surfaces.
 196              */
 197             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 198          } else {
 199             return isl_surf_get_array_pitch_el_rows(surf);
 200          }
 201       } else {
 202          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 203           *
 204           *    "This field must be set to an integer multiple of the Surface
 205           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 206           *    ETC*, and EAC* Surface Formats), this field is in units of
 207           *    rows in the uncompressed surface, and must be set to an
 208           *    integer multiple of the vertical alignment parameter "j"
 209           *    defined in the Common Surface Formats section."
 210           */
 211          return isl_surf_get_array_pitch_sa_rows(surf);
 212       }
 213    case ISL_DIM_LAYOUT_GEN9_1D:
 214       /* QPitch is usually expressed as rows of surface elements (where
 215        * a surface element is an compression block or a single surface
 216        * sample). Skylake 1D is an outlier.
 217        *
 218        * From the Skylake BSpec >> Memory Views >> Common Surface
 219        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 220        *
 221        *    Surface QPitch specifies the distance in pixels between array
 222        *    slices.
 223        */
 224       return isl_surf_get_array_pitch_el(surf);
 225    case ISL_DIM_LAYOUT_GEN4_3D:
 226       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 227        * different pitch at each LOD.  Also, the QPitch field is ignored for
 228        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 229        *
 230        *    This field specifies the distance in rows between array slices. It
 231        *    is used only in the following cases:
 232        *     - Surface Array is enabled OR
 233        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 234        *       Surface Storage Format set to MSFMT_MSS OR
 235        *     - Surface Type is SURFTYPE_CUBE
 236        *
 237        * None of the three conditions above can possibly apply to a 3D surface
 238        * so it is safe to just set QPitch to 0.
 239        */
 240       return 0;
 241    }
 242 }
 243 #endif /* GEN_GEN >= 8 */
 244
 245 void
 246 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 247                             const struct isl_surf_fill_state_info *restrict info)
 248 {
 249    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 250
 251    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 252
 253    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 254       assert(isl_format_supports_rendering(dev->info, info->view->format));
 255    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 256       assert(isl_format_supports_sampling(dev->info, info->view->format));
 257
 258    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 259     *
 260     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 261     *    format if the Surface Type is SURFTYPE_1D
 262     */
 263    if (info->surf->dim == ISL_SURF_DIM_1D)
 264       assert(!isl_format_is_compressed(info->view->format));
 265
 266    if (isl_format_is_compressed(info->surf->format)) {
 267       /* You're not allowed to make a view of a compressed format with any
 268        * format other than the surface format.  None of the userspace APIs
 269        * allow for this directly and doing so would mess up a number of
 270        * surface parameters such as Width, Height, and alignments.  Ideally,
 271        * we'd like to assert that the two formats match.  However, we have an
 272        * S3TC workaround that requires us to do reinterpretation.  So assert
 273        * that they're at least the same bpb and block size.
 274        */
 275       ASSERTED const struct isl_format_layout *surf_fmtl =
 276          isl_format_get_layout(info->surf->format);
 277       ASSERTED const struct isl_format_layout *view_fmtl =
 278          isl_format_get_layout(info->surf->format);
 279       assert(surf_fmtl->bpb == view_fmtl->bpb);
 280       assert(surf_fmtl->bw == view_fmtl->bw);
 281       assert(surf_fmtl->bh == view_fmtl->bh);
 282    }
 283
 284    s.SurfaceFormat = info->view->format;
 285
 286 #if GEN_GEN >= 12
 287    s.DepthStencilResource =
 288       isl_surf_usage_is_depth_or_stencil(info->surf->usage);
 289 #endif
 290
 291 #if GEN_GEN <= 5
 292    s.ColorBufferComponentWriteDisables = info->write_disables;
 293 #else
 294    assert(info->write_disables == 0);
 295 #endif
 296
 297 #if GEN_IS_HASWELL
 298    s.IntegerSurfaceFormat =
 299       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 300 #endif
 301
 302    assert(info->surf->logical_level0_px.width > 0 &&
 303           info->surf->logical_level0_px.height > 0);
 304
 305    s.Width = info->surf->logical_level0_px.width - 1;
 306    s.Height = info->surf->logical_level0_px.height - 1;
 307
 308    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 309     * (Surface Arrays For all surfaces other than separate stencil buffer):
 310     *
 311     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 312     *  calculated in the equation above , for every other odd Surface Height
 313     *  starting from 1 i.e. 1,5,9,13"
 314     *
 315     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 316     * input for the rendering surface to achieve the same qpitch. For the
 317     * affected heights, we increment the height by 1 for the rendering
 318     * surface.
 319     */
 320    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 321        info->surf->samples > 1 &&
 322        (info->surf->logical_level0_px.height % 4) == 1)
 323       s.Height++;
 324
 325    switch (s.SurfaceType) {
 326    case SURFTYPE_1D:
 327    case SURFTYPE_2D:
 328       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 329        *
 330        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 331        *    must be set to zero if this surface is used with sampling engine
 332        *    messages."
 333        *
 334        * This restriction appears to exist only on Ivy Bridge.
 335        */
 336       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 337           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 338           info->surf->samples > 1)
 339          assert(info->view->base_array_layer == 0);
 340
 341       s.MinimumArrayElement = info->view->base_array_layer;
 342
 343       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 344        *
 345        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 346        *    by one for each increase from zero of Minimum Array Element. For
 347        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 348        *    the range of this field is reduced to [0,1023].
 349        *
 350        * In other words, 'Depth' is the number of array layers.
 351        */
 352       s.Depth = info->view->array_len - 1;
 353
 354       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 355        *
 356        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 357        *    This field must be set to the same value as the Depth field.
 358        */
 359       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 360                                ISL_SURF_USAGE_STORAGE_BIT))
 361          s.RenderTargetViewExtent = s.Depth;
 362       break;
 363    case SURFTYPE_CUBE:
 364       s.MinimumArrayElement = info->view->base_array_layer;
 365       /* Same as SURFTYPE_2D, but divided by 6 */
 366       s.Depth = info->view->array_len / 6 - 1;
 367       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 368                                ISL_SURF_USAGE_STORAGE_BIT))
 369          s.RenderTargetViewExtent = s.Depth;
 370       break;
 371    case SURFTYPE_3D:
 372       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 373        *
 374        *    If the volume texture is MIP-mapped, this field specifies the
 375        *    depth of the base MIP level.
 376        */
 377       s.Depth = info->surf->logical_level0_px.depth - 1;
 378
 379       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 380        *
 381        *    For Render Target and Typed Dataport 3D Surfaces: This field
 382        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 383        *    the LOD currently being rendered to.
 384        *
 385        * The docs specify that this only matters for render targets and
 386        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 387        * Depth field has more bits than RenderTargetViewExtent so we can have
 388        * textures with more levels than we can render to.  In order to prevent
 389        * assert-failures in the packing function below, we only set the field
 390        * when it's actually going to be used by the hardware.
 391        *
 392        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 393        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 394        * Since it's already initialized to 0, we can just leave it alone for
 395        * texture surfaces.
 396        */
 397       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 398                                ISL_SURF_USAGE_STORAGE_BIT)) {
 399          s.MinimumArrayElement = info->view->base_array_layer;
 400          s.RenderTargetViewExtent = info->view->array_len - 1;
 401       }
 402       break;
 403    default:
 404       unreachable("bad SurfaceType");
 405    }
 406
 407 #if GEN_GEN >= 12
 408    /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
 409    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
 410       info->view->array_len > 1;
 411 #elif GEN_GEN >= 7
 412    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 413 #endif
 414
 415    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 416       /* For render target surfaces, the hardware interprets field
 417        * MIPCount/LOD as LOD. The Broadwell PRM says:
 418        *
 419        *    MIPCountLOD defines the LOD that will be rendered into.
 420        *    SurfaceMinLOD is ignored.
 421        */
 422       s.MIPCountLOD = info->view->base_level;
 423       s.SurfaceMinLOD = 0;
 424    } else {
 425       /* For non render target surfaces, the hardware interprets field
 426        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 427        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 428        */
 429       s.SurfaceMinLOD = info->view->base_level;
 430       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 431    }
 432
 433 #if GEN_GEN >= 9
 434    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 435     * Start LOD" to 15 to prevent the hardware from trying to use them.
 436     */
 437    s.TiledResourceMode = NONE;
 438    s.MipTailStartLOD = 15;
 439 #endif
 440
 441 #if GEN_GEN >= 6
 442    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 443    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 444 #if GEN_GEN >= 7
 445    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 446 #endif
 447 #endif
 448
 449    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 450       /* For gen9 1-D textures, surface pitch is ignored */
 451       s.SurfacePitch = 0;
 452    } else {
 453       s.SurfacePitch = info->surf->row_pitch_B - 1;
 454    }
 455
 456 #if GEN_GEN >= 8
 457    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 458 #elif GEN_GEN == 7
 459    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 460                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 461 #endif
 462
 463 #if GEN_GEN >= 8
 464    assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
 465    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 466 #else
 467    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 468    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 469                                                       TILEWALK_XMAJOR,
 470 #endif
 471
 472 #if GEN_GEN >= 8
 473    s.RenderCacheReadWriteMode = WriteOnlyCache;
 474 #else
 475    s.RenderCacheReadWriteMode = 0;
 476 #endif
 477
 478 #if GEN_GEN >= 11
 479    /* We've seen dEQP failures when enabling this bit with UINT formats,
 480     * which particularly affects blorp_copy() operations.  It shouldn't
 481     * have any effect on UINT textures anyway, so disable it for them.
 482     */
 483    s.EnableUnormPathInColorPipe =
 484       !isl_format_has_int_channel(info->view->format);
 485 #endif
 486
 487    s.CubeFaceEnablePositiveZ = 1;
 488    s.CubeFaceEnableNegativeZ = 1;
 489    s.CubeFaceEnablePositiveY = 1;
 490    s.CubeFaceEnableNegativeY = 1;
 491    s.CubeFaceEnablePositiveX = 1;
 492    s.CubeFaceEnableNegativeX = 1;
 493
 494 #if GEN_GEN >= 6
 495    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 496 #if GEN_GEN >= 7
 497    s.MultisampledSurfaceStorageFormat =
 498       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 499 #endif
 500 #endif
 501
 502 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 503    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 504       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 505
 506    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 507    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 508    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 509    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 510 #else
 511    assert(isl_swizzle_is_identity(info->view->swizzle));
 512 #endif
 513
 514    s.SurfaceBaseAddress = info->address;
 515
 516 #if GEN_GEN >= 6
 517    s.MOCS = info->mocs;
 518 #endif
 519
 520 #if GEN_GEN > 4 || GEN_IS_G4X
 521    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 522       /* There are fairly strict rules about when the offsets can be used.
 523        * These are mostly taken from the Sky Lake PRM documentation for
 524        * RENDER_SURFACE_STATE.
 525        */
 526       assert(info->surf->tiling != ISL_TILING_LINEAR);
 527       assert(info->surf->dim == ISL_SURF_DIM_2D);
 528       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 529       assert(info->surf->levels == 1);
 530       assert(info->surf->logical_level0_px.array_len == 1);
 531       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 532
 533       if (GEN_GEN >= 8) {
 534          /* Broadwell added more rules. */
 535          assert(info->surf->samples == 1);
 536          if (isl_format_get_layout(info->view->format)->bpb == 8)
 537             assert(info->x_offset_sa % 16 == 0);
 538          if (isl_format_get_layout(info->view->format)->bpb == 16)
 539             assert(info->x_offset_sa % 8 == 0);
 540       }
 541
 542 #if GEN_GEN >= 7
 543       s.SurfaceArray = false;
 544 #endif
 545    }
 546
 547    const unsigned x_div = 4;
 548    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 549    assert(info->x_offset_sa % x_div == 0);
 550    assert(info->y_offset_sa % y_div == 0);
 551    s.XOffset = info->x_offset_sa / x_div;
 552    s.YOffset = info->y_offset_sa / y_div;
 553 #else
 554    assert(info->x_offset_sa == 0);
 555    assert(info->y_offset_sa == 0);
 556 #endif
 557
 558 #if GEN_GEN >= 7
 559    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 560       /* Check valid aux usages per-gen */
 561       if (GEN_GEN >= 12) {
 562          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 563                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
 564                 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
 565                 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
 566                 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
 567       } else if (GEN_GEN >= 9) {
 568          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 569                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 570                 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
 571                 info->aux_usage == ISL_AUX_USAGE_CCS_E);
 572       } else if (GEN_GEN >= 8) {
 573          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 574                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 575                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 576       } else if (GEN_GEN >= 7) {
 577          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 578                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 579       }
 580
 581       /* The docs don't appear to say anything whatsoever about compression
 582        * and the data port.  Testing seems to indicate that the data port
 583        * completely ignores the AuxiliarySurfaceMode field.
 584        */
 585       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 586
 587       if (isl_surf_usage_is_depth(info->surf->usage))
 588          assert(isl_aux_usage_has_hiz(info->aux_usage));
 589
 590       if (isl_surf_usage_is_stencil(info->surf->usage))
 591          assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
 592
 593       if (isl_aux_usage_has_hiz(info->aux_usage)) {
 594          /* For Gen8-10, there are some restrictions around sampling from HiZ.
 595           * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 596           * say:
 597           *
 598           *    "If this field is set to AUX_HIZ, Number of Multisamples must
 599           *    be MULTISAMPLECOUNT_1, and Surface Type cannot be SURFTYPE_3D."
 600           *
 601           * On Gen12, the docs are a bit less obvious but the restriction is
 602           * the same.  The limitation isn't called out explicitly but the docs
 603           * for the CCS_E value of RENDER_SURFACE_STATE::AuxiliarySurfaceMode
 604           * say:
 605           *
 606           *    "If Number of multisamples > 1, programming this value means
 607           *    MSAA compression is enabled for that surface. Auxillary surface
 608           *    is MSC with tile y."
 609           *
 610           * Since this interpretation ignores whether the surface is
 611           * depth/stencil or not and since multisampled depth buffers use
 612           * ISL_MSAA_LAYOUT_INTERLEAVED which is incompatible with MCS
 613           * compression, this means that we can't even specify MSAA depth CCS
 614           * in RENDER_SURFACE_STATE::AuxiliarySurfaceMode.
 615           */
 616          assert(info->surf->samples == 1);
 617
 618          /* The dimension must not be 3D */
 619          assert(info->surf->dim != ISL_SURF_DIM_3D);
 620
 621          /* The format must be one of the following: */
 622          switch (info->view->format) {
 623          case ISL_FORMAT_R32_FLOAT:
 624          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 625          case ISL_FORMAT_R16_UNORM:
 626             break;
 627          default:
 628             assert(!"Incompatible HiZ Sampling format");
 629             break;
 630          }
 631       }
 632
 633 #if GEN_GEN >= 8
 634       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 635 #else
 636       s.MCSEnable = true;
 637 #endif
 638    }
 639
 640    /* The auxiliary buffer info is filled when it's useable by the HW.
 641     *
 642     * Starting with Gen12, the only form of compression that can be used
 643     * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
 644     * HiZ still requires a surface but the HiZ surface can only be
 645     * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
 646     *
 647     * On all earlier hardware, an aux surface is required for all forms
 648     * of compression.
 649     */
 650    if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
 651        (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
 652
 653       assert(info->aux_surf != NULL);
 654
 655       struct isl_tile_info tile_info;
 656       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 657       uint32_t pitch_in_tiles =
 658          info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 659
 660       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 661       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 662
 663 #if GEN_GEN >= 8
 664       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 665        * doesn't expect our definition of the compression, it expects qpitch
 666        * in units of samples on the main surface.
 667        */
 668       s.AuxiliarySurfaceQPitch =
 669          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 670 #endif
 671    }
 672 #endif
 673
 674 #if GEN_GEN >= 8 && GEN_GEN < 11
 675    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 676     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 677     *
 678     *    This bit must be set for the following surface types: BC2_UNORM
 679     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 680     */
 681    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 682       switch (info->view->format) {
 683       case ISL_FORMAT_BC2_UNORM:
 684       case ISL_FORMAT_BC3_UNORM:
 685       case ISL_FORMAT_BC5_UNORM:
 686       case ISL_FORMAT_BC5_SNORM:
 687       case ISL_FORMAT_BC7_UNORM:
 688          s.SamplerL2BypassModeDisable = true;
 689          break;
 690       default:
 691          /* From the SKL PRM, Programming Note under Sampler Output Channel
 692           * Mapping:
 693           *
 694           *    If a surface has an associated HiZ Auxilliary surface, the
 695           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 696           *    must be set.
 697           */
 698          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 699             s.SamplerL2BypassModeDisable = true;
 700          break;
 701       }
 702    }
 703 #endif
 704
 705    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 706       if (info->use_clear_address) {
 707 #if GEN_GEN >= 10
 708          s.ClearValueAddressEnable = true;
 709          s.ClearValueAddress = info->clear_address;
 710 #else
 711          unreachable("Gen9 and earlier do not support indirect clear colors");
 712 #endif
 713       }
 714
 715 #if GEN_GEN == 11
 716       /*
 717        * From BXML > GT > Shared Functions > vol5c Shared Functions >
 718        * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
 719        *
 720        *   Project: Gen11
 721        *
 722        *   "Enables Pixel backend hw to convert clear values into native format
 723        *    and write back to clear address, so that display and sampler can use
 724        *    the converted value for resolving fast cleared RTs."
 725        *
 726        * Summary:
 727        *   Clear color conversion must be enabled if the clear color is stored
 728        *   indirectly and fast color clears are enabled.
 729        */
 730       if (info->use_clear_address) {
 731          s.ClearColorConversionEnable = true;
 732       }
 733 #endif
 734
 735 #if GEN_GEN >= 12
 736       assert(info->use_clear_address);
 737 #elif GEN_GEN >= 9
 738       if (!info->use_clear_address) {
 739          s.RedClearColor = info->clear_color.u32[0];
 740          s.GreenClearColor = info->clear_color.u32[1];
 741          s.BlueClearColor = info->clear_color.u32[2];
 742          s.AlphaClearColor = info->clear_color.u32[3];
 743       }
 744 #elif GEN_GEN >= 7
 745       /* Prior to Sky Lake, we only have one bit for the clear color which
 746        * gives us 0 or 1 in whatever the surface's format happens to be.
 747        */
 748       if (isl_format_has_int_channel(info->view->format)) {
 749          for (unsigned i = 0; i < 4; i++) {
 750             assert(info->clear_color.u32[i] == 0 ||
 751                    info->clear_color.u32[i] == 1);
 752          }
 753          s.RedClearColor = info->clear_color.u32[0] != 0;
 754          s.GreenClearColor = info->clear_color.u32[1] != 0;
 755          s.BlueClearColor = info->clear_color.u32[2] != 0;
 756          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 757       } else {
 758          for (unsigned i = 0; i < 4; i++) {
 759             assert(info->clear_color.f32[i] == 0.0f ||
 760                    info->clear_color.f32[i] == 1.0f);
 761          }
 762          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 763          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 764          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 765          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 766       }
 767 #endif
 768    }
 769
 770    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 771 }
 772
 773 void
 774 isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
 775                               const struct isl_buffer_fill_state_info *restrict info)
 776 {
 777    uint64_t buffer_size = info->size_B;
 778
 779    /* Uniform and Storage buffers need to have surface size not less that the
 780     * aligned 32-bit size of the buffer. To calculate the array lenght on
 781     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 782     * added to the surface, so we can calculate latter the original buffer
 783     * size to know the number of elements.
 784     *
 785     *  surface_size = isl_align(buffer_size, 4) +
 786     *                 (isl_align(buffer_size) - buffer_size)
 787     *
 788     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 789     */
 790    if (info->format == ISL_FORMAT_RAW  ||
 791        info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
 792       assert(info->stride_B == 1);
 793       uint64_t aligned_size = isl_align(buffer_size, 4);
 794       buffer_size = aligned_size + (aligned_size - buffer_size);
 795    }
 796
 797    uint32_t num_elements = buffer_size / info->stride_B;
 798
 799    if (GEN_GEN >= 7) {
 800       /* From the IVB PRM, SURFACE_STATE::Height,
 801        *
 802        *    For typed buffer and structured buffer surfaces, the number
 803        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 804        *    surfaces, the number of entries in the buffer is the number of bytes
 805        *    which can range from 1 to 2^30.
 806        */
 807       if (info->format == ISL_FORMAT_RAW) {
 808          assert(num_elements <= (1ull << 30));
 809          assert(num_elements > 0);
 810       } else {
 811          assert(num_elements <= (1ull << 27));
 812       }
 813    } else {
 814       assert(num_elements <= (1ull << 27));
 815    }
 816
 817    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 818
 819    s.SurfaceType = SURFTYPE_BUFFER;
 820    s.SurfaceFormat = info->format;
 821
 822 #if GEN_GEN >= 6
 823    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 824 #if GEN_GEN >= 7
 825    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 826    s.SurfaceArray = false;
 827 #endif
 828 #endif
 829
 830 #if GEN_GEN >= 7
 831    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 832    s.Width = (num_elements - 1) & 0x7f;
 833    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 834 #else
 835    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 836    s.Width = (num_elements - 1) & 0x7f;
 837    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 838 #endif
 839
 840    if (GEN_GEN == 12 && dev->info->revision == 0) {
 841       /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
 842        * textures with very close base addresses (delta < 64B) to corrupt each
 843        * other.  We can sort-of work around this by making small buffer
 844        * textures 1D textures instead.  This doesn't fix the problem for large
 845        * buffer textures but the liklihood of large, overlapping, and very
 846        * close buffer textures is fairly low and the point is to hack around
 847        * the bug so we can run apps and tests.
 848        */
 849        if (info->format != ISL_FORMAT_RAW &&
 850            info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
 851            num_elements <= (1 << 14)) {
 852          s.SurfaceType = SURFTYPE_1D;
 853          s.Width = num_elements - 1;
 854          s.Height = 0;
 855          s.Depth = 0;
 856       }
 857    }
 858
 859    s.SurfacePitch = info->stride_B - 1;
 860
 861 #if GEN_GEN >= 6
 862    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 863 #endif
 864
 865 #if (GEN_GEN >= 8)
 866    s.TileMode = LINEAR;
 867 #else
 868    s.TiledSurface = false;
 869 #endif
 870
 871 #if (GEN_GEN >= 8)
 872    s.RenderCacheReadWriteMode = WriteOnlyCache;
 873 #else
 874    s.RenderCacheReadWriteMode = 0;
 875 #endif
 876
 877    s.SurfaceBaseAddress = info->address;
 878 #if GEN_GEN >= 6
 879    s.MOCS = info->mocs;
 880 #endif
 881
 882 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 883    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
 884    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
 885    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
 886    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 887 #endif
 888
 889    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 890 }
 891
 892 void
 893 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 894 {
 895    struct GENX(RENDER_SURFACE_STATE) s = {
 896       .SurfaceType = SURFTYPE_NULL,
 897       /* We previously had this format set to B8G8R8A8_UNORM but ran into
 898        * hangs on IVB. R32_UINT seems to work for everybody.
 899        *
 900        * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
 901        */
 902       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 903 #if GEN_GEN >= 7
 904       .SurfaceArray = size.depth > 1,
 905 #endif
 906 #if GEN_GEN >= 8
 907       .TileMode = YMAJOR,
 908 #else
 909       .TiledSurface = true,
 910       .TileWalk = TILEWALK_YMAJOR,
 911 #endif
 912 #if GEN_GEN == 7
 913       /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
 914        * Functions"
 915        *
 916        * RENDER_SURFACE_STATE::Surface Vertical Alignment
 917        *
 918        *    "This field must be set to VALIGN_4 for all tiled Y Render Target
 919        *     surfaces."
 920        *
 921        * Affect IVB, HSW.
 922        */
 923       .SurfaceVerticalAlignment = VALIGN_4,
 924 #endif
 925       .Width = size.width - 1,
 926       .Height = size.height - 1,
 927       .Depth = size.depth - 1,
 928       .RenderTargetViewExtent = size.depth - 1,
 929 #if GEN_GEN <= 5
 930       .ColorBufferComponentWriteDisables = 0xf,
 931 #endif
 932    };
 933    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 934 }