2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
29 static inline uint64_t
30 __gen_combine_address(void *data
, void *loc
, uint64_t addr
, uint32_t delta
)
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
41 static const uint8_t isl_to_gen_halign
[] = {
47 static const uint8_t isl_to_gen_halign
[] = {
54 static const uint8_t isl_to_gen_valign
[] = {
60 static const uint8_t isl_to_gen_valign
[] = {
67 static const uint8_t isl_to_gen_tiling
[] = {
68 [ISL_TILING_LINEAR
] = LINEAR
,
69 [ISL_TILING_X
] = XMAJOR
,
70 [ISL_TILING_Y0
] = YMAJOR
,
71 [ISL_TILING_Yf
] = YMAJOR
,
72 [ISL_TILING_Ys
] = YMAJOR
,
73 [ISL_TILING_W
] = WMAJOR
,
78 static const uint32_t isl_to_gen_multisample_layout
[] = {
79 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
80 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
81 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
86 static const uint32_t isl_to_gen_aux_mode
[] = {
87 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
88 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
89 [ISL_AUX_USAGE_MCS
] = AUX_CCS_D
,
90 [ISL_AUX_USAGE_CCS_D
] = AUX_CCS_D
,
91 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
94 static const uint32_t isl_to_gen_aux_mode
[] = {
95 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
96 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
97 [ISL_AUX_USAGE_MCS
] = AUX_MCS
,
98 [ISL_AUX_USAGE_CCS_D
] = AUX_MCS
,
103 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
107 unreachable("bad isl_surf_dim");
108 case ISL_SURF_DIM_1D
:
109 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
111 case ISL_SURF_DIM_2D
:
112 if ((usage
& ISL_SURF_USAGE_CUBE_BIT
) &&
113 (usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
114 /* We need SURFTYPE_CUBE to make cube sampling work */
115 return SURFTYPE_CUBE
;
117 /* Everything else (render and storage) treat cubes as plain
122 case ISL_SURF_DIM_3D
:
123 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
129 * Get the horizontal and vertical alignment in the units expected by the
130 * hardware. Note that this does NOT give you the actual hardware enum values
131 * but an index into the isl_to_gen_[hv]align arrays above.
133 static inline struct isl_extent3d
134 get_image_alignment(const struct isl_surf
*surf
)
137 if (isl_tiling_is_std_y(surf
->tiling
) ||
138 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
139 /* The hardware ignores the alignment values. Anyway, the surface's
140 * true alignment is likely outside the enum range of HALIGN* and
143 return isl_extent3d(4, 4, 1);
145 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
146 * of surface elements (not pixels nor samples). For compressed formats,
147 * a "surface element" is defined as a compression block. For example,
148 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
149 * format (ETC2 has a block height of 4), then the vertical alignment is
150 * 4 compression blocks or, equivalently, 16 pixels.
152 return isl_surf_get_image_alignment_el(surf
);
155 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
156 * units of surface samples. For example, if SurfaceVerticalAlignment
157 * is VALIGN_4 and the surface is singlesampled, then for any surface
158 * format (compressed or not) the vertical alignment is
161 return isl_surf_get_image_alignment_sa(surf
);
167 get_qpitch(const struct isl_surf
*surf
)
169 switch (surf
->dim_layout
) {
171 unreachable("Bad isl_surf_dim");
172 case ISL_DIM_LAYOUT_GEN4_2D
:
174 if (surf
->dim
== ISL_SURF_DIM_3D
&& surf
->tiling
== ISL_TILING_W
) {
175 /* This is rather annoying and completely undocumented. It
176 * appears that the hardware has a bug (or undocumented feature)
177 * regarding stencil buffers most likely related to the way
178 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
179 * stencil buffer normally, and use texelFetch on it, the z or
180 * array index will get implicitly multiplied by 2 for no obvious
181 * reason. The fix appears to be to divide qpitch by 2 for
184 return isl_surf_get_array_pitch_el_rows(surf
) / 2;
186 return isl_surf_get_array_pitch_el_rows(surf
);
189 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
191 * "This field must be set to an integer multiple of the Surface
192 * Vertical Alignment. For compressed textures (BC*, FXT1,
193 * ETC*, and EAC* Surface Formats), this field is in units of
194 * rows in the uncompressed surface, and must be set to an
195 * integer multiple of the vertical alignment parameter "j"
196 * defined in the Common Surface Formats section."
198 return isl_surf_get_array_pitch_sa_rows(surf
);
200 case ISL_DIM_LAYOUT_GEN9_1D
:
201 /* QPitch is usually expressed as rows of surface elements (where
202 * a surface element is an compression block or a single surface
203 * sample). Skylake 1D is an outlier.
205 * From the Skylake BSpec >> Memory Views >> Common Surface
206 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
208 * Surface QPitch specifies the distance in pixels between array
211 return isl_surf_get_array_pitch_el(surf
);
212 case ISL_DIM_LAYOUT_GEN4_3D
:
213 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
214 * different pitch at each LOD. Also, the QPitch field is ignored for
215 * these surfaces. From the Broadwell PRM documentation for QPitch:
217 * This field specifies the distance in rows between array slices. It
218 * is used only in the following cases:
219 * - Surface Array is enabled OR
220 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
221 * Surface Storage Format set to MSFMT_MSS OR
222 * - Surface Type is SURFTYPE_CUBE
224 * None of the three conditions above can possibly apply to a 3D surface
225 * so it is safe to just set QPitch to 0.
230 #endif /* GEN_GEN >= 8 */
233 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
234 const struct isl_surf_fill_state_info
*restrict info
)
236 struct GENX(RENDER_SURFACE_STATE
) s
= { 0 };
238 s
.SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
);
240 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
241 assert(isl_format_supports_rendering(dev
->info
, info
->view
->format
));
242 else if (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
)
243 assert(isl_format_supports_sampling(dev
->info
, info
->view
->format
));
245 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
247 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
248 * format if the Surface Type is SURFTYPE_1D
250 if (info
->surf
->dim
== ISL_SURF_DIM_1D
)
251 assert(!isl_format_is_compressed(info
->view
->format
));
253 if (isl_format_is_compressed(info
->surf
->format
)) {
254 /* You're not allowed to make a view of a compressed format with any
255 * format other than the surface format. None of the userspace APIs
256 * allow for this directly and doing so would mess up a number of
257 * surface parameters such as Width, Height, and alignments. Ideally,
258 * we'd like to assert that the two formats match. However, we have an
259 * S3TC workaround that requires us to do reinterpretation. So assert
260 * that they're at least the same bpb and block size.
262 MAYBE_UNUSED
const struct isl_format_layout
*surf_fmtl
=
263 isl_format_get_layout(info
->surf
->format
);
264 MAYBE_UNUSED
const struct isl_format_layout
*view_fmtl
=
265 isl_format_get_layout(info
->surf
->format
);
266 assert(surf_fmtl
->bpb
== view_fmtl
->bpb
);
267 assert(surf_fmtl
->bw
== view_fmtl
->bw
);
268 assert(surf_fmtl
->bh
== view_fmtl
->bh
);
271 s
.SurfaceFormat
= info
->view
->format
;
274 s
.ColorBufferComponentWriteDisables
= info
->write_disables
;
276 assert(info
->write_disables
== 0);
280 s
.IntegerSurfaceFormat
= isl_format_has_int_channel(s
.SurfaceFormat
);
283 assert(info
->surf
->logical_level0_px
.width
> 0 &&
284 info
->surf
->logical_level0_px
.height
> 0);
286 s
.Width
= info
->surf
->logical_level0_px
.width
- 1;
287 s
.Height
= info
->surf
->logical_level0_px
.height
- 1;
289 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
290 * (Surface Arrays For all surfaces other than separate stencil buffer):
292 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
293 * calculated in the equation above , for every other odd Surface Height
294 * starting from 1 i.e. 1,5,9,13"
296 * Since this Qpitch errata only impacts the sampler, we have to adjust the
297 * input for the rendering surface to achieve the same qpitch. For the
298 * affected heights, we increment the height by 1 for the rendering
301 if (GEN_GEN
== 6 && (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
302 info
->surf
->samples
> 1 &&
303 (info
->surf
->logical_level0_px
.height
% 4) == 1)
306 switch (s
.SurfaceType
) {
309 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
311 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
312 * must be set to zero if this surface is used with sampling engine
315 * This restriction appears to exist only on Ivy Bridge.
317 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !ISL_DEV_IS_BAYTRAIL(dev
) &&
318 (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
) &&
319 info
->surf
->samples
> 1)
320 assert(info
->view
->base_array_layer
== 0);
322 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
324 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
326 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
327 * by one for each increase from zero of Minimum Array Element. For
328 * example, if Minimum Array Element is set to 1024 on a 2D surface,
329 * the range of this field is reduced to [0,1023].
331 * In other words, 'Depth' is the number of array layers.
333 s
.Depth
= info
->view
->array_len
- 1;
335 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
337 * For Render Target and Typed Dataport 1D and 2D Surfaces:
338 * This field must be set to the same value as the Depth field.
340 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
341 ISL_SURF_USAGE_STORAGE_BIT
))
342 s
.RenderTargetViewExtent
= s
.Depth
;
345 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
346 /* Same as SURFTYPE_2D, but divided by 6 */
347 s
.Depth
= info
->view
->array_len
/ 6 - 1;
348 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
349 ISL_SURF_USAGE_STORAGE_BIT
))
350 s
.RenderTargetViewExtent
= s
.Depth
;
353 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
355 * If the volume texture is MIP-mapped, this field specifies the
356 * depth of the base MIP level.
358 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
360 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
362 * For Render Target and Typed Dataport 3D Surfaces: This field
363 * indicates the extent of the accessible 'R' coordinates minus 1 on
364 * the LOD currently being rendered to.
366 * The docs specify that this only matters for render targets and
367 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
368 * Depth field has more bits than RenderTargetViewExtent so we can have
369 * textures with more levels than we can render to. In order to prevent
370 * assert-failures in the packing function below, we only set the field
371 * when it's actually going to be used by the hardware.
373 * Similaraly, the MinimumArrayElement field is ignored by all hardware
374 * prior to Sky Lake when texturing and we want it set to 0 anyway.
375 * Since it's already initialized to 0, we can just leave it alone for
378 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
379 ISL_SURF_USAGE_STORAGE_BIT
)) {
380 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
381 s
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
385 unreachable("bad SurfaceType");
389 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
;
392 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
393 /* For render target surfaces, the hardware interprets field
394 * MIPCount/LOD as LOD. The Broadwell PRM says:
396 * MIPCountLOD defines the LOD that will be rendered into.
397 * SurfaceMinLOD is ignored.
399 s
.MIPCountLOD
= info
->view
->base_level
;
402 /* For non render target surfaces, the hardware interprets field
403 * MIPCount/LOD as MIPCount. The range of levels accessible by the
404 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
406 s
.SurfaceMinLOD
= info
->view
->base_level
;
407 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
411 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
412 * Start LOD" to 15 to prevent the hardware from trying to use them.
414 s
.TiledResourceMode
= NONE
;
415 s
.MipTailStartLOD
= 15;
419 const struct isl_extent3d image_align
= get_image_alignment(info
->surf
);
420 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[image_align
.height
];
422 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[image_align
.width
];
426 if (info
->surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
427 /* For gen9 1-D textures, surface pitch is ignored */
430 s
.SurfacePitch
= info
->surf
->row_pitch
- 1;
434 s
.SurfaceQPitch
= get_qpitch(info
->surf
) >> 2;
436 s
.SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
437 ISL_ARRAY_PITCH_SPAN_COMPACT
;
441 s
.TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
];
443 s
.TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
444 s
.TileWalk
= info
->surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
449 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
451 s
.RenderCacheReadWriteMode
= 0;
454 if (info
->view
->usage
& ISL_SURF_USAGE_CUBE_BIT
) {
456 s
.CubeFaceEnablePositiveZ
= 1;
457 s
.CubeFaceEnableNegativeZ
= 1;
458 s
.CubeFaceEnablePositiveY
= 1;
459 s
.CubeFaceEnableNegativeY
= 1;
460 s
.CubeFaceEnablePositiveX
= 1;
461 s
.CubeFaceEnableNegativeX
= 1;
463 s
.CubeFaceEnables
= 0x3f;
468 s
.NumberofMultisamples
= ffs(info
->surf
->samples
) - 1;
470 s
.MultisampledSurfaceStorageFormat
=
471 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
];
475 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
476 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
477 /* From the Sky Lake PRM Vol. 2d,
478 * RENDER_SURFACE_STATE::Shader Channel Select Red
480 * "For Render Target, Red, Green and Blue Shader Channel Selects
481 * MUST be such that only valid components can be swapped i.e. only
482 * change the order of components in the pixel. Any other values for
483 * these Shader Channel Select fields are not valid for Render
484 * Targets. This also means that there MUST not be multiple shader
485 * channels mapped to the same RT channel."
487 assert(info
->view
->swizzle
.r
== ISL_CHANNEL_SELECT_RED
||
488 info
->view
->swizzle
.r
== ISL_CHANNEL_SELECT_GREEN
||
489 info
->view
->swizzle
.r
== ISL_CHANNEL_SELECT_BLUE
);
490 assert(info
->view
->swizzle
.g
== ISL_CHANNEL_SELECT_RED
||
491 info
->view
->swizzle
.g
== ISL_CHANNEL_SELECT_GREEN
||
492 info
->view
->swizzle
.g
== ISL_CHANNEL_SELECT_BLUE
);
493 assert(info
->view
->swizzle
.b
== ISL_CHANNEL_SELECT_RED
||
494 info
->view
->swizzle
.b
== ISL_CHANNEL_SELECT_GREEN
||
495 info
->view
->swizzle
.b
== ISL_CHANNEL_SELECT_BLUE
);
496 assert(info
->view
->swizzle
.r
!= info
->view
->swizzle
.g
);
497 assert(info
->view
->swizzle
.r
!= info
->view
->swizzle
.b
);
498 assert(info
->view
->swizzle
.g
!= info
->view
->swizzle
.b
);
500 /* From the Sky Lake PRM Vol. 2d,
501 * RENDER_SURFACE_STATE::Shader Channel Select Alpha
503 * "For Render Target, this field MUST be programmed to
504 * value = SCS_ALPHA."
506 assert(info
->view
->swizzle
.a
== ISL_CHANNEL_SELECT_ALPHA
);
508 s
.ShaderChannelSelectRed
= info
->view
->swizzle
.r
;
509 s
.ShaderChannelSelectGreen
= info
->view
->swizzle
.g
;
510 s
.ShaderChannelSelectBlue
= info
->view
->swizzle
.b
;
511 s
.ShaderChannelSelectAlpha
= info
->view
->swizzle
.a
;
514 s
.SurfaceBaseAddress
= info
->address
;
520 #if GEN_GEN > 4 || GEN_IS_G4X
521 if (info
->x_offset_sa
!= 0 || info
->y_offset_sa
!= 0) {
522 /* There are fairly strict rules about when the offsets can be used.
523 * These are mostly taken from the Sky Lake PRM documentation for
524 * RENDER_SURFACE_STATE.
526 assert(info
->surf
->tiling
!= ISL_TILING_LINEAR
);
527 assert(info
->surf
->dim
== ISL_SURF_DIM_2D
);
528 assert(isl_is_pow2(isl_format_get_layout(info
->view
->format
)->bpb
));
529 assert(info
->surf
->levels
== 1);
530 assert(info
->surf
->logical_level0_px
.array_len
== 1);
531 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
534 /* Broadwell added more rules. */
535 assert(info
->surf
->samples
== 1);
536 if (isl_format_get_layout(info
->view
->format
)->bpb
== 8)
537 assert(info
->x_offset_sa
% 16 == 0);
538 if (isl_format_get_layout(info
->view
->format
)->bpb
== 16)
539 assert(info
->x_offset_sa
% 8 == 0);
543 s
.SurfaceArray
= false;
547 const unsigned x_div
= 4;
548 const unsigned y_div
= GEN_GEN
>= 8 ? 4 : 2;
549 assert(info
->x_offset_sa
% x_div
== 0);
550 assert(info
->y_offset_sa
% y_div
== 0);
551 s
.XOffset
= info
->x_offset_sa
/ x_div
;
552 s
.YOffset
= info
->y_offset_sa
/ y_div
;
554 assert(info
->x_offset_sa
== 0);
555 assert(info
->y_offset_sa
== 0);
559 if (info
->aux_surf
&& info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
560 /* The docs don't appear to say anything whatsoever about compression
561 * and the data port. Testing seems to indicate that the data port
562 * completely ignores the AuxiliarySurfaceMode field.
564 assert(!(info
->view
->usage
& ISL_SURF_USAGE_STORAGE_BIT
));
566 struct isl_tile_info tile_info
;
567 isl_surf_get_tile_info(info
->aux_surf
, &tile_info
);
568 uint32_t pitch_in_tiles
=
569 info
->aux_surf
->row_pitch
/ tile_info
.phys_extent_B
.width
;
571 s
.AuxiliarySurfaceBaseAddress
= info
->aux_address
;
572 s
.AuxiliarySurfacePitch
= pitch_in_tiles
- 1;
575 assert(GEN_GEN
>= 9 || info
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
576 /* Auxiliary surfaces in ISL have compressed formats but the hardware
577 * doesn't expect our definition of the compression, it expects qpitch
578 * in units of samples on the main surface.
580 s
.AuxiliarySurfaceQPitch
=
581 isl_surf_get_array_pitch_sa_rows(info
->aux_surf
) >> 2;
583 if (info
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
584 /* The number of samples must be 1 */
585 assert(info
->surf
->samples
== 1);
587 /* The dimension must not be 3D */
588 assert(info
->surf
->dim
!= ISL_SURF_DIM_3D
);
590 /* The format must be one of the following: */
591 switch (info
->view
->format
) {
592 case ISL_FORMAT_R32_FLOAT
:
593 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
594 case ISL_FORMAT_R16_UNORM
:
597 assert(!"Incompatible HiZ Sampling format");
602 s
.AuxiliarySurfaceMode
= isl_to_gen_aux_mode
[info
->aux_usage
];
604 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
605 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
612 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
613 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
615 * This bit must be set for the following surface types: BC2_UNORM
616 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
618 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
619 switch (info
->view
->format
) {
620 case ISL_FORMAT_BC2_UNORM
:
621 case ISL_FORMAT_BC3_UNORM
:
622 case ISL_FORMAT_BC5_UNORM
:
623 case ISL_FORMAT_BC5_SNORM
:
624 case ISL_FORMAT_BC7_UNORM
:
625 s
.SamplerL2BypassModeDisable
= true;
628 /* From the SKL PRM, Programming Note under Sampler Output Channel
631 * If a surface has an associated HiZ Auxilliary surface, the
632 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
635 if (GEN_GEN
>= 9 && info
->aux_usage
== ISL_AUX_USAGE_HIZ
)
636 s
.SamplerL2BypassModeDisable
= true;
642 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
644 s
.RedClearColor
= info
->clear_color
.u32
[0];
645 s
.GreenClearColor
= info
->clear_color
.u32
[1];
646 s
.BlueClearColor
= info
->clear_color
.u32
[2];
647 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
649 /* Prior to Sky Lake, we only have one bit for the clear color which
650 * gives us 0 or 1 in whatever the surface's format happens to be.
652 if (isl_format_has_int_channel(info
->view
->format
)) {
653 for (unsigned i
= 0; i
< 4; i
++) {
654 assert(info
->clear_color
.u32
[i
] == 0 ||
655 info
->clear_color
.u32
[i
] == 1);
657 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
658 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
659 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
660 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
662 for (unsigned i
= 0; i
< 4; i
++) {
663 assert(info
->clear_color
.f32
[i
] == 0.0f
||
664 info
->clear_color
.f32
[i
] == 1.0f
);
666 s
.RedClearColor
= info
->clear_color
.f32
[0] != 0.0f
;
667 s
.GreenClearColor
= info
->clear_color
.f32
[1] != 0.0f
;
668 s
.BlueClearColor
= info
->clear_color
.f32
[2] != 0.0f
;
669 s
.AlphaClearColor
= info
->clear_color
.f32
[3] != 0.0f
;
674 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
678 isl_genX(buffer_fill_state_s
)(void *state
,
679 const struct isl_buffer_fill_state_info
*restrict info
)
681 uint32_t num_elements
= info
->size
/ info
->stride
;
684 /* From the IVB PRM, SURFACE_STATE::Height,
686 * For typed buffer and structured buffer surfaces, the number
687 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
688 * surfaces, the number of entries in the buffer is the number of bytes
689 * which can range from 1 to 2^30.
691 if (info
->format
== ISL_FORMAT_RAW
) {
692 assert(num_elements
<= (1ull << 30));
693 assert(num_elements
> 0);
695 assert(num_elements
<= (1ull << 27));
698 assert(num_elements
<= (1ull << 27));
701 struct GENX(RENDER_SURFACE_STATE
) s
= { 0, };
703 s
.SurfaceType
= SURFTYPE_BUFFER
;
704 s
.SurfaceFormat
= info
->format
;
707 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[4];
709 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[4];
710 s
.SurfaceArray
= false;
715 s
.Height
= ((num_elements
- 1) >> 7) & 0x3fff;
716 s
.Width
= (num_elements
- 1) & 0x7f;
717 s
.Depth
= ((num_elements
- 1) >> 21) & 0x3ff;
719 s
.Height
= ((num_elements
- 1) >> 7) & 0x1fff;
720 s
.Width
= (num_elements
- 1) & 0x7f;
721 s
.Depth
= ((num_elements
- 1) >> 20) & 0x7f;
724 s
.SurfacePitch
= info
->stride
- 1;
727 s
.NumberofMultisamples
= MULTISAMPLECOUNT_1
;
733 s
.TiledSurface
= false;
737 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
739 s
.RenderCacheReadWriteMode
= 0;
742 s
.SurfaceBaseAddress
= info
->address
;
747 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
748 s
.ShaderChannelSelectRed
= SCS_RED
;
749 s
.ShaderChannelSelectGreen
= SCS_GREEN
;
750 s
.ShaderChannelSelectBlue
= SCS_BLUE
;
751 s
.ShaderChannelSelectAlpha
= SCS_ALPHA
;
754 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);