2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
29 static inline uint64_t
30 __gen_combine_address(void *data
, void *loc
, uint64_t addr
, uint32_t delta
)
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
40 #define __PASTE2(x, y) x ## y
41 #define __PASTE(x, y) __PASTE2(x, y)
42 #define isl_genX(x) __PASTE(isl_, genX(x))
45 static const uint8_t isl_to_gen_halign
[] = {
51 static const uint8_t isl_to_gen_valign
[] = {
57 static const uint8_t isl_to_gen_halign
[] = {
62 static const uint8_t isl_to_gen_valign
[] = {
69 static const uint8_t isl_to_gen_tiling
[] = {
70 [ISL_TILING_LINEAR
] = LINEAR
,
71 [ISL_TILING_X
] = XMAJOR
,
72 [ISL_TILING_Y0
] = YMAJOR
,
73 [ISL_TILING_Yf
] = YMAJOR
,
74 [ISL_TILING_Ys
] = YMAJOR
,
75 [ISL_TILING_W
] = WMAJOR
,
80 static const uint32_t isl_to_gen_multisample_layout
[] = {
81 [ISL_MSAA_LAYOUT_NONE
] = MSS
,
82 [ISL_MSAA_LAYOUT_INTERLEAVED
] = DEPTH_STENCIL
,
83 [ISL_MSAA_LAYOUT_ARRAY
] = MSS
,
86 static const uint32_t isl_to_gen_multisample_layout
[] = {
87 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
88 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
89 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
94 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
98 unreachable("bad isl_surf_dim");
100 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
102 case ISL_SURF_DIM_2D
:
103 if (usage
& ISL_SURF_USAGE_STORAGE_BIT
) {
104 /* Storage images are always plain 2-D, not cube */
106 } else if (usage
& ISL_SURF_USAGE_CUBE_BIT
) {
107 return SURFTYPE_CUBE
;
111 case ISL_SURF_DIM_3D
:
112 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
118 * Get the values to pack into RENDER_SUFFACE_STATE.SurfaceHorizontalAlignment
119 * and SurfaceVerticalAlignment.
122 get_halign_valign(const struct isl_surf
*surf
,
123 uint32_t *halign
, uint32_t *valign
)
126 if (isl_tiling_is_std_y(surf
->tiling
) ||
127 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
128 /* The hardware ignores the alignment values. Anyway, the surface's
129 * true alignment is likely outside the enum range of HALIGN* and
135 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
136 * of surface elements (not pixels nor samples). For compressed formats,
137 * a "surface element" is defined as a compression block. For example,
138 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
139 * format (ETC2 has a block height of 4), then the vertical alignment is
140 * 4 compression blocks or, equivalently, 16 pixels.
142 struct isl_extent3d image_align_el
143 = isl_surf_get_image_alignment_el(surf
);
145 *halign
= isl_to_gen_halign
[image_align_el
.width
];
146 *valign
= isl_to_gen_valign
[image_align_el
.height
];
149 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
150 * units of surface samples. For example, if SurfaceVerticalAlignment
151 * is VALIGN_4 and the surface is singlesampled, then for any surface
152 * format (compressed or not) the vertical alignment is
155 struct isl_extent3d image_align_sa
156 = isl_surf_get_image_alignment_sa(surf
);
158 *halign
= isl_to_gen_halign
[image_align_sa
.width
];
159 *valign
= isl_to_gen_valign
[image_align_sa
.height
];
165 get_qpitch(const struct isl_surf
*surf
)
169 assert(!"Bad isl_surf_dim");
170 case ISL_SURF_DIM_1D
:
172 /* QPitch is usually expressed as rows of surface elements (where
173 * a surface element is an compression block or a single surface
174 * sample). Skylake 1D is an outlier.
176 * From the Skylake BSpec >> Memory Views >> Common Surface
177 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
179 * Surface QPitch specifies the distance in pixels between array
182 return isl_surf_get_array_pitch_el(surf
);
184 return isl_surf_get_array_pitch_el_rows(surf
);
186 case ISL_SURF_DIM_2D
:
187 case ISL_SURF_DIM_3D
:
189 return isl_surf_get_array_pitch_el_rows(surf
);
191 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
193 * "This field must be set to an integer multiple of the Surface
194 * Vertical Alignment. For compressed textures (BC*, FXT1,
195 * ETC*, and EAC* Surface Formats), this field is in units of
196 * rows in the uncompressed surface, and must be set to an
197 * integer multiple of the vertical alignment parameter "j"
198 * defined in the Common Surface Formats section."
200 return isl_surf_get_array_pitch_sa_rows(surf
);
204 #endif /* GEN_GEN >= 8 */
207 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
208 const struct isl_surf_fill_state_info
*restrict info
)
210 uint32_t halign
, valign
;
211 get_halign_valign(info
->surf
, &halign
, &valign
);
213 struct GENX(RENDER_SURFACE_STATE
) s
= {
214 .SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
),
215 .SurfaceArray
= info
->surf
->phys_level0_sa
.array_len
> 1,
216 .SurfaceVerticalAlignment
= valign
,
217 .SurfaceHorizontalAlignment
= halign
,
220 .TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
],
222 .TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
223 .TileWalk
= info
->surf
->tiling
== ISL_TILING_X
? TILEWALK_XMAJOR
:
227 .VerticalLineStride
= 0,
228 .VerticalLineStrideOffset
= 0,
231 .SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
232 ISL_ARRAY_PITCH_SPAN_COMPACT
,
236 .SamplerL2BypassModeDisable
= true,
240 .RenderCacheReadWriteMode
= WriteOnlyCache
,
242 .RenderCacheReadWriteMode
= 0,
246 .CubeFaceEnablePositiveZ
= 1,
247 .CubeFaceEnableNegativeZ
= 1,
248 .CubeFaceEnablePositiveY
= 1,
249 .CubeFaceEnableNegativeY
= 1,
250 .CubeFaceEnablePositiveX
= 1,
251 .CubeFaceEnableNegativeX
= 1,
253 .CubeFaceEnables
= 0x3f,
257 .SurfaceQPitch
= get_qpitch(info
->surf
) >> 2,
260 .Width
= info
->surf
->logical_level0_px
.width
- 1,
261 .Height
= info
->surf
->logical_level0_px
.height
- 1,
262 .Depth
= 0, /* TEMPLATE */
264 .RenderTargetViewExtent
= 0, /* TEMPLATE */
265 .MinimumArrayElement
= 0, /* TEMPLATE */
267 .MultisampledSurfaceStorageFormat
=
268 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
],
269 .NumberofMultisamples
= ffs(info
->surf
->samples
) - 1,
270 .MultisamplePositionPaletteIndex
= 0, /* UNUSED */
275 .ResourceMinLOD
= 0.0,
277 .MIPCountLOD
= 0, /* TEMPLATE */
278 .SurfaceMinLOD
= 0, /* TEMPLATE */
280 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
281 .ShaderChannelSelectRed
= info
->view
->channel_select
[0],
282 .ShaderChannelSelectGreen
= info
->view
->channel_select
[1],
283 .ShaderChannelSelectBlue
= info
->view
->channel_select
[2],
284 .ShaderChannelSelectAlpha
= info
->view
->channel_select
[3],
287 .SurfaceBaseAddress
= info
->address
,
291 .AuxiliarySurfaceMode
= AUX_NONE
,
297 if (info
->surf
->tiling
== ISL_TILING_W
) {
298 /* From the Broadwell PRM documentation for this field:
300 * "If the surface is a stencil buffer (and thus has Tile Mode set
301 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
302 * computed based on width, as the stencil buffer is stored with
303 * two rows interleaved."
305 s
.SurfacePitch
= info
->surf
->row_pitch
* 2 - 1;
307 s
.SurfacePitch
= info
->surf
->row_pitch
- 1;
310 if (info
->view
->usage
& ISL_SURF_USAGE_STORAGE_BIT
) {
311 s
.SurfaceFormat
= isl_lower_storage_image_format(dev
, info
->view
->format
);
313 s
.SurfaceFormat
= info
->view
->format
;
316 switch (s
.SurfaceType
) {
319 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
321 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
323 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
324 * by one for each increase from zero of Minimum Array Element. For
325 * example, if Minimum Array Element is set to 1024 on a 2D surface,
326 * the range of this field is reduced to [0,1023].
328 * In other words, 'Depth' is the number of array layers.
330 s
.Depth
= info
->view
->array_len
- 1;
332 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
334 * For Render Target and Typed Dataport 1D and 2D Surfaces:
335 * This field must be set to the same value as the Depth field.
337 s
.RenderTargetViewExtent
= s
.Depth
;
340 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
341 /* Same as SURFTYPE_2D, but divided by 6 */
342 s
.Depth
= info
->view
->array_len
/ 6 - 1;
343 s
.RenderTargetViewExtent
= s
.Depth
;
346 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
348 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
350 * If the volume texture is MIP-mapped, this field specifies the
351 * depth of the base MIP level.
353 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
355 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
357 * For Render Target and Typed Dataport 3D Surfaces: This field
358 * indicates the extent of the accessible 'R' coordinates minus 1 on
359 * the LOD currently being rendered to.
361 s
.RenderTargetViewExtent
= isl_minify(info
->surf
->logical_level0_px
.depth
,
362 info
->view
->base_level
) - 1;
365 unreachable(!"bad SurfaceType");
368 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
369 /* For render target surfaces, the hardware interprets field
370 * MIPCount/LOD as LOD. The Broadwell PRM says:
372 * MIPCountLOD defines the LOD that will be rendered into.
373 * SurfaceMinLOD is ignored.
375 s
.MIPCountLOD
= info
->view
->base_level
;
378 /* For non render target surfaces, the hardware interprets field
379 * MIPCount/LOD as MIPCount. The range of levels accessible by the
380 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
382 s
.SurfaceMinLOD
= info
->view
->base_level
;
383 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
387 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
388 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
390 * This bit must be set for the following surface types: BC2_UNORM
391 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
393 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
394 switch (info
->view
->format
) {
395 case ISL_FORMAT_BC2_UNORM
:
396 case ISL_FORMAT_BC3_UNORM
:
397 case ISL_FORMAT_BC5_UNORM
:
398 case ISL_FORMAT_BC5_SNORM
:
399 case ISL_FORMAT_BC7_UNORM
:
400 s
.SamplerL2BypassModeDisable
= true;
409 /* Prior to Sky Lake, we only have one bit for the clear color which
410 * gives us 0 or 1 in whatever the surface's format happens to be.
412 if (isl_format_has_int_channel(info
->view
->format
)) {
413 for (unsigned i
= 0; i
< 4; i
++) {
414 assert(info
->clear_color
.u32
[i
] == 0 ||
415 info
->clear_color
.u32
[i
] == 1);
418 for (unsigned i
= 0; i
< 4; i
++) {
419 assert(info
->clear_color
.f32
[i
] == 0.0f
||
420 info
->clear_color
.f32
[i
] == 1.0f
);
423 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
424 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
425 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
426 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
428 s
.RedClearColor
= info
->clear_color
.u32
[0];
429 s
.GreenClearColor
= info
->clear_color
.u32
[1];
430 s
.BlueClearColor
= info
->clear_color
.u32
[2];
431 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
434 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
438 isl_genX(buffer_fill_state_s
)(void *state
,
439 const struct isl_buffer_fill_state_info
*restrict info
)
441 uint32_t num_elements
= info
->size
/ info
->stride
;
443 struct GENX(RENDER_SURFACE_STATE
) surface_state
= {
444 .SurfaceType
= SURFTYPE_BUFFER
,
445 .SurfaceArray
= false,
446 .SurfaceFormat
= info
->format
,
447 .SurfaceVerticalAlignment
= isl_to_gen_valign
[4],
448 .SurfaceHorizontalAlignment
= isl_to_gen_halign
[4],
449 .Height
= ((num_elements
- 1) >> 7) & 0x3fff,
450 .Width
= (num_elements
- 1) & 0x7f,
451 .Depth
= ((num_elements
- 1) >> 21) & 0x3f,
452 .SurfacePitch
= info
->stride
- 1,
453 .NumberofMultisamples
= MULTISAMPLECOUNT_1
,
458 .TiledSurface
= false,
462 .SamplerL2BypassModeDisable
= true,
463 .RenderCacheReadWriteMode
= WriteOnlyCache
,
465 .RenderCacheReadWriteMode
= 0,
470 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
471 .ShaderChannelSelectRed
= SCS_RED
,
472 .ShaderChannelSelectGreen
= SCS_GREEN
,
473 .ShaderChannelSelectBlue
= SCS_BLUE
,
474 .ShaderChannelSelectAlpha
= SCS_ALPHA
,
476 .SurfaceBaseAddress
= info
->address
,
479 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &surface_state
);