src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 9
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  93    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  94    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  95    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  96 };
  97 #elif GEN_GEN >= 8
  98 static const uint32_t isl_to_gen_aux_mode[] = {
  99    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 100    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 101    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 102    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 103 };
 104 #endif
 105
 106 static uint8_t
 107 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 108 {
 109    switch (dim) {
 110    default:
 111       unreachable("bad isl_surf_dim");
 112    case ISL_SURF_DIM_1D:
 113       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 114       return SURFTYPE_1D;
 115    case ISL_SURF_DIM_2D:
 116       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
 117          /* Storage images are always plain 2-D, not cube */
 118          return SURFTYPE_2D;
 119       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 120          return SURFTYPE_CUBE;
 121       } else {
 122          return SURFTYPE_2D;
 123       }
 124    case ISL_SURF_DIM_3D:
 125       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 126       return SURFTYPE_3D;
 127    }
 128 }
 129
 130 /**
 131  * Get the horizontal and vertical alignment in the units expected by the
 132  * hardware.  Note that this does NOT give you the actual hardware enum values
 133  * but an index into the isl_to_gen_[hv]align arrays above.
 134  */
 135 static inline struct isl_extent3d
 136 get_image_alignment(const struct isl_surf *surf)
 137 {
 138    if (GEN_GEN >= 9) {
 139       if (isl_tiling_is_std_y(surf->tiling) ||
 140           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 141          /* The hardware ignores the alignment values. Anyway, the surface's
 142           * true alignment is likely outside the enum range of HALIGN* and
 143           * VALIGN*.
 144           */
 145          return isl_extent3d(4, 4, 1);
 146       } else {
 147          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 148           * of surface elements (not pixels nor samples). For compressed formats,
 149           * a "surface element" is defined as a compression block.  For example,
 150           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 151           * format (ETC2 has a block height of 4), then the vertical alignment is
 152           * 4 compression blocks or, equivalently, 16 pixels.
 153           */
 154          return isl_surf_get_image_alignment_el(surf);
 155       }
 156    } else {
 157       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 158        * units of surface samples.  For example, if SurfaceVerticalAlignment
 159        * is VALIGN_4 and the surface is singlesampled, then for any surface
 160        * format (compressed or not) the vertical alignment is
 161        * 4 pixels.
 162        */
 163       return isl_surf_get_image_alignment_sa(surf);
 164    }
 165 }
 166
 167 #if GEN_GEN >= 8
 168 static uint32_t
 169 get_qpitch(const struct isl_surf *surf)
 170 {
 171    switch (surf->dim_layout) {
 172    default:
 173       unreachable("Bad isl_surf_dim");
 174    case ISL_DIM_LAYOUT_GEN4_2D:
 175       if (GEN_GEN >= 9) {
 176          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 177             /* This is rather annoying and completely undocumented.  It
 178              * appears that the hardware has a bug (or undocumented feature)
 179              * regarding stencil buffers most likely related to the way
 180              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 181              * stencil buffer normally, and use texelFetch on it, the z or
 182              * array index will get implicitly multiplied by 2 for no obvious
 183              * reason.  The fix appears to be to divide qpitch by 2 for
 184              * W-tiled surfaces.
 185              */
 186             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 187          } else {
 188             return isl_surf_get_array_pitch_el_rows(surf);
 189          }
 190       } else {
 191          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 192           *
 193           *    "This field must be set to an integer multiple of the Surface
 194           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 195           *    ETC*, and EAC* Surface Formats), this field is in units of
 196           *    rows in the uncompressed surface, and must be set to an
 197           *    integer multiple of the vertical alignment parameter "j"
 198           *    defined in the Common Surface Formats section."
 199           */
 200          return isl_surf_get_array_pitch_sa_rows(surf);
 201       }
 202    case ISL_DIM_LAYOUT_GEN9_1D:
 203       /* QPitch is usually expressed as rows of surface elements (where
 204        * a surface element is an compression block or a single surface
 205        * sample). Skylake 1D is an outlier.
 206        *
 207        * From the Skylake BSpec >> Memory Views >> Common Surface
 208        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 209        *
 210        *    Surface QPitch specifies the distance in pixels between array
 211        *    slices.
 212        */
 213       return isl_surf_get_array_pitch_el(surf);
 214    case ISL_DIM_LAYOUT_GEN4_3D:
 215       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 216        * different pitch at each LOD.  Also, the QPitch field is ignored for
 217        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 218        *
 219        *    This field specifies the distance in rows between array slices. It
 220        *    is used only in the following cases:
 221        *     - Surface Array is enabled OR
 222        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 223        *       Surface Storage Format set to MSFMT_MSS OR
 224        *     - Surface Type is SURFTYPE_CUBE
 225        *
 226        * None of the three conditions above can possibly apply to a 3D surface
 227        * so it is safe to just set QPitch to 0.
 228        */
 229       return 0;
 230    }
 231 }
 232 #endif /* GEN_GEN >= 8 */
 233
 234 void
 235 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 236                             const struct isl_surf_fill_state_info *restrict info)
 237 {
 238    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 239
 240    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 241
 242    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 243       assert(isl_format_supports_rendering(dev->info, info->view->format));
 244    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 245       assert(isl_format_supports_sampling(dev->info, info->view->format));
 246    s.SurfaceFormat = info->view->format;
 247
 248 #if GEN_IS_HASWELL
 249    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 250 #endif
 251
 252    s.Width = info->surf->logical_level0_px.width - 1;
 253    s.Height = info->surf->logical_level0_px.height - 1;
 254
 255    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 256     * (Surface Arrays For all surfaces other than separate stencil buffer):
 257     *
 258     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 259     *  calculated in the equation above , for every other odd Surface Height
 260     *  starting from 1 i.e. 1,5,9,13"
 261     *
 262     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 263     * input for the rendering surface to achieve the same qpitch. For the
 264     * affected heights, we increment the height by 1 for the rendering
 265     * surface.
 266     */
 267    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 268        info->surf->samples > 1 &&
 269        (info->surf->logical_level0_px.height % 4) == 1)
 270       s.Height++;
 271
 272    switch (s.SurfaceType) {
 273    case SURFTYPE_1D:
 274    case SURFTYPE_2D:
 275       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 276        *
 277        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 278        *    must be set to zero if this surface is used with sampling engine
 279        *    messages."
 280        *
 281        * This restriction appears to exist only on Ivy Bridge.
 282        */
 283       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 284           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 285           info->surf->samples > 1)
 286          assert(info->view->base_array_layer == 0);
 287
 288       s.MinimumArrayElement = info->view->base_array_layer;
 289
 290       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 291        *
 292        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 293        *    by one for each increase from zero of Minimum Array Element. For
 294        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 295        *    the range of this field is reduced to [0,1023].
 296        *
 297        * In other words, 'Depth' is the number of array layers.
 298        */
 299       s.Depth = info->view->array_len - 1;
 300
 301       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 302        *
 303        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 304        *    This field must be set to the same value as the Depth field.
 305        */
 306       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 307                                ISL_SURF_USAGE_STORAGE_BIT))
 308          s.RenderTargetViewExtent = s.Depth;
 309       break;
 310    case SURFTYPE_CUBE:
 311       s.MinimumArrayElement = info->view->base_array_layer;
 312       /* Same as SURFTYPE_2D, but divided by 6 */
 313       s.Depth = info->view->array_len / 6 - 1;
 314       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 315                                ISL_SURF_USAGE_STORAGE_BIT))
 316          s.RenderTargetViewExtent = s.Depth;
 317       break;
 318    case SURFTYPE_3D:
 319       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 320        *
 321        *    If the volume texture is MIP-mapped, this field specifies the
 322        *    depth of the base MIP level.
 323        */
 324       s.Depth = info->surf->logical_level0_px.depth - 1;
 325
 326       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 327        *
 328        *    For Render Target and Typed Dataport 3D Surfaces: This field
 329        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 330        *    the LOD currently being rendered to.
 331        *
 332        * The docs specify that this only matters for render targets and
 333        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 334        * Depth field has more bits than RenderTargetViewExtent so we can have
 335        * textures with more levels than we can render to.  In order to prevent
 336        * assert-failures in the packing function below, we only set the field
 337        * when it's actually going to be used by the hardware.
 338        *
 339        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 340        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 341        * Since it's already initialized to 0, we can just leave it alone for
 342        * texture surfaces.
 343        */
 344       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 345                                ISL_SURF_USAGE_STORAGE_BIT)) {
 346          s.MinimumArrayElement = info->view->base_array_layer;
 347          s.RenderTargetViewExtent = info->view->array_len - 1;
 348       }
 349       break;
 350    default:
 351       unreachable("bad SurfaceType");
 352    }
 353
 354 #if GEN_GEN >= 7
 355    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 356 #endif
 357
 358    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 359       /* For render target surfaces, the hardware interprets field
 360        * MIPCount/LOD as LOD. The Broadwell PRM says:
 361        *
 362        *    MIPCountLOD defines the LOD that will be rendered into.
 363        *    SurfaceMinLOD is ignored.
 364        */
 365       s.MIPCountLOD = info->view->base_level;
 366       s.SurfaceMinLOD = 0;
 367    } else {
 368       /* For non render target surfaces, the hardware interprets field
 369        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 370        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 371        */
 372       s.SurfaceMinLOD = info->view->base_level;
 373       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 374    }
 375
 376 #if GEN_GEN >= 9
 377    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 378     * Start LOD" to 15 to prevent the hardware from trying to use them.
 379     */
 380    s.TiledResourceMode = NONE;
 381    s.MipTailStartLOD = 15;
 382 #endif
 383
 384 #if GEN_GEN >= 6
 385    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 386    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 387 #if GEN_GEN >= 7
 388    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 389 #endif
 390 #endif
 391
 392    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 393       /* For gen9 1-D textures, surface pitch is ignored */
 394       s.SurfacePitch = 0;
 395    } else {
 396       s.SurfacePitch = info->surf->row_pitch - 1;
 397    }
 398
 399 #if GEN_GEN >= 8
 400    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 401 #elif GEN_GEN == 7
 402    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 403                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 404 #endif
 405
 406 #if GEN_GEN >= 8
 407    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 408 #else
 409    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 410    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 411                                                       TILEWALK_XMAJOR,
 412 #endif
 413
 414 #if GEN_GEN >= 8
 415    s.RenderCacheReadWriteMode = WriteOnlyCache;
 416 #else
 417    s.RenderCacheReadWriteMode = 0;
 418 #endif
 419
 420    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 421 #if GEN_GEN >= 8
 422       s.CubeFaceEnablePositiveZ = 1;
 423       s.CubeFaceEnableNegativeZ = 1;
 424       s.CubeFaceEnablePositiveY = 1;
 425       s.CubeFaceEnableNegativeY = 1;
 426       s.CubeFaceEnablePositiveX = 1;
 427       s.CubeFaceEnableNegativeX = 1;
 428 #else
 429       s.CubeFaceEnables = 0x3f;
 430 #endif
 431    }
 432
 433 #if GEN_GEN >= 6
 434    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 435 #if GEN_GEN >= 7
 436    s.MultisampledSurfaceStorageFormat =
 437       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 438 #endif
 439 #endif
 440
 441 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 442    s.ShaderChannelSelectRed = info->view->swizzle.r;
 443    s.ShaderChannelSelectGreen = info->view->swizzle.g;
 444    s.ShaderChannelSelectBlue = info->view->swizzle.b;
 445    s.ShaderChannelSelectAlpha = info->view->swizzle.a;
 446 #endif
 447
 448    s.SurfaceBaseAddress = info->address;
 449
 450 #if GEN_GEN >= 6
 451    s.MOCS = info->mocs;
 452 #endif
 453
 454 #if GEN_GEN > 4 || GEN_IS_G4X
 455    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 456       /* There are fairly strict rules about when the offsets can be used.
 457        * These are mostly taken from the Sky Lake PRM documentation for
 458        * RENDER_SURFACE_STATE.
 459        */
 460       assert(info->surf->tiling != ISL_TILING_LINEAR);
 461       assert(info->surf->dim == ISL_SURF_DIM_2D);
 462       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 463       assert(info->surf->levels == 1);
 464       assert(info->surf->logical_level0_px.array_len == 1);
 465       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 466
 467       if (GEN_GEN >= 8) {
 468          /* Broadwell added more rules. */
 469          assert(info->surf->samples == 1);
 470          if (isl_format_get_layout(info->view->format)->bpb == 8)
 471             assert(info->x_offset_sa % 16 == 0);
 472          if (isl_format_get_layout(info->view->format)->bpb == 16)
 473             assert(info->x_offset_sa % 8 == 0);
 474       }
 475
 476 #if GEN_GEN >= 7
 477       s.SurfaceArray = false;
 478 #endif
 479    }
 480
 481    const unsigned x_div = 4;
 482    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 483    assert(info->x_offset_sa % x_div == 0);
 484    assert(info->y_offset_sa % y_div == 0);
 485    s.XOffset = info->x_offset_sa / x_div;
 486    s.YOffset = info->y_offset_sa / y_div;
 487 #else
 488    assert(info->x_offset_sa == 0);
 489    assert(info->y_offset_sa == 0);
 490 #endif
 491
 492 #if GEN_GEN >= 7
 493    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 494       struct isl_tile_info tile_info;
 495       isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
 496       uint32_t pitch_in_tiles =
 497          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 498
 499 #if GEN_GEN >= 8
 500       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 501       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 502       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 503        * doesn't expect our definition of the compression, it expects qpitch
 504        * in units of samples on the main surface.
 505        */
 506       s.AuxiliarySurfaceQPitch =
 507          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 508       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 509       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 510 #else
 511       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 512              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 513       s.MCSBaseAddress = info->aux_address,
 514       s.MCSSurfacePitch = pitch_in_tiles - 1;
 515       s.MCSEnable = true;
 516 #endif
 517    }
 518 #endif
 519
 520 #if GEN_GEN >= 8
 521    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 522     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 523     *
 524     *    This bit must be set for the following surface types: BC2_UNORM
 525     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 526     */
 527    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 528       switch (info->view->format) {
 529       case ISL_FORMAT_BC2_UNORM:
 530       case ISL_FORMAT_BC3_UNORM:
 531       case ISL_FORMAT_BC5_UNORM:
 532       case ISL_FORMAT_BC5_SNORM:
 533       case ISL_FORMAT_BC7_UNORM:
 534          s.SamplerL2BypassModeDisable = true;
 535          break;
 536       default:
 537          break;
 538       }
 539    }
 540 #endif
 541
 542    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 543 #if GEN_GEN >= 9
 544       s.RedClearColor = info->clear_color.u32[0];
 545       s.GreenClearColor = info->clear_color.u32[1];
 546       s.BlueClearColor = info->clear_color.u32[2];
 547       s.AlphaClearColor = info->clear_color.u32[3];
 548 #elif GEN_GEN >= 7
 549       /* Prior to Sky Lake, we only have one bit for the clear color which
 550        * gives us 0 or 1 in whatever the surface's format happens to be.
 551        */
 552       if (isl_format_has_int_channel(info->view->format)) {
 553          for (unsigned i = 0; i < 4; i++) {
 554             assert(info->clear_color.u32[i] == 0 ||
 555                    info->clear_color.u32[i] == 1);
 556          }
 557          s.RedClearColor = info->clear_color.u32[0] != 0;
 558          s.GreenClearColor = info->clear_color.u32[1] != 0;
 559          s.BlueClearColor = info->clear_color.u32[2] != 0;
 560          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 561       } else {
 562          for (unsigned i = 0; i < 4; i++) {
 563             assert(info->clear_color.f32[i] == 0.0f ||
 564                    info->clear_color.f32[i] == 1.0f);
 565          }
 566          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 567          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 568          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 569          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 570       }
 571 #endif
 572    }
 573
 574    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 575 }
 576
 577 void
 578 isl_genX(buffer_fill_state_s)(void *state,
 579                               const struct isl_buffer_fill_state_info *restrict info)
 580 {
 581    uint32_t num_elements = info->size / info->stride;
 582
 583    if (GEN_GEN >= 7) {
 584       /* From the IVB PRM, SURFACE_STATE::Height,
 585        *
 586        *    For typed buffer and structured buffer surfaces, the number
 587        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 588        *    surfaces, the number of entries in the buffer is the number of bytes
 589        *    which can range from 1 to 2^30.
 590        */
 591       if (info->format == ISL_FORMAT_RAW) {
 592          assert(num_elements <= (1ull << 30));
 593          assert((num_elements & 3) == 0);
 594       } else {
 595          assert(num_elements <= (1ull << 27));
 596       }
 597    } else {
 598       assert(num_elements <= (1ull << 27));
 599    }
 600
 601    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 602
 603    s.SurfaceType = SURFTYPE_BUFFER;
 604    s.SurfaceFormat = info->format;
 605
 606 #if GEN_GEN >= 6
 607    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 608 #if GEN_GEN >= 7
 609    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 610    s.SurfaceArray = false;
 611 #endif
 612 #endif
 613
 614 #if GEN_GEN >= 7
 615    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 616    s.Width = (num_elements - 1) & 0x7f;
 617    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 618 #else
 619    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 620    s.Width = (num_elements - 1) & 0x7f;
 621    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 622 #endif
 623
 624    s.SurfacePitch = info->stride - 1;
 625
 626 #if GEN_GEN >= 6
 627    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 628 #endif
 629
 630 #if (GEN_GEN >= 8)
 631    s.TileMode = LINEAR;
 632 #else
 633    s.TiledSurface = false;
 634 #endif
 635
 636 #if (GEN_GEN >= 8)
 637    s.RenderCacheReadWriteMode = WriteOnlyCache;
 638 #else
 639    s.RenderCacheReadWriteMode = 0;
 640 #endif
 641
 642    s.SurfaceBaseAddress = info->address;
 643 #if GEN_GEN >= 6
 644    s.MOCS = info->mocs;
 645 #endif
 646
 647 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 648    s.ShaderChannelSelectRed = SCS_RED;
 649    s.ShaderChannelSelectGreen = SCS_GREEN;
 650    s.ShaderChannelSelectBlue = SCS_BLUE;
 651    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 652 #endif
 653
 654    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 655 }