src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 static const uint32_t isl_to_gen_multisample_layout[] = {
  82    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  83    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  84    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  85 };
  86
  87 static uint8_t
  88 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
  89 {
  90    switch (dim) {
  91    default:
  92       unreachable("bad isl_surf_dim");
  93    case ISL_SURF_DIM_1D:
  94       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
  95       return SURFTYPE_1D;
  96    case ISL_SURF_DIM_2D:
  97       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
  98          /* Storage images are always plain 2-D, not cube */
  99          return SURFTYPE_2D;
 100       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 101          return SURFTYPE_CUBE;
 102       } else {
 103          return SURFTYPE_2D;
 104       }
 105    case ISL_SURF_DIM_3D:
 106       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 107       return SURFTYPE_3D;
 108    }
 109 }
 110
 111 /**
 112  * Get the horizontal and vertical alignment in the units expected by the
 113  * hardware.  Note that this does NOT give you the actual hardware enum values
 114  * but an index into the isl_to_gen_[hv]align arrays above.
 115  */
 116 static struct isl_extent3d
 117 get_image_alignment(const struct isl_surf *surf)
 118 {
 119    if (GEN_GEN >= 9) {
 120       if (isl_tiling_is_std_y(surf->tiling) ||
 121           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 122          /* The hardware ignores the alignment values. Anyway, the surface's
 123           * true alignment is likely outside the enum range of HALIGN* and
 124           * VALIGN*.
 125           */
 126          return isl_extent3d(0, 0, 0);
 127       } else {
 128          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 129           * of surface elements (not pixels nor samples). For compressed formats,
 130           * a "surface element" is defined as a compression block.  For example,
 131           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 132           * format (ETC2 has a block height of 4), then the vertical alignment is
 133           * 4 compression blocks or, equivalently, 16 pixels.
 134           */
 135          return isl_surf_get_image_alignment_el(surf);
 136       }
 137    } else {
 138       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 139        * units of surface samples.  For example, if SurfaceVerticalAlignment
 140        * is VALIGN_4 and the surface is singlesampled, then for any surface
 141        * format (compressed or not) the vertical alignment is
 142        * 4 pixels.
 143        */
 144       return isl_surf_get_image_alignment_sa(surf);
 145    }
 146 }
 147
 148 #if GEN_GEN >= 8
 149 static uint32_t
 150 get_qpitch(const struct isl_surf *surf)
 151 {
 152    switch (surf->dim_layout) {
 153    default:
 154       unreachable("Bad isl_surf_dim");
 155    case ISL_DIM_LAYOUT_GEN4_2D:
 156    case ISL_DIM_LAYOUT_GEN4_3D:
 157       if (GEN_GEN >= 9) {
 158          return isl_surf_get_array_pitch_el_rows(surf);
 159       } else {
 160          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 161           *
 162           *    "This field must be set to an integer multiple of the Surface
 163           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 164           *    ETC*, and EAC* Surface Formats), this field is in units of
 165           *    rows in the uncompressed surface, and must be set to an
 166           *    integer multiple of the vertical alignment parameter "j"
 167           *    defined in the Common Surface Formats section."
 168           */
 169          return isl_surf_get_array_pitch_sa_rows(surf);
 170       }
 171    case ISL_DIM_LAYOUT_GEN9_1D:
 172       /* QPitch is usually expressed as rows of surface elements (where
 173        * a surface element is an compression block or a single surface
 174        * sample). Skylake 1D is an outlier.
 175        *
 176        * From the Skylake BSpec >> Memory Views >> Common Surface
 177        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 178        *
 179        *    Surface QPitch specifies the distance in pixels between array
 180        *    slices.
 181        */
 182       return isl_surf_get_array_pitch_el(surf);
 183    }
 184 }
 185 #endif /* GEN_GEN >= 8 */
 186
 187 void
 188 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 189                             const struct isl_surf_fill_state_info *restrict info)
 190 {
 191    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 192
 193    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 194
 195    if (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT) {
 196       s.SurfaceFormat =
 197          isl_lower_storage_image_format(dev->info, info->view->format);
 198    } else {
 199       s.SurfaceFormat = info->view->format;
 200    }
 201
 202 #if GEN_IS_HASWELL
 203    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 204 #endif
 205
 206    s.Width = info->surf->logical_level0_px.width - 1;
 207    s.Height = info->surf->logical_level0_px.height - 1;
 208
 209    switch (s.SurfaceType) {
 210    case SURFTYPE_1D:
 211    case SURFTYPE_2D:
 212       s.MinimumArrayElement = info->view->base_array_layer;
 213
 214       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 215        *
 216        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 217        *    by one for each increase from zero of Minimum Array Element. For
 218        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 219        *    the range of this field is reduced to [0,1023].
 220        *
 221        * In other words, 'Depth' is the number of array layers.
 222        */
 223       s.Depth = info->view->array_len - 1;
 224
 225       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 226        *
 227        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 228        *    This field must be set to the same value as the Depth field.
 229        */
 230       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 231                                ISL_SURF_USAGE_STORAGE_BIT))
 232          s.RenderTargetViewExtent = s.Depth;
 233       break;
 234    case SURFTYPE_CUBE:
 235       s.MinimumArrayElement = info->view->base_array_layer;
 236       /* Same as SURFTYPE_2D, but divided by 6 */
 237       s.Depth = info->view->array_len / 6 - 1;
 238       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 239                                ISL_SURF_USAGE_STORAGE_BIT))
 240          s.RenderTargetViewExtent = s.Depth;
 241       break;
 242    case SURFTYPE_3D:
 243       s.MinimumArrayElement = info->view->base_array_layer;
 244
 245       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 246        *
 247        *    If the volume texture is MIP-mapped, this field specifies the
 248        *    depth of the base MIP level.
 249        */
 250       s.Depth = info->surf->logical_level0_px.depth - 1;
 251
 252       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 253        *
 254        *    For Render Target and Typed Dataport 3D Surfaces: This field
 255        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 256        *    the LOD currently being rendered to.
 257        *
 258        * The docs specify that this only matters for render targets and
 259        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 260        * Depth field has more bits than RenderTargetViewExtent so we can have
 261        * textures with more levels than we can render to.  In order to prevent
 262        * assert-failures in the packing function below, we only set the field
 263        * when it's actually going to be used by the hardware.
 264        */
 265       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 266                                ISL_SURF_USAGE_STORAGE_BIT)) {
 267          s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 268                                                info->view->base_level) - 1;
 269       }
 270       break;
 271    default:
 272       unreachable("bad SurfaceType");
 273    }
 274
 275    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 276
 277    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 278       /* For render target surfaces, the hardware interprets field
 279        * MIPCount/LOD as LOD. The Broadwell PRM says:
 280        *
 281        *    MIPCountLOD defines the LOD that will be rendered into.
 282        *    SurfaceMinLOD is ignored.
 283        */
 284       s.MIPCountLOD = info->view->base_level;
 285       s.SurfaceMinLOD = 0;
 286    } else {
 287       /* For non render target surfaces, the hardware interprets field
 288        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 289        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 290        */
 291       s.SurfaceMinLOD = info->view->base_level;
 292       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 293    }
 294
 295    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 296    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 297    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 298
 299    if (info->surf->tiling == ISL_TILING_W) {
 300       /* From the Broadwell PRM documentation for this field:
 301        *
 302        *    "If the surface is a stencil buffer (and thus has Tile Mode set
 303        *    to TILEMODE_WMAJOR), the pitch must be set to 2x the value
 304        *    computed based on width, as the stencil buffer is stored with
 305        *    two rows interleaved."
 306        */
 307       s.SurfacePitch = info->surf->row_pitch * 2 - 1;
 308    } else {
 309       s.SurfacePitch = info->surf->row_pitch - 1;
 310    }
 311
 312 #if GEN_GEN >= 8
 313    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 314 #elif GEN_GEN == 7
 315    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 316                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 317 #endif
 318
 319 #if GEN_GEN >= 8
 320    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 321 #else
 322    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 323    s.TileWalk = info->surf->tiling == ISL_TILING_X ? TILEWALK_XMAJOR :
 324                                                      TILEWALK_YMAJOR;
 325 #endif
 326
 327 #if GEN_GEN >= 8
 328    s.RenderCacheReadWriteMode = WriteOnlyCache;
 329 #else
 330    s.RenderCacheReadWriteMode = 0;
 331 #endif
 332
 333    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 334 #if GEN_GEN >= 8
 335       s.CubeFaceEnablePositiveZ = 1;
 336       s.CubeFaceEnableNegativeZ = 1;
 337       s.CubeFaceEnablePositiveY = 1;
 338       s.CubeFaceEnableNegativeY = 1;
 339       s.CubeFaceEnablePositiveX = 1;
 340       s.CubeFaceEnableNegativeX = 1;
 341 #else
 342       s.CubeFaceEnables = 0x3f;
 343 #endif
 344    }
 345
 346    s.MultisampledSurfaceStorageFormat =
 347       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 348    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 349
 350 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 351    s.ShaderChannelSelectRed = info->view->channel_select[0];
 352    s.ShaderChannelSelectGreen = info->view->channel_select[1];
 353    s.ShaderChannelSelectBlue = info->view->channel_select[2];
 354    s.ShaderChannelSelectAlpha = info->view->channel_select[3];
 355 #endif
 356
 357    s.SurfaceBaseAddress = info->address;
 358    s.MOCS = info->mocs;
 359
 360 #if GEN_GEN >= 8
 361    s.AuxiliarySurfaceMode = AUX_NONE;
 362 #else
 363    s.MCSEnable = false;
 364 #endif
 365
 366 #if GEN_GEN >= 8
 367    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 368     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 369     *
 370     *    This bit must be set for the following surface types: BC2_UNORM
 371     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 372     */
 373    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 374       switch (info->view->format) {
 375       case ISL_FORMAT_BC2_UNORM:
 376       case ISL_FORMAT_BC3_UNORM:
 377       case ISL_FORMAT_BC5_UNORM:
 378       case ISL_FORMAT_BC5_SNORM:
 379       case ISL_FORMAT_BC7_UNORM:
 380          s.SamplerL2BypassModeDisable = true;
 381          break;
 382       default:
 383          break;
 384       }
 385    }
 386 #endif
 387
 388 #if GEN_GEN >= 9
 389    s.RedClearColor = info->clear_color.u32[0];
 390    s.GreenClearColor = info->clear_color.u32[1];
 391    s.BlueClearColor = info->clear_color.u32[2];
 392    s.AlphaClearColor = info->clear_color.u32[3];
 393 #elif GEN_GEN >= 7
 394    /* Prior to Sky Lake, we only have one bit for the clear color which
 395     * gives us 0 or 1 in whatever the surface's format happens to be.
 396     */
 397    if (isl_format_has_int_channel(info->view->format)) {
 398       for (unsigned i = 0; i < 4; i++) {
 399          assert(info->clear_color.u32[i] == 0 ||
 400                 info->clear_color.u32[i] == 1);
 401       }
 402       s.RedClearColor = info->clear_color.u32[0] != 0;
 403       s.GreenClearColor = info->clear_color.u32[1] != 0;
 404       s.BlueClearColor = info->clear_color.u32[2] != 0;
 405       s.AlphaClearColor = info->clear_color.u32[3] != 0;
 406    } else {
 407       for (unsigned i = 0; i < 4; i++) {
 408          assert(info->clear_color.f32[i] == 0.0f ||
 409                 info->clear_color.f32[i] == 1.0f);
 410       }
 411       s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 412       s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 413       s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 414       s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 415    }
 416 #endif
 417
 418    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 419 }
 420
 421 void
 422 isl_genX(buffer_fill_state_s)(void *state,
 423                               const struct isl_buffer_fill_state_info *restrict info)
 424 {
 425    uint32_t num_elements = info->size / info->stride;
 426
 427    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 428       .SurfaceType = SURFTYPE_BUFFER,
 429       .SurfaceArray = false,
 430       .SurfaceFormat = info->format,
 431       .SurfaceVerticalAlignment = isl_to_gen_valign[4],
 432       .SurfaceHorizontalAlignment = isl_to_gen_halign[4],
 433       .Height = ((num_elements - 1) >> 7) & 0x3fff,
 434       .Width = (num_elements - 1) & 0x7f,
 435       .Depth = ((num_elements - 1) >> 21) & 0x3f,
 436       .SurfacePitch = info->stride - 1,
 437       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 438
 439 #if (GEN_GEN >= 8)
 440       .TileMode = LINEAR,
 441 #else
 442       .TiledSurface = false,
 443 #endif
 444
 445 #if (GEN_GEN >= 8)
 446       .RenderCacheReadWriteMode = WriteOnlyCache,
 447 #else
 448       .RenderCacheReadWriteMode = 0,
 449 #endif
 450
 451       .MOCS = info->mocs,
 452
 453 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 454       .ShaderChannelSelectRed = SCS_RED,
 455       .ShaderChannelSelectGreen = SCS_GREEN,
 456       .ShaderChannelSelectBlue = SCS_BLUE,
 457       .ShaderChannelSelectAlpha = SCS_ALPHA,
 458 #endif
 459       .SurfaceBaseAddress = info->address,
 460    };
 461
 462    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
 463 }