src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 9
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  93    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  94    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  95    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  96 };
  97 #elif GEN_GEN >= 8
  98 static const uint32_t isl_to_gen_aux_mode[] = {
  99    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 100    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 101    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 102    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 103 };
 104 #endif
 105
 106 static uint8_t
 107 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 108 {
 109    switch (dim) {
 110    default:
 111       unreachable("bad isl_surf_dim");
 112    case ISL_SURF_DIM_1D:
 113       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 114       return SURFTYPE_1D;
 115    case ISL_SURF_DIM_2D:
 116       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
 117          /* Storage images are always plain 2-D, not cube */
 118          return SURFTYPE_2D;
 119       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 120          return SURFTYPE_CUBE;
 121       } else {
 122          return SURFTYPE_2D;
 123       }
 124    case ISL_SURF_DIM_3D:
 125       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 126       return SURFTYPE_3D;
 127    }
 128 }
 129
 130 /**
 131  * Get the horizontal and vertical alignment in the units expected by the
 132  * hardware.  Note that this does NOT give you the actual hardware enum values
 133  * but an index into the isl_to_gen_[hv]align arrays above.
 134  */
 135 static inline struct isl_extent3d
 136 get_image_alignment(const struct isl_surf *surf)
 137 {
 138    if (GEN_GEN >= 9) {
 139       if (isl_tiling_is_std_y(surf->tiling) ||
 140           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 141          /* The hardware ignores the alignment values. Anyway, the surface's
 142           * true alignment is likely outside the enum range of HALIGN* and
 143           * VALIGN*.
 144           */
 145          return isl_extent3d(4, 4, 1);
 146       } else {
 147          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 148           * of surface elements (not pixels nor samples). For compressed formats,
 149           * a "surface element" is defined as a compression block.  For example,
 150           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 151           * format (ETC2 has a block height of 4), then the vertical alignment is
 152           * 4 compression blocks or, equivalently, 16 pixels.
 153           */
 154          return isl_surf_get_image_alignment_el(surf);
 155       }
 156    } else {
 157       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 158        * units of surface samples.  For example, if SurfaceVerticalAlignment
 159        * is VALIGN_4 and the surface is singlesampled, then for any surface
 160        * format (compressed or not) the vertical alignment is
 161        * 4 pixels.
 162        */
 163       return isl_surf_get_image_alignment_sa(surf);
 164    }
 165 }
 166
 167 #if GEN_GEN >= 8
 168 static uint32_t
 169 get_qpitch(const struct isl_surf *surf)
 170 {
 171    switch (surf->dim_layout) {
 172    default:
 173       unreachable("Bad isl_surf_dim");
 174    case ISL_DIM_LAYOUT_GEN4_2D:
 175    case ISL_DIM_LAYOUT_GEN4_3D:
 176       if (GEN_GEN >= 9) {
 177          return isl_surf_get_array_pitch_el_rows(surf);
 178       } else {
 179          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 180           *
 181           *    "This field must be set to an integer multiple of the Surface
 182           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 183           *    ETC*, and EAC* Surface Formats), this field is in units of
 184           *    rows in the uncompressed surface, and must be set to an
 185           *    integer multiple of the vertical alignment parameter "j"
 186           *    defined in the Common Surface Formats section."
 187           */
 188          return isl_surf_get_array_pitch_sa_rows(surf);
 189       }
 190    case ISL_DIM_LAYOUT_GEN9_1D:
 191       /* QPitch is usually expressed as rows of surface elements (where
 192        * a surface element is an compression block or a single surface
 193        * sample). Skylake 1D is an outlier.
 194        *
 195        * From the Skylake BSpec >> Memory Views >> Common Surface
 196        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 197        *
 198        *    Surface QPitch specifies the distance in pixels between array
 199        *    slices.
 200        */
 201       return isl_surf_get_array_pitch_el(surf);
 202    }
 203 }
 204 #endif /* GEN_GEN >= 8 */
 205
 206 void
 207 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 208                             const struct isl_surf_fill_state_info *restrict info)
 209 {
 210    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 211
 212    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 213    s.SurfaceFormat = info->view->format;
 214
 215 #if GEN_IS_HASWELL
 216    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 217 #endif
 218
 219    s.Width = info->surf->logical_level0_px.width - 1;
 220    s.Height = info->surf->logical_level0_px.height - 1;
 221
 222    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 223     * (Surface Arrays For all surfaces other than separate stencil buffer):
 224     *
 225     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 226     *  calculated in the equation above , for every other odd Surface Height
 227     *  starting from 1 i.e. 1,5,9,13"
 228     *
 229     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 230     * input for the rendering surface to achieve the same qpitch. For the
 231     * affected heights, we increment the height by 1 for the rendering
 232     * surface.
 233     */
 234    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 235        info->surf->samples > 1 &&
 236        (info->surf->logical_level0_px.height % 4) == 1)
 237       s.Height++;
 238
 239    switch (s.SurfaceType) {
 240    case SURFTYPE_1D:
 241    case SURFTYPE_2D:
 242       s.MinimumArrayElement = info->view->base_array_layer;
 243
 244       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 245        *
 246        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 247        *    by one for each increase from zero of Minimum Array Element. For
 248        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 249        *    the range of this field is reduced to [0,1023].
 250        *
 251        * In other words, 'Depth' is the number of array layers.
 252        */
 253       s.Depth = info->view->array_len - 1;
 254
 255       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 256        *
 257        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 258        *    This field must be set to the same value as the Depth field.
 259        */
 260       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 261                                ISL_SURF_USAGE_STORAGE_BIT))
 262          s.RenderTargetViewExtent = s.Depth;
 263       break;
 264    case SURFTYPE_CUBE:
 265       s.MinimumArrayElement = info->view->base_array_layer;
 266       /* Same as SURFTYPE_2D, but divided by 6 */
 267       s.Depth = info->view->array_len / 6 - 1;
 268       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 269                                ISL_SURF_USAGE_STORAGE_BIT))
 270          s.RenderTargetViewExtent = s.Depth;
 271       break;
 272    case SURFTYPE_3D:
 273       s.MinimumArrayElement = info->view->base_array_layer;
 274
 275       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 276        *
 277        *    If the volume texture is MIP-mapped, this field specifies the
 278        *    depth of the base MIP level.
 279        */
 280       s.Depth = info->surf->logical_level0_px.depth - 1;
 281
 282       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 283        *
 284        *    For Render Target and Typed Dataport 3D Surfaces: This field
 285        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 286        *    the LOD currently being rendered to.
 287        *
 288        * The docs specify that this only matters for render targets and
 289        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 290        * Depth field has more bits than RenderTargetViewExtent so we can have
 291        * textures with more levels than we can render to.  In order to prevent
 292        * assert-failures in the packing function below, we only set the field
 293        * when it's actually going to be used by the hardware.
 294        */
 295       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 296                                ISL_SURF_USAGE_STORAGE_BIT)) {
 297          s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 298                                                info->view->base_level) - 1;
 299       }
 300       break;
 301    default:
 302       unreachable("bad SurfaceType");
 303    }
 304
 305 #if GEN_GEN >= 7
 306    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 307 #endif
 308
 309    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 310       /* For render target surfaces, the hardware interprets field
 311        * MIPCount/LOD as LOD. The Broadwell PRM says:
 312        *
 313        *    MIPCountLOD defines the LOD that will be rendered into.
 314        *    SurfaceMinLOD is ignored.
 315        */
 316       s.MIPCountLOD = info->view->base_level;
 317       s.SurfaceMinLOD = 0;
 318    } else {
 319       /* For non render target surfaces, the hardware interprets field
 320        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 321        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 322        */
 323       s.SurfaceMinLOD = info->view->base_level;
 324       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 325    }
 326
 327 #if GEN_GEN >= 9
 328    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 329     * Start LOD" to 15 to prevent the hardware from trying to use them.
 330     */
 331    s.TiledResourceMode = NONE;
 332    s.MipTailStartLOD = 15;
 333 #endif
 334
 335 #if GEN_GEN >= 6
 336    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 337    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 338 #if GEN_GEN >= 7
 339    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 340 #endif
 341 #endif
 342
 343    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 344       /* For gen9 1-D textures, surface pitch is ignored */
 345       s.SurfacePitch = 0;
 346    } else {
 347       s.SurfacePitch = info->surf->row_pitch - 1;
 348    }
 349
 350 #if GEN_GEN >= 8
 351    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 352 #elif GEN_GEN == 7
 353    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 354                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 355 #endif
 356
 357 #if GEN_GEN >= 8
 358    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 359 #else
 360    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 361    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 362                                                       TILEWALK_XMAJOR,
 363 #endif
 364
 365 #if GEN_GEN >= 8
 366    s.RenderCacheReadWriteMode = WriteOnlyCache;
 367 #else
 368    s.RenderCacheReadWriteMode = 0;
 369 #endif
 370
 371    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 372 #if GEN_GEN >= 8
 373       s.CubeFaceEnablePositiveZ = 1;
 374       s.CubeFaceEnableNegativeZ = 1;
 375       s.CubeFaceEnablePositiveY = 1;
 376       s.CubeFaceEnableNegativeY = 1;
 377       s.CubeFaceEnablePositiveX = 1;
 378       s.CubeFaceEnableNegativeX = 1;
 379 #else
 380       s.CubeFaceEnables = 0x3f;
 381 #endif
 382    }
 383
 384 #if GEN_GEN >= 6
 385    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 386 #if GEN_GEN >= 7
 387    s.MultisampledSurfaceStorageFormat =
 388       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 389 #endif
 390 #endif
 391
 392 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 393    s.ShaderChannelSelectRed = info->view->channel_select[0];
 394    s.ShaderChannelSelectGreen = info->view->channel_select[1];
 395    s.ShaderChannelSelectBlue = info->view->channel_select[2];
 396    s.ShaderChannelSelectAlpha = info->view->channel_select[3];
 397 #endif
 398
 399    s.SurfaceBaseAddress = info->address;
 400
 401 #if GEN_GEN >= 6
 402    s.MOCS = info->mocs;
 403 #endif
 404
 405 #if GEN_GEN > 4 || GEN_IS_G4X
 406    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 407       /* There are fairly strict rules about when the offsets can be used.
 408        * These are mostly taken from the Sky Lake PRM documentation for
 409        * RENDER_SURFACE_STATE.
 410        */
 411       assert(info->surf->tiling != ISL_TILING_LINEAR);
 412       assert(info->surf->dim == ISL_SURF_DIM_2D);
 413       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 414       assert(info->surf->levels == 1);
 415       assert(info->surf->logical_level0_px.array_len == 1);
 416       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 417 #if GEN_GEN >= 7
 418       s.SurfaceArray = false;
 419 #endif
 420    }
 421
 422    const unsigned x_div = 4;
 423    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 424    assert(info->x_offset_sa % x_div == 0);
 425    assert(info->y_offset_sa % y_div == 0);
 426    s.XOffset = info->x_offset_sa / x_div;
 427    s.YOffset = info->y_offset_sa / y_div;
 428 #else
 429    assert(info->x_offset_sa == 0);
 430    assert(info->y_offset_sa == 0);
 431 #endif
 432
 433 #if GEN_GEN >= 7
 434    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 435       struct isl_tile_info tile_info;
 436       isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
 437       uint32_t pitch_in_tiles =
 438          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 439
 440 #if GEN_GEN >= 8
 441       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 442       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 443       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 444        * doesn't expect our definition of the compression, it expects qpitch
 445        * in units of samples on the main surface.
 446        */
 447       s.AuxiliarySurfaceQPitch =
 448          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 449       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 450       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 451 #else
 452       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 453              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 454       s.MCSBaseAddress = info->aux_address,
 455       s.MCSSurfacePitch = pitch_in_tiles - 1;
 456       s.MCSEnable = true;
 457 #endif
 458    }
 459 #endif
 460
 461 #if GEN_GEN >= 8
 462    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 463     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 464     *
 465     *    This bit must be set for the following surface types: BC2_UNORM
 466     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 467     */
 468    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 469       switch (info->view->format) {
 470       case ISL_FORMAT_BC2_UNORM:
 471       case ISL_FORMAT_BC3_UNORM:
 472       case ISL_FORMAT_BC5_UNORM:
 473       case ISL_FORMAT_BC5_SNORM:
 474       case ISL_FORMAT_BC7_UNORM:
 475          s.SamplerL2BypassModeDisable = true;
 476          break;
 477       default:
 478          break;
 479       }
 480    }
 481 #endif
 482
 483 #if GEN_GEN >= 9
 484    s.RedClearColor = info->clear_color.u32[0];
 485    s.GreenClearColor = info->clear_color.u32[1];
 486    s.BlueClearColor = info->clear_color.u32[2];
 487    s.AlphaClearColor = info->clear_color.u32[3];
 488 #elif GEN_GEN >= 7
 489    /* Prior to Sky Lake, we only have one bit for the clear color which
 490     * gives us 0 or 1 in whatever the surface's format happens to be.
 491     */
 492    if (isl_format_has_int_channel(info->view->format)) {
 493       for (unsigned i = 0; i < 4; i++) {
 494          assert(info->clear_color.u32[i] == 0 ||
 495                 info->clear_color.u32[i] == 1);
 496       }
 497       s.RedClearColor = info->clear_color.u32[0] != 0;
 498       s.GreenClearColor = info->clear_color.u32[1] != 0;
 499       s.BlueClearColor = info->clear_color.u32[2] != 0;
 500       s.AlphaClearColor = info->clear_color.u32[3] != 0;
 501    } else {
 502       for (unsigned i = 0; i < 4; i++) {
 503          assert(info->clear_color.f32[i] == 0.0f ||
 504                 info->clear_color.f32[i] == 1.0f);
 505       }
 506       s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 507       s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 508       s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 509       s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 510    }
 511 #endif
 512
 513    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 514 }
 515
 516 void
 517 isl_genX(buffer_fill_state_s)(void *state,
 518                               const struct isl_buffer_fill_state_info *restrict info)
 519 {
 520    uint32_t num_elements = info->size / info->stride;
 521
 522    if (GEN_GEN >= 7) {
 523       /* From the IVB PRM, SURFACE_STATE::Height,
 524        *
 525        *    For typed buffer and structured buffer surfaces, the number
 526        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 527        *    surfaces, the number of entries in the buffer is the number of bytes
 528        *    which can range from 1 to 2^30.
 529        */
 530       if (info->format == ISL_FORMAT_RAW) {
 531          assert(num_elements <= (1ull << 30));
 532          assert((num_elements & 3) == 0);
 533       } else {
 534          assert(num_elements <= (1ull << 27));
 535       }
 536    } else {
 537       assert(num_elements <= (1ull << 27));
 538    }
 539
 540    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 541
 542    s.SurfaceType = SURFTYPE_BUFFER;
 543    s.SurfaceFormat = info->format;
 544
 545 #if GEN_GEN >= 6
 546    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 547 #if GEN_GEN >= 7
 548    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 549    s.SurfaceArray = false;
 550 #endif
 551 #endif
 552
 553 #if GEN_GEN >= 7
 554    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 555    s.Width = (num_elements - 1) & 0x7f;
 556    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 557 #else
 558    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 559    s.Width = (num_elements - 1) & 0x7f;
 560    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 561 #endif
 562
 563    s.SurfacePitch = info->stride - 1;
 564
 565 #if GEN_GEN >= 6
 566    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 567 #endif
 568
 569 #if (GEN_GEN >= 8)
 570    s.TileMode = LINEAR;
 571 #else
 572    s.TiledSurface = false;
 573 #endif
 574
 575 #if (GEN_GEN >= 8)
 576    s.RenderCacheReadWriteMode = WriteOnlyCache;
 577 #else
 578    s.RenderCacheReadWriteMode = 0;
 579 #endif
 580
 581    s.SurfaceBaseAddress = info->address;
 582 #if GEN_GEN >= 6
 583    s.MOCS = info->mocs;
 584 #endif
 585
 586 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 587    s.ShaderChannelSelectRed = SCS_RED;
 588    s.ShaderChannelSelectGreen = SCS_GREEN;
 589    s.ShaderChannelSelectBlue = SCS_BLUE;
 590    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 591 #endif
 592
 593    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 594 }