2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
30 __gen_combine_address(__attribute__((unused
)) void *data
,
31 __attribute__((unused
)) void *loc
, uint64_t addr
,
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
43 static const uint8_t isl_to_gen_halign
[] = {
49 static const uint8_t isl_to_gen_halign
[] = {
56 static const uint8_t isl_to_gen_valign
[] = {
62 static const uint8_t isl_to_gen_valign
[] = {
69 static const uint8_t isl_to_gen_tiling
[] = {
70 [ISL_TILING_LINEAR
] = LINEAR
,
71 [ISL_TILING_X
] = XMAJOR
,
72 [ISL_TILING_Y0
] = YMAJOR
,
73 [ISL_TILING_Yf
] = YMAJOR
,
74 [ISL_TILING_Ys
] = YMAJOR
,
76 [ISL_TILING_W
] = WMAJOR
,
82 static const uint32_t isl_to_gen_multisample_layout
[] = {
83 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
84 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
85 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
90 static const uint32_t isl_to_gen_aux_mode
[] = {
91 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
92 [ISL_AUX_USAGE_MCS
] = AUX_CCS_E
,
93 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
94 [ISL_AUX_USAGE_MCS_CCS
] = AUX_MCS_LCE
,
97 static const uint32_t isl_to_gen_aux_mode
[] = {
98 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
99 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
100 [ISL_AUX_USAGE_MCS
] = AUX_CCS_D
,
101 [ISL_AUX_USAGE_CCS_D
] = AUX_CCS_D
,
102 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
105 static const uint32_t isl_to_gen_aux_mode
[] = {
106 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
107 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
108 [ISL_AUX_USAGE_MCS
] = AUX_MCS
,
109 [ISL_AUX_USAGE_CCS_D
] = AUX_MCS
,
114 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
118 unreachable("bad isl_surf_dim");
119 case ISL_SURF_DIM_1D
:
120 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
122 case ISL_SURF_DIM_2D
:
123 if ((usage
& ISL_SURF_USAGE_CUBE_BIT
) &&
124 (usage
& ISL_SURF_USAGE_TEXTURE_BIT
)) {
125 /* We need SURFTYPE_CUBE to make cube sampling work */
126 return SURFTYPE_CUBE
;
128 /* Everything else (render and storage) treat cubes as plain
133 case ISL_SURF_DIM_3D
:
134 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
140 * Get the horizontal and vertical alignment in the units expected by the
141 * hardware. Note that this does NOT give you the actual hardware enum values
142 * but an index into the isl_to_gen_[hv]align arrays above.
144 UNUSED
static struct isl_extent3d
145 get_image_alignment(const struct isl_surf
*surf
)
148 if (isl_tiling_is_std_y(surf
->tiling
) ||
149 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
150 /* The hardware ignores the alignment values. Anyway, the surface's
151 * true alignment is likely outside the enum range of HALIGN* and
154 return isl_extent3d(4, 4, 1);
156 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
157 * of surface elements (not pixels nor samples). For compressed formats,
158 * a "surface element" is defined as a compression block. For example,
159 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
160 * format (ETC2 has a block height of 4), then the vertical alignment is
161 * 4 compression blocks or, equivalently, 16 pixels.
163 return isl_surf_get_image_alignment_el(surf
);
166 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
167 * units of surface samples. For example, if SurfaceVerticalAlignment
168 * is VALIGN_4 and the surface is singlesampled, then for any surface
169 * format (compressed or not) the vertical alignment is
172 return isl_surf_get_image_alignment_sa(surf
);
178 get_qpitch(const struct isl_surf
*surf
)
180 switch (surf
->dim_layout
) {
182 unreachable("Bad isl_surf_dim");
183 case ISL_DIM_LAYOUT_GEN4_2D
:
185 if (surf
->dim
== ISL_SURF_DIM_3D
&& surf
->tiling
== ISL_TILING_W
) {
186 /* This is rather annoying and completely undocumented. It
187 * appears that the hardware has a bug (or undocumented feature)
188 * regarding stencil buffers most likely related to the way
189 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
190 * stencil buffer normally, and use texelFetch on it, the z or
191 * array index will get implicitly multiplied by 2 for no obvious
192 * reason. The fix appears to be to divide qpitch by 2 for
195 return isl_surf_get_array_pitch_el_rows(surf
) / 2;
197 return isl_surf_get_array_pitch_el_rows(surf
);
200 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
202 * "This field must be set to an integer multiple of the Surface
203 * Vertical Alignment. For compressed textures (BC*, FXT1,
204 * ETC*, and EAC* Surface Formats), this field is in units of
205 * rows in the uncompressed surface, and must be set to an
206 * integer multiple of the vertical alignment parameter "j"
207 * defined in the Common Surface Formats section."
209 return isl_surf_get_array_pitch_sa_rows(surf
);
211 case ISL_DIM_LAYOUT_GEN9_1D
:
212 /* QPitch is usually expressed as rows of surface elements (where
213 * a surface element is an compression block or a single surface
214 * sample). Skylake 1D is an outlier.
216 * From the Skylake BSpec >> Memory Views >> Common Surface
217 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
219 * Surface QPitch specifies the distance in pixels between array
222 return isl_surf_get_array_pitch_el(surf
);
223 case ISL_DIM_LAYOUT_GEN4_3D
:
224 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
225 * different pitch at each LOD. Also, the QPitch field is ignored for
226 * these surfaces. From the Broadwell PRM documentation for QPitch:
228 * This field specifies the distance in rows between array slices. It
229 * is used only in the following cases:
230 * - Surface Array is enabled OR
231 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
232 * Surface Storage Format set to MSFMT_MSS OR
233 * - Surface Type is SURFTYPE_CUBE
235 * None of the three conditions above can possibly apply to a 3D surface
236 * so it is safe to just set QPitch to 0.
241 #endif /* GEN_GEN >= 8 */
244 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
245 const struct isl_surf_fill_state_info
*restrict info
)
247 struct GENX(RENDER_SURFACE_STATE
) s
= { 0 };
249 s
.SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
);
251 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
252 assert(isl_format_supports_rendering(dev
->info
, info
->view
->format
));
253 else if (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
)
254 assert(isl_format_supports_sampling(dev
->info
, info
->view
->format
));
256 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
258 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
259 * format if the Surface Type is SURFTYPE_1D
261 if (info
->surf
->dim
== ISL_SURF_DIM_1D
)
262 assert(!isl_format_is_compressed(info
->view
->format
));
264 if (isl_format_is_compressed(info
->surf
->format
)) {
265 /* You're not allowed to make a view of a compressed format with any
266 * format other than the surface format. None of the userspace APIs
267 * allow for this directly and doing so would mess up a number of
268 * surface parameters such as Width, Height, and alignments. Ideally,
269 * we'd like to assert that the two formats match. However, we have an
270 * S3TC workaround that requires us to do reinterpretation. So assert
271 * that they're at least the same bpb and block size.
273 ASSERTED
const struct isl_format_layout
*surf_fmtl
=
274 isl_format_get_layout(info
->surf
->format
);
275 ASSERTED
const struct isl_format_layout
*view_fmtl
=
276 isl_format_get_layout(info
->surf
->format
);
277 assert(surf_fmtl
->bpb
== view_fmtl
->bpb
);
278 assert(surf_fmtl
->bw
== view_fmtl
->bw
);
279 assert(surf_fmtl
->bh
== view_fmtl
->bh
);
282 s
.SurfaceFormat
= info
->view
->format
;
285 s
.DepthStencilResource
=
286 isl_surf_usage_is_depth_or_stencil(info
->surf
->usage
);
290 s
.ColorBufferComponentWriteDisables
= info
->write_disables
;
292 assert(info
->write_disables
== 0);
296 s
.IntegerSurfaceFormat
=
297 isl_format_has_int_channel((enum isl_format
) s
.SurfaceFormat
);
300 assert(info
->surf
->logical_level0_px
.width
> 0 &&
301 info
->surf
->logical_level0_px
.height
> 0);
303 s
.Width
= info
->surf
->logical_level0_px
.width
- 1;
304 s
.Height
= info
->surf
->logical_level0_px
.height
- 1;
306 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
307 * (Surface Arrays For all surfaces other than separate stencil buffer):
309 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
310 * calculated in the equation above , for every other odd Surface Height
311 * starting from 1 i.e. 1,5,9,13"
313 * Since this Qpitch errata only impacts the sampler, we have to adjust the
314 * input for the rendering surface to achieve the same qpitch. For the
315 * affected heights, we increment the height by 1 for the rendering
318 if (GEN_GEN
== 6 && (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
319 info
->surf
->samples
> 1 &&
320 (info
->surf
->logical_level0_px
.height
% 4) == 1)
323 switch (s
.SurfaceType
) {
326 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
328 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
329 * must be set to zero if this surface is used with sampling engine
332 * This restriction appears to exist only on Ivy Bridge.
334 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !ISL_DEV_IS_BAYTRAIL(dev
) &&
335 (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
) &&
336 info
->surf
->samples
> 1)
337 assert(info
->view
->base_array_layer
== 0);
339 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
341 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
343 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
344 * by one for each increase from zero of Minimum Array Element. For
345 * example, if Minimum Array Element is set to 1024 on a 2D surface,
346 * the range of this field is reduced to [0,1023].
348 * In other words, 'Depth' is the number of array layers.
350 s
.Depth
= info
->view
->array_len
- 1;
352 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
354 * For Render Target and Typed Dataport 1D and 2D Surfaces:
355 * This field must be set to the same value as the Depth field.
357 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
358 ISL_SURF_USAGE_STORAGE_BIT
))
359 s
.RenderTargetViewExtent
= s
.Depth
;
362 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
363 /* Same as SURFTYPE_2D, but divided by 6 */
364 s
.Depth
= info
->view
->array_len
/ 6 - 1;
365 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
366 ISL_SURF_USAGE_STORAGE_BIT
))
367 s
.RenderTargetViewExtent
= s
.Depth
;
370 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
372 * If the volume texture is MIP-mapped, this field specifies the
373 * depth of the base MIP level.
375 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
377 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
379 * For Render Target and Typed Dataport 3D Surfaces: This field
380 * indicates the extent of the accessible 'R' coordinates minus 1 on
381 * the LOD currently being rendered to.
383 * The docs specify that this only matters for render targets and
384 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
385 * Depth field has more bits than RenderTargetViewExtent so we can have
386 * textures with more levels than we can render to. In order to prevent
387 * assert-failures in the packing function below, we only set the field
388 * when it's actually going to be used by the hardware.
390 * Similaraly, the MinimumArrayElement field is ignored by all hardware
391 * prior to Sky Lake when texturing and we want it set to 0 anyway.
392 * Since it's already initialized to 0, we can just leave it alone for
395 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
396 ISL_SURF_USAGE_STORAGE_BIT
)) {
397 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
398 s
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
402 unreachable("bad SurfaceType");
406 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
;
409 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
410 /* For render target surfaces, the hardware interprets field
411 * MIPCount/LOD as LOD. The Broadwell PRM says:
413 * MIPCountLOD defines the LOD that will be rendered into.
414 * SurfaceMinLOD is ignored.
416 s
.MIPCountLOD
= info
->view
->base_level
;
419 /* For non render target surfaces, the hardware interprets field
420 * MIPCount/LOD as MIPCount. The range of levels accessible by the
421 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
423 s
.SurfaceMinLOD
= info
->view
->base_level
;
424 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
428 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
429 * Start LOD" to 15 to prevent the hardware from trying to use them.
431 s
.TiledResourceMode
= NONE
;
432 s
.MipTailStartLOD
= 15;
436 const struct isl_extent3d image_align
= get_image_alignment(info
->surf
);
437 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[image_align
.height
];
439 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[image_align
.width
];
443 if (info
->surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
444 /* For gen9 1-D textures, surface pitch is ignored */
447 s
.SurfacePitch
= info
->surf
->row_pitch_B
- 1;
451 s
.SurfaceQPitch
= get_qpitch(info
->surf
) >> 2;
453 s
.SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
454 ISL_ARRAY_PITCH_SPAN_COMPACT
;
458 assert(GEN_GEN
< 12 || info
->surf
->tiling
!= ISL_TILING_W
);
459 s
.TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
];
461 s
.TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
462 s
.TileWalk
= info
->surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
467 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
469 s
.RenderCacheReadWriteMode
= 0;
473 /* We've seen dEQP failures when enabling this bit with UINT formats,
474 * which particularly affects blorp_copy() operations. It shouldn't
475 * have any effect on UINT textures anyway, so disable it for them.
477 s
.EnableUnormPathInColorPipe
=
478 !isl_format_has_int_channel(info
->view
->format
);
481 s
.CubeFaceEnablePositiveZ
= 1;
482 s
.CubeFaceEnableNegativeZ
= 1;
483 s
.CubeFaceEnablePositiveY
= 1;
484 s
.CubeFaceEnableNegativeY
= 1;
485 s
.CubeFaceEnablePositiveX
= 1;
486 s
.CubeFaceEnableNegativeX
= 1;
489 s
.NumberofMultisamples
= ffs(info
->surf
->samples
) - 1;
491 s
.MultisampledSurfaceStorageFormat
=
492 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
];
496 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
497 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
498 assert(isl_swizzle_supports_rendering(dev
->info
, info
->view
->swizzle
));
500 s
.ShaderChannelSelectRed
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.r
;
501 s
.ShaderChannelSelectGreen
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.g
;
502 s
.ShaderChannelSelectBlue
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.b
;
503 s
.ShaderChannelSelectAlpha
= (enum GENX(ShaderChannelSelect
)) info
->view
->swizzle
.a
;
505 assert(isl_swizzle_is_identity(info
->view
->swizzle
));
508 s
.SurfaceBaseAddress
= info
->address
;
514 #if GEN_GEN > 4 || GEN_IS_G4X
515 if (info
->x_offset_sa
!= 0 || info
->y_offset_sa
!= 0) {
516 /* There are fairly strict rules about when the offsets can be used.
517 * These are mostly taken from the Sky Lake PRM documentation for
518 * RENDER_SURFACE_STATE.
520 assert(info
->surf
->tiling
!= ISL_TILING_LINEAR
);
521 assert(info
->surf
->dim
== ISL_SURF_DIM_2D
);
522 assert(isl_is_pow2(isl_format_get_layout(info
->view
->format
)->bpb
));
523 assert(info
->surf
->levels
== 1);
524 assert(info
->surf
->logical_level0_px
.array_len
== 1);
525 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
528 /* Broadwell added more rules. */
529 assert(info
->surf
->samples
== 1);
530 if (isl_format_get_layout(info
->view
->format
)->bpb
== 8)
531 assert(info
->x_offset_sa
% 16 == 0);
532 if (isl_format_get_layout(info
->view
->format
)->bpb
== 16)
533 assert(info
->x_offset_sa
% 8 == 0);
537 s
.SurfaceArray
= false;
541 const unsigned x_div
= 4;
542 const unsigned y_div
= GEN_GEN
>= 8 ? 4 : 2;
543 assert(info
->x_offset_sa
% x_div
== 0);
544 assert(info
->y_offset_sa
% y_div
== 0);
545 s
.XOffset
= info
->x_offset_sa
/ x_div
;
546 s
.YOffset
= info
->y_offset_sa
/ y_div
;
548 assert(info
->x_offset_sa
== 0);
549 assert(info
->y_offset_sa
== 0);
553 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
554 /* Check valid aux usages per-gen */
556 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
557 info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
558 info
->aux_usage
== ISL_AUX_USAGE_MCS_CCS
);
559 } else if (GEN_GEN
>= 9) {
560 assert(info
->aux_usage
== ISL_AUX_USAGE_HIZ
||
561 info
->aux_usage
== ISL_AUX_USAGE_MCS
||
562 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
||
563 info
->aux_usage
== ISL_AUX_USAGE_CCS_E
);
564 } else if (GEN_GEN
>= 8) {
565 assert(info
->aux_usage
== ISL_AUX_USAGE_HIZ
||
566 info
->aux_usage
== ISL_AUX_USAGE_MCS
||
567 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
568 } else if (GEN_GEN
>= 7) {
569 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
570 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
574 /* We don't need an auxiliary surface for CCS on gen12+ */
575 assert (info
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
576 info
->aux_usage
== ISL_AUX_USAGE_MC
|| info
->aux_surf
);
578 /* We must have an auxiliary surface */
579 assert(info
->aux_surf
);
582 /* The docs don't appear to say anything whatsoever about compression
583 * and the data port. Testing seems to indicate that the data port
584 * completely ignores the AuxiliarySurfaceMode field.
586 assert(!(info
->view
->usage
& ISL_SURF_USAGE_STORAGE_BIT
));
588 if (info
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
589 /* The number of samples must be 1 */
590 assert(info
->surf
->samples
== 1);
592 /* The dimension must not be 3D */
593 assert(info
->surf
->dim
!= ISL_SURF_DIM_3D
);
595 /* The format must be one of the following: */
596 switch (info
->view
->format
) {
597 case ISL_FORMAT_R32_FLOAT
:
598 case ISL_FORMAT_R24_UNORM_X8_TYPELESS
:
599 case ISL_FORMAT_R16_UNORM
:
602 assert(!"Incompatible HiZ Sampling format");
608 s
.AuxiliarySurfaceMode
= isl_to_gen_aux_mode
[info
->aux_usage
];
614 /* The auxiliary buffer info is filled when it's useable by the HW. On
615 * gen12 and above, CCS is controlled by the aux table and not the
616 * auxiliary surface information in SURFACE_STATE.
618 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
&&
619 ((info
->aux_usage
!= ISL_AUX_USAGE_MC
&&
620 info
->aux_usage
!= ISL_AUX_USAGE_CCS_E
) || GEN_GEN
<= 11)) {
622 assert(info
->aux_surf
!= NULL
);
624 struct isl_tile_info tile_info
;
625 isl_surf_get_tile_info(info
->aux_surf
, &tile_info
);
626 uint32_t pitch_in_tiles
=
627 info
->aux_surf
->row_pitch_B
/ tile_info
.phys_extent_B
.width
;
629 s
.AuxiliarySurfaceBaseAddress
= info
->aux_address
;
630 s
.AuxiliarySurfacePitch
= pitch_in_tiles
- 1;
633 /* Auxiliary surfaces in ISL have compressed formats but the hardware
634 * doesn't expect our definition of the compression, it expects qpitch
635 * in units of samples on the main surface.
637 s
.AuxiliarySurfaceQPitch
=
638 isl_surf_get_array_pitch_sa_rows(info
->aux_surf
) >> 2;
643 #if GEN_GEN >= 8 && GEN_GEN < 11
644 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
645 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
647 * This bit must be set for the following surface types: BC2_UNORM
648 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
650 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
651 switch (info
->view
->format
) {
652 case ISL_FORMAT_BC2_UNORM
:
653 case ISL_FORMAT_BC3_UNORM
:
654 case ISL_FORMAT_BC5_UNORM
:
655 case ISL_FORMAT_BC5_SNORM
:
656 case ISL_FORMAT_BC7_UNORM
:
657 s
.SamplerL2BypassModeDisable
= true;
660 /* From the SKL PRM, Programming Note under Sampler Output Channel
663 * If a surface has an associated HiZ Auxilliary surface, the
664 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
667 if (GEN_GEN
>= 9 && info
->aux_usage
== ISL_AUX_USAGE_HIZ
)
668 s
.SamplerL2BypassModeDisable
= true;
674 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
675 if (info
->use_clear_address
) {
677 s
.ClearValueAddressEnable
= true;
678 s
.ClearValueAddress
= info
->clear_address
;
680 unreachable("Gen9 and earlier do not support indirect clear colors");
686 * From BXML > GT > Shared Functions > vol5c Shared Functions >
687 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
691 * "Enables Pixel backend hw to convert clear values into native format
692 * and write back to clear address, so that display and sampler can use
693 * the converted value for resolving fast cleared RTs."
696 * Clear color conversion must be enabled if the clear color is stored
697 * indirectly and fast color clears are enabled.
699 if (info
->use_clear_address
) {
700 s
.ClearColorConversionEnable
= true;
705 assert(info
->use_clear_address
);
707 if (!info
->use_clear_address
) {
708 s
.RedClearColor
= info
->clear_color
.u32
[0];
709 s
.GreenClearColor
= info
->clear_color
.u32
[1];
710 s
.BlueClearColor
= info
->clear_color
.u32
[2];
711 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
714 /* Prior to Sky Lake, we only have one bit for the clear color which
715 * gives us 0 or 1 in whatever the surface's format happens to be.
717 if (isl_format_has_int_channel(info
->view
->format
)) {
718 for (unsigned i
= 0; i
< 4; i
++) {
719 assert(info
->clear_color
.u32
[i
] == 0 ||
720 info
->clear_color
.u32
[i
] == 1);
722 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
723 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
724 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
725 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
727 for (unsigned i
= 0; i
< 4; i
++) {
728 assert(info
->clear_color
.f32
[i
] == 0.0f
||
729 info
->clear_color
.f32
[i
] == 1.0f
);
731 s
.RedClearColor
= info
->clear_color
.f32
[0] != 0.0f
;
732 s
.GreenClearColor
= info
->clear_color
.f32
[1] != 0.0f
;
733 s
.BlueClearColor
= info
->clear_color
.f32
[2] != 0.0f
;
734 s
.AlphaClearColor
= info
->clear_color
.f32
[3] != 0.0f
;
739 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
743 isl_genX(buffer_fill_state_s
)(const struct isl_device
*dev
, void *state
,
744 const struct isl_buffer_fill_state_info
*restrict info
)
746 uint64_t buffer_size
= info
->size_B
;
748 /* Uniform and Storage buffers need to have surface size not less that the
749 * aligned 32-bit size of the buffer. To calculate the array lenght on
750 * unsized arrays in StorageBuffer the last 2 bits store the padding size
751 * added to the surface, so we can calculate latter the original buffer
752 * size to know the number of elements.
754 * surface_size = isl_align(buffer_size, 4) +
755 * (isl_align(buffer_size) - buffer_size)
757 * buffer_size = (surface_size & ~3) - (surface_size & 3)
759 if (info
->format
== ISL_FORMAT_RAW
||
760 info
->stride_B
< isl_format_get_layout(info
->format
)->bpb
/ 8) {
761 assert(info
->stride_B
== 1);
762 uint64_t aligned_size
= isl_align(buffer_size
, 4);
763 buffer_size
= aligned_size
+ (aligned_size
- buffer_size
);
766 uint32_t num_elements
= buffer_size
/ info
->stride_B
;
769 /* From the IVB PRM, SURFACE_STATE::Height,
771 * For typed buffer and structured buffer surfaces, the number
772 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
773 * surfaces, the number of entries in the buffer is the number of bytes
774 * which can range from 1 to 2^30.
776 if (info
->format
== ISL_FORMAT_RAW
) {
777 assert(num_elements
<= (1ull << 30));
778 assert(num_elements
> 0);
780 assert(num_elements
<= (1ull << 27));
783 assert(num_elements
<= (1ull << 27));
786 struct GENX(RENDER_SURFACE_STATE
) s
= { 0, };
788 s
.SurfaceType
= SURFTYPE_BUFFER
;
789 s
.SurfaceFormat
= info
->format
;
792 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[4];
794 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[4];
795 s
.SurfaceArray
= false;
800 s
.Height
= ((num_elements
- 1) >> 7) & 0x3fff;
801 s
.Width
= (num_elements
- 1) & 0x7f;
802 s
.Depth
= ((num_elements
- 1) >> 21) & 0x3ff;
804 s
.Height
= ((num_elements
- 1) >> 7) & 0x1fff;
805 s
.Width
= (num_elements
- 1) & 0x7f;
806 s
.Depth
= ((num_elements
- 1) >> 20) & 0x7f;
809 if (GEN_GEN
== 12 && dev
->info
->revision
== 0) {
810 /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
811 * textures with very close base addresses (delta < 64B) to corrupt each
812 * other. We can sort-of work around this by making small buffer
813 * textures 1D textures instead. This doesn't fix the problem for large
814 * buffer textures but the liklihood of large, overlapping, and very
815 * close buffer textures is fairly low and the point is to hack around
816 * the bug so we can run apps and tests.
818 if (info
->format
!= ISL_FORMAT_RAW
&&
819 info
->stride_B
== isl_format_get_layout(info
->format
)->bpb
/ 8 &&
820 num_elements
<= (1 << 14)) {
821 s
.SurfaceType
= SURFTYPE_1D
;
822 s
.Width
= num_elements
- 1;
828 s
.SurfacePitch
= info
->stride_B
- 1;
831 s
.NumberofMultisamples
= MULTISAMPLECOUNT_1
;
837 s
.TiledSurface
= false;
841 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
843 s
.RenderCacheReadWriteMode
= 0;
846 s
.SurfaceBaseAddress
= info
->address
;
851 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
852 s
.ShaderChannelSelectRed
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.r
;
853 s
.ShaderChannelSelectGreen
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.g
;
854 s
.ShaderChannelSelectBlue
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.b
;
855 s
.ShaderChannelSelectAlpha
= (enum GENX(ShaderChannelSelect
)) info
->swizzle
.a
;
858 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
862 isl_genX(null_fill_state
)(void *state
, struct isl_extent3d size
)
864 struct GENX(RENDER_SURFACE_STATE
) s
= {
865 .SurfaceType
= SURFTYPE_NULL
,
866 /* We previously had this format set to B8G8R8A8_UNORM but ran into
867 * hangs on IVB. R32_UINT seems to work for everybody.
869 * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
871 .SurfaceFormat
= ISL_FORMAT_R32_UINT
,
873 .SurfaceArray
= size
.depth
> 1,
878 .TiledSurface
= true,
879 .TileWalk
= TILEWALK_YMAJOR
,
882 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
885 * RENDER_SURFACE_STATE::Surface Vertical Alignment
887 * "This field must be set to VALIGN_4 for all tiled Y Render Target
892 .SurfaceVerticalAlignment
= VALIGN_4
,
894 .Width
= size
.width
- 1,
895 .Height
= size
.height
- 1,
896 .Depth
= size
.depth
- 1,
897 .RenderTargetViewExtent
= size
.depth
- 1,
899 .ColorBufferComponentWriteDisables
= 0xf,
902 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);