2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
29 static inline uint64_t
30 __gen_combine_address(void *data
, void *loc
, uint64_t addr
, uint32_t delta
)
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
40 #define __PASTE2(x, y) x ## y
41 #define __PASTE(x, y) __PASTE2(x, y)
42 #define isl_genX(x) __PASTE(isl_, genX(x))
45 static const uint8_t isl_to_gen_halign
[] = {
51 static const uint8_t isl_to_gen_halign
[] = {
58 static const uint8_t isl_to_gen_valign
[] = {
64 static const uint8_t isl_to_gen_valign
[] = {
71 static const uint8_t isl_to_gen_tiling
[] = {
72 [ISL_TILING_LINEAR
] = LINEAR
,
73 [ISL_TILING_X
] = XMAJOR
,
74 [ISL_TILING_Y0
] = YMAJOR
,
75 [ISL_TILING_Yf
] = YMAJOR
,
76 [ISL_TILING_Ys
] = YMAJOR
,
77 [ISL_TILING_W
] = WMAJOR
,
82 static const uint32_t isl_to_gen_multisample_layout
[] = {
83 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
84 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
85 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
90 static const uint32_t isl_to_gen_aux_mode
[] = {
91 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
92 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
93 [ISL_AUX_USAGE_MCS
] = AUX_CCS_D
,
94 [ISL_AUX_USAGE_CCS_D
] = AUX_CCS_D
,
95 [ISL_AUX_USAGE_CCS_E
] = AUX_CCS_E
,
98 static const uint32_t isl_to_gen_aux_mode
[] = {
99 [ISL_AUX_USAGE_NONE
] = AUX_NONE
,
100 [ISL_AUX_USAGE_HIZ
] = AUX_HIZ
,
101 [ISL_AUX_USAGE_MCS
] = AUX_MCS
,
102 [ISL_AUX_USAGE_CCS_D
] = AUX_MCS
,
107 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
111 unreachable("bad isl_surf_dim");
112 case ISL_SURF_DIM_1D
:
113 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
115 case ISL_SURF_DIM_2D
:
116 if (usage
& ISL_SURF_USAGE_STORAGE_BIT
) {
117 /* Storage images are always plain 2-D, not cube */
119 } else if (usage
& ISL_SURF_USAGE_CUBE_BIT
) {
120 return SURFTYPE_CUBE
;
124 case ISL_SURF_DIM_3D
:
125 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
131 * Get the horizontal and vertical alignment in the units expected by the
132 * hardware. Note that this does NOT give you the actual hardware enum values
133 * but an index into the isl_to_gen_[hv]align arrays above.
135 static inline struct isl_extent3d
136 get_image_alignment(const struct isl_surf
*surf
)
139 if (isl_tiling_is_std_y(surf
->tiling
) ||
140 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
141 /* The hardware ignores the alignment values. Anyway, the surface's
142 * true alignment is likely outside the enum range of HALIGN* and
145 return isl_extent3d(4, 4, 1);
147 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
148 * of surface elements (not pixels nor samples). For compressed formats,
149 * a "surface element" is defined as a compression block. For example,
150 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
151 * format (ETC2 has a block height of 4), then the vertical alignment is
152 * 4 compression blocks or, equivalently, 16 pixels.
154 return isl_surf_get_image_alignment_el(surf
);
157 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
158 * units of surface samples. For example, if SurfaceVerticalAlignment
159 * is VALIGN_4 and the surface is singlesampled, then for any surface
160 * format (compressed or not) the vertical alignment is
163 return isl_surf_get_image_alignment_sa(surf
);
169 get_qpitch(const struct isl_surf
*surf
)
171 switch (surf
->dim_layout
) {
173 unreachable("Bad isl_surf_dim");
174 case ISL_DIM_LAYOUT_GEN4_2D
:
176 if (surf
->dim
== ISL_SURF_DIM_3D
&& surf
->tiling
== ISL_TILING_W
) {
177 /* This is rather annoying and completely undocumented. It
178 * appears that the hardware has a bug (or undocumented feature)
179 * regarding stencil buffers most likely related to the way
180 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
181 * stencil buffer normally, and use texelFetch on it, the z or
182 * array index will get implicitly multiplied by 2 for no obvious
183 * reason. The fix appears to be to divide qpitch by 2 for
186 return isl_surf_get_array_pitch_el_rows(surf
) / 2;
188 return isl_surf_get_array_pitch_el_rows(surf
);
191 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
193 * "This field must be set to an integer multiple of the Surface
194 * Vertical Alignment. For compressed textures (BC*, FXT1,
195 * ETC*, and EAC* Surface Formats), this field is in units of
196 * rows in the uncompressed surface, and must be set to an
197 * integer multiple of the vertical alignment parameter "j"
198 * defined in the Common Surface Formats section."
200 return isl_surf_get_array_pitch_sa_rows(surf
);
202 case ISL_DIM_LAYOUT_GEN9_1D
:
203 /* QPitch is usually expressed as rows of surface elements (where
204 * a surface element is an compression block or a single surface
205 * sample). Skylake 1D is an outlier.
207 * From the Skylake BSpec >> Memory Views >> Common Surface
208 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
210 * Surface QPitch specifies the distance in pixels between array
213 return isl_surf_get_array_pitch_el(surf
);
214 case ISL_DIM_LAYOUT_GEN4_3D
:
215 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
216 * different pitch at each LOD. Also, the QPitch field is ignored for
217 * these surfaces. From the Broadwell PRM documentation for QPitch:
219 * This field specifies the distance in rows between array slices. It
220 * is used only in the following cases:
221 * - Surface Array is enabled OR
222 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
223 * Surface Storage Format set to MSFMT_MSS OR
224 * - Surface Type is SURFTYPE_CUBE
226 * None of the three conditions above can possibly apply to a 3D surface
227 * so it is safe to just set QPitch to 0.
232 #endif /* GEN_GEN >= 8 */
235 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
236 const struct isl_surf_fill_state_info
*restrict info
)
238 struct GENX(RENDER_SURFACE_STATE
) s
= { 0 };
240 s
.SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
);
242 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
)
243 assert(isl_format_supports_rendering(dev
->info
, info
->view
->format
));
244 else if (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
)
245 assert(isl_format_supports_sampling(dev
->info
, info
->view
->format
));
247 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
249 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
250 * format if the Surface Type is SURFTYPE_1D
252 if (info
->surf
->dim
== ISL_SURF_DIM_1D
)
253 assert(!isl_format_is_compressed(info
->view
->format
));
255 s
.SurfaceFormat
= info
->view
->format
;
258 s
.IntegerSurfaceFormat
= isl_format_has_int_channel(s
.SurfaceFormat
);
261 assert(info
->surf
->logical_level0_px
.width
> 0 &&
262 info
->surf
->logical_level0_px
.height
> 0);
264 s
.Width
= info
->surf
->logical_level0_px
.width
- 1;
265 s
.Height
= info
->surf
->logical_level0_px
.height
- 1;
267 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
268 * (Surface Arrays For all surfaces other than separate stencil buffer):
270 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
271 * calculated in the equation above , for every other odd Surface Height
272 * starting from 1 i.e. 1,5,9,13"
274 * Since this Qpitch errata only impacts the sampler, we have to adjust the
275 * input for the rendering surface to achieve the same qpitch. For the
276 * affected heights, we increment the height by 1 for the rendering
279 if (GEN_GEN
== 6 && (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) &&
280 info
->surf
->samples
> 1 &&
281 (info
->surf
->logical_level0_px
.height
% 4) == 1)
284 switch (s
.SurfaceType
) {
287 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
289 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
290 * must be set to zero if this surface is used with sampling engine
293 * This restriction appears to exist only on Ivy Bridge.
295 if (GEN_GEN
== 7 && !GEN_IS_HASWELL
&& !ISL_DEV_IS_BAYTRAIL(dev
) &&
296 (info
->view
->usage
& ISL_SURF_USAGE_TEXTURE_BIT
) &&
297 info
->surf
->samples
> 1)
298 assert(info
->view
->base_array_layer
== 0);
300 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
302 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
304 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
305 * by one for each increase from zero of Minimum Array Element. For
306 * example, if Minimum Array Element is set to 1024 on a 2D surface,
307 * the range of this field is reduced to [0,1023].
309 * In other words, 'Depth' is the number of array layers.
311 s
.Depth
= info
->view
->array_len
- 1;
313 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
315 * For Render Target and Typed Dataport 1D and 2D Surfaces:
316 * This field must be set to the same value as the Depth field.
318 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
319 ISL_SURF_USAGE_STORAGE_BIT
))
320 s
.RenderTargetViewExtent
= s
.Depth
;
323 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
324 /* Same as SURFTYPE_2D, but divided by 6 */
325 s
.Depth
= info
->view
->array_len
/ 6 - 1;
326 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
327 ISL_SURF_USAGE_STORAGE_BIT
))
328 s
.RenderTargetViewExtent
= s
.Depth
;
331 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
333 * If the volume texture is MIP-mapped, this field specifies the
334 * depth of the base MIP level.
336 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
338 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
340 * For Render Target and Typed Dataport 3D Surfaces: This field
341 * indicates the extent of the accessible 'R' coordinates minus 1 on
342 * the LOD currently being rendered to.
344 * The docs specify that this only matters for render targets and
345 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
346 * Depth field has more bits than RenderTargetViewExtent so we can have
347 * textures with more levels than we can render to. In order to prevent
348 * assert-failures in the packing function below, we only set the field
349 * when it's actually going to be used by the hardware.
351 * Similaraly, the MinimumArrayElement field is ignored by all hardware
352 * prior to Sky Lake when texturing and we want it set to 0 anyway.
353 * Since it's already initialized to 0, we can just leave it alone for
356 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
357 ISL_SURF_USAGE_STORAGE_BIT
)) {
358 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
359 s
.RenderTargetViewExtent
= info
->view
->array_len
- 1;
363 unreachable("bad SurfaceType");
367 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
;
370 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
371 /* For render target surfaces, the hardware interprets field
372 * MIPCount/LOD as LOD. The Broadwell PRM says:
374 * MIPCountLOD defines the LOD that will be rendered into.
375 * SurfaceMinLOD is ignored.
377 s
.MIPCountLOD
= info
->view
->base_level
;
380 /* For non render target surfaces, the hardware interprets field
381 * MIPCount/LOD as MIPCount. The range of levels accessible by the
382 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
384 s
.SurfaceMinLOD
= info
->view
->base_level
;
385 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
389 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
390 * Start LOD" to 15 to prevent the hardware from trying to use them.
392 s
.TiledResourceMode
= NONE
;
393 s
.MipTailStartLOD
= 15;
397 const struct isl_extent3d image_align
= get_image_alignment(info
->surf
);
398 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[image_align
.height
];
400 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[image_align
.width
];
404 if (info
->surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
405 /* For gen9 1-D textures, surface pitch is ignored */
408 s
.SurfacePitch
= info
->surf
->row_pitch
- 1;
412 s
.SurfaceQPitch
= get_qpitch(info
->surf
) >> 2;
414 s
.SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
415 ISL_ARRAY_PITCH_SPAN_COMPACT
;
419 s
.TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
];
421 s
.TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
422 s
.TileWalk
= info
->surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
427 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
429 s
.RenderCacheReadWriteMode
= 0;
432 if (info
->view
->usage
& ISL_SURF_USAGE_CUBE_BIT
) {
434 s
.CubeFaceEnablePositiveZ
= 1;
435 s
.CubeFaceEnableNegativeZ
= 1;
436 s
.CubeFaceEnablePositiveY
= 1;
437 s
.CubeFaceEnableNegativeY
= 1;
438 s
.CubeFaceEnablePositiveX
= 1;
439 s
.CubeFaceEnableNegativeX
= 1;
441 s
.CubeFaceEnables
= 0x3f;
446 s
.NumberofMultisamples
= ffs(info
->surf
->samples
) - 1;
448 s
.MultisampledSurfaceStorageFormat
=
449 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
];
453 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
454 s
.ShaderChannelSelectRed
= info
->view
->swizzle
.r
;
455 s
.ShaderChannelSelectGreen
= info
->view
->swizzle
.g
;
456 s
.ShaderChannelSelectBlue
= info
->view
->swizzle
.b
;
457 s
.ShaderChannelSelectAlpha
= info
->view
->swizzle
.a
;
460 s
.SurfaceBaseAddress
= info
->address
;
466 #if GEN_GEN > 4 || GEN_IS_G4X
467 if (info
->x_offset_sa
!= 0 || info
->y_offset_sa
!= 0) {
468 /* There are fairly strict rules about when the offsets can be used.
469 * These are mostly taken from the Sky Lake PRM documentation for
470 * RENDER_SURFACE_STATE.
472 assert(info
->surf
->tiling
!= ISL_TILING_LINEAR
);
473 assert(info
->surf
->dim
== ISL_SURF_DIM_2D
);
474 assert(isl_is_pow2(isl_format_get_layout(info
->view
->format
)->bpb
));
475 assert(info
->surf
->levels
== 1);
476 assert(info
->surf
->logical_level0_px
.array_len
== 1);
477 assert(info
->aux_usage
== ISL_AUX_USAGE_NONE
);
480 /* Broadwell added more rules. */
481 assert(info
->surf
->samples
== 1);
482 if (isl_format_get_layout(info
->view
->format
)->bpb
== 8)
483 assert(info
->x_offset_sa
% 16 == 0);
484 if (isl_format_get_layout(info
->view
->format
)->bpb
== 16)
485 assert(info
->x_offset_sa
% 8 == 0);
489 s
.SurfaceArray
= false;
493 const unsigned x_div
= 4;
494 const unsigned y_div
= GEN_GEN
>= 8 ? 4 : 2;
495 assert(info
->x_offset_sa
% x_div
== 0);
496 assert(info
->y_offset_sa
% y_div
== 0);
497 s
.XOffset
= info
->x_offset_sa
/ x_div
;
498 s
.YOffset
= info
->y_offset_sa
/ y_div
;
500 assert(info
->x_offset_sa
== 0);
501 assert(info
->y_offset_sa
== 0);
505 if (info
->aux_surf
&& info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
506 struct isl_tile_info tile_info
;
507 isl_surf_get_tile_info(dev
, info
->aux_surf
, &tile_info
);
508 uint32_t pitch_in_tiles
=
509 info
->aux_surf
->row_pitch
/ tile_info
.phys_extent_B
.width
;
512 assert(GEN_GEN
>= 9 || info
->aux_usage
!= ISL_AUX_USAGE_CCS_E
);
513 s
.AuxiliarySurfacePitch
= pitch_in_tiles
- 1;
514 /* Auxiliary surfaces in ISL have compressed formats but the hardware
515 * doesn't expect our definition of the compression, it expects qpitch
516 * in units of samples on the main surface.
518 s
.AuxiliarySurfaceQPitch
=
519 isl_surf_get_array_pitch_sa_rows(info
->aux_surf
) >> 2;
520 s
.AuxiliarySurfaceBaseAddress
= info
->aux_address
;
521 s
.AuxiliarySurfaceMode
= isl_to_gen_aux_mode
[info
->aux_usage
];
523 assert(info
->aux_usage
== ISL_AUX_USAGE_MCS
||
524 info
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
525 s
.MCSBaseAddress
= info
->aux_address
,
526 s
.MCSSurfacePitch
= pitch_in_tiles
- 1;
533 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
534 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
536 * This bit must be set for the following surface types: BC2_UNORM
537 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
539 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
540 switch (info
->view
->format
) {
541 case ISL_FORMAT_BC2_UNORM
:
542 case ISL_FORMAT_BC3_UNORM
:
543 case ISL_FORMAT_BC5_UNORM
:
544 case ISL_FORMAT_BC5_SNORM
:
545 case ISL_FORMAT_BC7_UNORM
:
546 s
.SamplerL2BypassModeDisable
= true;
554 if (info
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
556 s
.RedClearColor
= info
->clear_color
.u32
[0];
557 s
.GreenClearColor
= info
->clear_color
.u32
[1];
558 s
.BlueClearColor
= info
->clear_color
.u32
[2];
559 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
561 /* Prior to Sky Lake, we only have one bit for the clear color which
562 * gives us 0 or 1 in whatever the surface's format happens to be.
564 if (isl_format_has_int_channel(info
->view
->format
)) {
565 for (unsigned i
= 0; i
< 4; i
++) {
566 assert(info
->clear_color
.u32
[i
] == 0 ||
567 info
->clear_color
.u32
[i
] == 1);
569 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
570 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
571 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
572 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
574 for (unsigned i
= 0; i
< 4; i
++) {
575 assert(info
->clear_color
.f32
[i
] == 0.0f
||
576 info
->clear_color
.f32
[i
] == 1.0f
);
578 s
.RedClearColor
= info
->clear_color
.f32
[0] != 0.0f
;
579 s
.GreenClearColor
= info
->clear_color
.f32
[1] != 0.0f
;
580 s
.BlueClearColor
= info
->clear_color
.f32
[2] != 0.0f
;
581 s
.AlphaClearColor
= info
->clear_color
.f32
[3] != 0.0f
;
586 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
590 isl_genX(buffer_fill_state_s
)(void *state
,
591 const struct isl_buffer_fill_state_info
*restrict info
)
593 uint32_t num_elements
= info
->size
/ info
->stride
;
596 /* From the IVB PRM, SURFACE_STATE::Height,
598 * For typed buffer and structured buffer surfaces, the number
599 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
600 * surfaces, the number of entries in the buffer is the number of bytes
601 * which can range from 1 to 2^30.
603 if (info
->format
== ISL_FORMAT_RAW
) {
604 assert(num_elements
<= (1ull << 30));
605 assert((num_elements
& 3) == 0);
607 assert(num_elements
<= (1ull << 27));
610 assert(num_elements
<= (1ull << 27));
613 struct GENX(RENDER_SURFACE_STATE
) s
= { 0, };
615 s
.SurfaceType
= SURFTYPE_BUFFER
;
616 s
.SurfaceFormat
= info
->format
;
619 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[4];
621 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[4];
622 s
.SurfaceArray
= false;
627 s
.Height
= ((num_elements
- 1) >> 7) & 0x3fff;
628 s
.Width
= (num_elements
- 1) & 0x7f;
629 s
.Depth
= ((num_elements
- 1) >> 21) & 0x3ff;
631 s
.Height
= ((num_elements
- 1) >> 7) & 0x1fff;
632 s
.Width
= (num_elements
- 1) & 0x7f;
633 s
.Depth
= ((num_elements
- 1) >> 20) & 0x7f;
636 s
.SurfacePitch
= info
->stride
- 1;
639 s
.NumberofMultisamples
= MULTISAMPLECOUNT_1
;
645 s
.TiledSurface
= false;
649 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
651 s
.RenderCacheReadWriteMode
= 0;
654 s
.SurfaceBaseAddress
= info
->address
;
659 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
660 s
.ShaderChannelSelectRed
= SCS_RED
;
661 s
.ShaderChannelSelectGreen
= SCS_GREEN
;
662 s
.ShaderChannelSelectBlue
= SCS_BLUE
;
663 s
.ShaderChannelSelectAlpha
= SCS_ALPHA
;
666 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);