src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50
  51 static const uint8_t isl_to_gen_valign[] = {
  52     [4] = VALIGN4,
  53     [8] = VALIGN8,
  54     [16] = VALIGN16,
  55 };
  56 #else
  57 static const uint8_t isl_to_gen_halign[] = {
  58     [4] = HALIGN_4,
  59     [8] = HALIGN_8,
  60 };
  61
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75    [ISL_TILING_W]       = WMAJOR,
  76 };
  77 #endif
  78
  79 #if GEN_GEN >= 8
  80 static const uint32_t isl_to_gen_multisample_layout[] = {
  81    [ISL_MSAA_LAYOUT_NONE]           = MSS,
  82    [ISL_MSAA_LAYOUT_INTERLEAVED]    = DEPTH_STENCIL,
  83    [ISL_MSAA_LAYOUT_ARRAY]          = MSS,
  84 };
  85 #else
  86 static const uint32_t isl_to_gen_multisample_layout[] = {
  87    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  88    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  89    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  90 };
  91 #endif
  92
  93 static uint8_t
  94 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
  95 {
  96    switch (dim) {
  97    default:
  98       unreachable("bad isl_surf_dim");
  99    case ISL_SURF_DIM_1D:
 100       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 101       return SURFTYPE_1D;
 102    case ISL_SURF_DIM_2D:
 103       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
 104          /* Storage images are always plain 2-D, not cube */
 105          return SURFTYPE_2D;
 106       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 107          return SURFTYPE_CUBE;
 108       } else {
 109          return SURFTYPE_2D;
 110       }
 111    case ISL_SURF_DIM_3D:
 112       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 113       return SURFTYPE_3D;
 114    }
 115 }
 116
 117 /**
 118  * Get the values to pack into RENDER_SUFFACE_STATE.SurfaceHorizontalAlignment
 119  * and SurfaceVerticalAlignment.
 120  */
 121 static void
 122 get_halign_valign(const struct isl_surf *surf,
 123                   uint32_t *halign, uint32_t *valign)
 124 {
 125    if (GEN_GEN >= 9) {
 126       if (isl_tiling_is_std_y(surf->tiling) ||
 127           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 128          /* The hardware ignores the alignment values. Anyway, the surface's
 129           * true alignment is likely outside the enum range of HALIGN* and
 130           * VALIGN*.
 131           */
 132          *halign = 0;
 133          *valign = 0;
 134       } else {
 135          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 136           * of surface elements (not pixels nor samples). For compressed formats,
 137           * a "surface element" is defined as a compression block.  For example,
 138           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 139           * format (ETC2 has a block height of 4), then the vertical alignment is
 140           * 4 compression blocks or, equivalently, 16 pixels.
 141           */
 142          struct isl_extent3d image_align_el
 143             = isl_surf_get_image_alignment_el(surf);
 144
 145          *halign = isl_to_gen_halign[image_align_el.width];
 146          *valign = isl_to_gen_valign[image_align_el.height];
 147       }
 148    } else {
 149       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 150        * units of surface samples.  For example, if SurfaceVerticalAlignment
 151        * is VALIGN_4 and the surface is singlesampled, then for any surface
 152        * format (compressed or not) the vertical alignment is
 153        * 4 pixels.
 154        */
 155       struct isl_extent3d image_align_sa
 156          = isl_surf_get_image_alignment_sa(surf);
 157
 158       *halign = isl_to_gen_halign[image_align_sa.width];
 159       *valign = isl_to_gen_valign[image_align_sa.height];
 160    }
 161 }
 162
 163 #if GEN_GEN >= 8
 164 static uint32_t
 165 get_qpitch(const struct isl_surf *surf)
 166 {
 167    switch (surf->dim) {
 168    default:
 169       unreachable("Bad isl_surf_dim");
 170    case ISL_SURF_DIM_1D:
 171       if (GEN_GEN >= 9) {
 172          /* QPitch is usually expressed as rows of surface elements (where
 173           * a surface element is an compression block or a single surface
 174           * sample). Skylake 1D is an outlier.
 175           *
 176           * From the Skylake BSpec >> Memory Views >> Common Surface
 177           * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 178           *
 179           *    Surface QPitch specifies the distance in pixels between array
 180           *    slices.
 181           */
 182          return isl_surf_get_array_pitch_el(surf);
 183       } else {
 184          return isl_surf_get_array_pitch_el_rows(surf);
 185       }
 186    case ISL_SURF_DIM_2D:
 187    case ISL_SURF_DIM_3D:
 188       if (GEN_GEN >= 9) {
 189          return isl_surf_get_array_pitch_el_rows(surf);
 190       } else {
 191          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 192           *
 193           *    "This field must be set to an integer multiple of the Surface
 194           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 195           *    ETC*, and EAC* Surface Formats), this field is in units of
 196           *    rows in the uncompressed surface, and must be set to an
 197           *    integer multiple of the vertical alignment parameter "j"
 198           *    defined in the Common Surface Formats section."
 199           */
 200          return isl_surf_get_array_pitch_sa_rows(surf);
 201       }
 202    }
 203 }
 204 #endif /* GEN_GEN >= 8 */
 205
 206 void
 207 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 208                             const struct isl_surf_fill_state_info *restrict info)
 209 {
 210    uint32_t halign, valign;
 211    get_halign_valign(info->surf, &halign, &valign);
 212
 213    struct GENX(RENDER_SURFACE_STATE) s = {
 214       .SurfaceType = get_surftype(info->surf->dim, info->view->usage),
 215       .SurfaceArray = info->surf->phys_level0_sa.array_len > 1,
 216       .SurfaceVerticalAlignment = valign,
 217       .SurfaceHorizontalAlignment = halign,
 218
 219 #if GEN_GEN >= 8
 220       .TileMode = isl_to_gen_tiling[info->surf->tiling],
 221 #else
 222       .TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 223       .TileWalk = info->surf->tiling == ISL_TILING_X ? TILEWALK_XMAJOR :
 224                                                        TILEWALK_YMAJOR,
 225 #endif
 226
 227       .VerticalLineStride = 0,
 228       .VerticalLineStrideOffset = 0,
 229
 230 #if (GEN_GEN == 7)
 231       .SurfaceArraySpacing = info->surf->array_pitch_span ==
 232                              ISL_ARRAY_PITCH_SPAN_COMPACT,
 233 #endif
 234
 235 #if GEN_GEN >= 8
 236       .SamplerL2BypassModeDisable = true,
 237 #endif
 238
 239 #if GEN_GEN >= 8
 240       .RenderCacheReadWriteMode = WriteOnlyCache,
 241 #else
 242       .RenderCacheReadWriteMode = 0,
 243 #endif
 244
 245 #if GEN_GEN >= 8
 246       .CubeFaceEnablePositiveZ = 1,
 247       .CubeFaceEnableNegativeZ = 1,
 248       .CubeFaceEnablePositiveY = 1,
 249       .CubeFaceEnableNegativeY = 1,
 250       .CubeFaceEnablePositiveX = 1,
 251       .CubeFaceEnableNegativeX = 1,
 252 #else
 253       .CubeFaceEnables = 0x3f,
 254 #endif
 255
 256 #if GEN_GEN >= 8
 257       .SurfaceQPitch = get_qpitch(info->surf) >> 2,
 258 #endif
 259
 260       .Width = info->surf->logical_level0_px.width - 1,
 261       .Height = info->surf->logical_level0_px.height - 1,
 262       .Depth = 0, /* TEMPLATE */
 263
 264       .RenderTargetViewExtent = 0, /* TEMPLATE */
 265       .MinimumArrayElement = 0, /* TEMPLATE */
 266
 267       .MultisampledSurfaceStorageFormat =
 268          isl_to_gen_multisample_layout[info->surf->msaa_layout],
 269       .NumberofMultisamples = ffs(info->surf->samples) - 1,
 270       .MultisamplePositionPaletteIndex = 0, /* UNUSED */
 271
 272       .XOffset = 0,
 273       .YOffset = 0,
 274
 275       .ResourceMinLOD = 0.0,
 276
 277       .MIPCountLOD = 0, /* TEMPLATE */
 278       .SurfaceMinLOD = 0, /* TEMPLATE */
 279
 280 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 281       .ShaderChannelSelectRed = info->view->channel_select[0],
 282       .ShaderChannelSelectGreen = info->view->channel_select[1],
 283       .ShaderChannelSelectBlue = info->view->channel_select[2],
 284       .ShaderChannelSelectAlpha = info->view->channel_select[3],
 285 #endif
 286
 287       .SurfaceBaseAddress = info->address,
 288       .MOCS = info->mocs,
 289
 290 #if GEN_GEN >= 8
 291       .AuxiliarySurfaceMode = AUX_NONE,
 292 #else
 293       .MCSEnable = false,
 294 #endif
 295    };
 296
 297    if (info->surf->tiling == ISL_TILING_W) {
 298       /* From the Broadwell PRM documentation for this field:
 299        *
 300        *    "If the surface is a stencil buffer (and thus has Tile Mode set
 301        *    to TILEMODE_WMAJOR), the pitch must be set to 2x the value
 302        *    computed based on width, as the stencil buffer is stored with
 303        *    two rows interleaved."
 304        */
 305       s.SurfacePitch = info->surf->row_pitch * 2 - 1;
 306    } else {
 307       s.SurfacePitch = info->surf->row_pitch - 1;
 308    }
 309
 310    if (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT) {
 311       s.SurfaceFormat =
 312          isl_lower_storage_image_format(dev->info, info->view->format);
 313    } else {
 314       s.SurfaceFormat = info->view->format;
 315    }
 316
 317    switch (s.SurfaceType) {
 318    case SURFTYPE_1D:
 319    case SURFTYPE_2D:
 320       s.MinimumArrayElement = info->view->base_array_layer;
 321
 322       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 323        *
 324        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 325        *    by one for each increase from zero of Minimum Array Element. For
 326        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 327        *    the range of this field is reduced to [0,1023].
 328        *
 329        * In other words, 'Depth' is the number of array layers.
 330        */
 331       s.Depth = info->view->array_len - 1;
 332
 333       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 334        *
 335        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 336        *    This field must be set to the same value as the Depth field.
 337        */
 338       s.RenderTargetViewExtent = s.Depth;
 339       break;
 340    case SURFTYPE_CUBE:
 341       s.MinimumArrayElement = info->view->base_array_layer;
 342       /* Same as SURFTYPE_2D, but divided by 6 */
 343       s.Depth = info->view->array_len / 6 - 1;
 344       s.RenderTargetViewExtent = s.Depth;
 345       break;
 346    case SURFTYPE_3D:
 347       s.MinimumArrayElement = info->view->base_array_layer;
 348
 349       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 350        *
 351        *    If the volume texture is MIP-mapped, this field specifies the
 352        *    depth of the base MIP level.
 353        */
 354       s.Depth = info->surf->logical_level0_px.depth - 1;
 355
 356       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 357        *
 358        *    For Render Target and Typed Dataport 3D Surfaces: This field
 359        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 360        *    the LOD currently being rendered to.
 361        */
 362       s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 363                                             info->view->base_level) - 1;
 364       break;
 365    default:
 366       unreachable("bad SurfaceType");
 367    }
 368
 369    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 370       /* For render target surfaces, the hardware interprets field
 371        * MIPCount/LOD as LOD. The Broadwell PRM says:
 372        *
 373        *    MIPCountLOD defines the LOD that will be rendered into.
 374        *    SurfaceMinLOD is ignored.
 375        */
 376       s.MIPCountLOD = info->view->base_level;
 377       s.SurfaceMinLOD = 0;
 378    } else {
 379       /* For non render target surfaces, the hardware interprets field
 380        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 381        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 382        */
 383       s.SurfaceMinLOD = info->view->base_level;
 384       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 385    }
 386
 387 #if GEN_GEN >= 8
 388    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 389     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 390     *
 391     *    This bit must be set for the following surface types: BC2_UNORM
 392     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 393     */
 394    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 395       switch (info->view->format) {
 396       case ISL_FORMAT_BC2_UNORM:
 397       case ISL_FORMAT_BC3_UNORM:
 398       case ISL_FORMAT_BC5_UNORM:
 399       case ISL_FORMAT_BC5_SNORM:
 400       case ISL_FORMAT_BC7_UNORM:
 401          s.SamplerL2BypassModeDisable = true;
 402          break;
 403       default:
 404          break;
 405       }
 406    }
 407 #endif
 408
 409    if (GEN_GEN <= 8) {
 410       /* Prior to Sky Lake, we only have one bit for the clear color which
 411        * gives us 0 or 1 in whatever the surface's format happens to be.
 412        */
 413       if (isl_format_has_int_channel(info->view->format)) {
 414          for (unsigned i = 0; i < 4; i++) {
 415             assert(info->clear_color.u32[i] == 0 ||
 416                    info->clear_color.u32[i] == 1);
 417          }
 418       } else {
 419          for (unsigned i = 0; i < 4; i++) {
 420             assert(info->clear_color.f32[i] == 0.0f ||
 421                    info->clear_color.f32[i] == 1.0f);
 422          }
 423       }
 424       s.RedClearColor = info->clear_color.u32[0] != 0;
 425       s.GreenClearColor = info->clear_color.u32[1] != 0;
 426       s.BlueClearColor = info->clear_color.u32[2] != 0;
 427       s.AlphaClearColor = info->clear_color.u32[3] != 0;
 428    } else {
 429       s.RedClearColor = info->clear_color.u32[0];
 430       s.GreenClearColor = info->clear_color.u32[1];
 431       s.BlueClearColor = info->clear_color.u32[2];
 432       s.AlphaClearColor = info->clear_color.u32[3];
 433    }
 434
 435    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 436 }
 437
 438 void
 439 isl_genX(buffer_fill_state_s)(void *state,
 440                               const struct isl_buffer_fill_state_info *restrict info)
 441 {
 442    uint32_t num_elements = info->size / info->stride;
 443
 444    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 445       .SurfaceType = SURFTYPE_BUFFER,
 446       .SurfaceArray = false,
 447       .SurfaceFormat = info->format,
 448       .SurfaceVerticalAlignment = isl_to_gen_valign[4],
 449       .SurfaceHorizontalAlignment = isl_to_gen_halign[4],
 450       .Height = ((num_elements - 1) >> 7) & 0x3fff,
 451       .Width = (num_elements - 1) & 0x7f,
 452       .Depth = ((num_elements - 1) >> 21) & 0x3f,
 453       .SurfacePitch = info->stride - 1,
 454       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 455
 456 #if (GEN_GEN >= 8)
 457       .TileMode = LINEAR,
 458 #else
 459       .TiledSurface = false,
 460 #endif
 461
 462 #if (GEN_GEN >= 8)
 463       .SamplerL2BypassModeDisable = true,
 464       .RenderCacheReadWriteMode = WriteOnlyCache,
 465 #else
 466       .RenderCacheReadWriteMode = 0,
 467 #endif
 468
 469       .MOCS = info->mocs,
 470
 471 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 472       .ShaderChannelSelectRed = SCS_RED,
 473       .ShaderChannelSelectGreen = SCS_GREEN,
 474       .ShaderChannelSelectBlue = SCS_BLUE,
 475       .ShaderChannelSelectAlpha = SCS_ALPHA,
 476 #endif
 477       .SurfaceBaseAddress = info->address,
 478    };
 479
 480    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
 481 }