src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 static const uint32_t isl_to_gen_multisample_layout[] = {
  82    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  83    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  84    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  85 };
  86
  87 #if GEN_GEN >= 9
  88 static const uint32_t isl_to_gen_aux_mode[] = {
  89    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  90    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  91    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  92    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94 };
  95 #elif GEN_GEN >= 8
  96 static const uint32_t isl_to_gen_aux_mode[] = {
  97    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  98    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  99    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 100    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 101 };
 102 #endif
 103
 104 static uint8_t
 105 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 106 {
 107    switch (dim) {
 108    default:
 109       unreachable("bad isl_surf_dim");
 110    case ISL_SURF_DIM_1D:
 111       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 112       return SURFTYPE_1D;
 113    case ISL_SURF_DIM_2D:
 114       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
 115          /* Storage images are always plain 2-D, not cube */
 116          return SURFTYPE_2D;
 117       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 118          return SURFTYPE_CUBE;
 119       } else {
 120          return SURFTYPE_2D;
 121       }
 122    case ISL_SURF_DIM_3D:
 123       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 124       return SURFTYPE_3D;
 125    }
 126 }
 127
 128 /**
 129  * Get the horizontal and vertical alignment in the units expected by the
 130  * hardware.  Note that this does NOT give you the actual hardware enum values
 131  * but an index into the isl_to_gen_[hv]align arrays above.
 132  */
 133 static struct isl_extent3d
 134 get_image_alignment(const struct isl_surf *surf)
 135 {
 136    if (GEN_GEN >= 9) {
 137       if (isl_tiling_is_std_y(surf->tiling) ||
 138           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 139          /* The hardware ignores the alignment values. Anyway, the surface's
 140           * true alignment is likely outside the enum range of HALIGN* and
 141           * VALIGN*.
 142           */
 143          return isl_extent3d(0, 0, 0);
 144       } else {
 145          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 146           * of surface elements (not pixels nor samples). For compressed formats,
 147           * a "surface element" is defined as a compression block.  For example,
 148           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 149           * format (ETC2 has a block height of 4), then the vertical alignment is
 150           * 4 compression blocks or, equivalently, 16 pixels.
 151           */
 152          return isl_surf_get_image_alignment_el(surf);
 153       }
 154    } else {
 155       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 156        * units of surface samples.  For example, if SurfaceVerticalAlignment
 157        * is VALIGN_4 and the surface is singlesampled, then for any surface
 158        * format (compressed or not) the vertical alignment is
 159        * 4 pixels.
 160        */
 161       return isl_surf_get_image_alignment_sa(surf);
 162    }
 163 }
 164
 165 #if GEN_GEN >= 8
 166 static uint32_t
 167 get_qpitch(const struct isl_surf *surf)
 168 {
 169    switch (surf->dim_layout) {
 170    default:
 171       unreachable("Bad isl_surf_dim");
 172    case ISL_DIM_LAYOUT_GEN4_2D:
 173    case ISL_DIM_LAYOUT_GEN4_3D:
 174       if (GEN_GEN >= 9) {
 175          return isl_surf_get_array_pitch_el_rows(surf);
 176       } else {
 177          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 178           *
 179           *    "This field must be set to an integer multiple of the Surface
 180           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 181           *    ETC*, and EAC* Surface Formats), this field is in units of
 182           *    rows in the uncompressed surface, and must be set to an
 183           *    integer multiple of the vertical alignment parameter "j"
 184           *    defined in the Common Surface Formats section."
 185           */
 186          return isl_surf_get_array_pitch_sa_rows(surf);
 187       }
 188    case ISL_DIM_LAYOUT_GEN9_1D:
 189       /* QPitch is usually expressed as rows of surface elements (where
 190        * a surface element is an compression block or a single surface
 191        * sample). Skylake 1D is an outlier.
 192        *
 193        * From the Skylake BSpec >> Memory Views >> Common Surface
 194        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 195        *
 196        *    Surface QPitch specifies the distance in pixels between array
 197        *    slices.
 198        */
 199       return isl_surf_get_array_pitch_el(surf);
 200    }
 201 }
 202 #endif /* GEN_GEN >= 8 */
 203
 204 void
 205 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 206                             const struct isl_surf_fill_state_info *restrict info)
 207 {
 208    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 209
 210    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 211    s.SurfaceFormat = info->view->format;
 212
 213 #if GEN_IS_HASWELL
 214    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 215 #endif
 216
 217    s.Width = info->surf->logical_level0_px.width - 1;
 218    s.Height = info->surf->logical_level0_px.height - 1;
 219
 220    switch (s.SurfaceType) {
 221    case SURFTYPE_1D:
 222    case SURFTYPE_2D:
 223       s.MinimumArrayElement = info->view->base_array_layer;
 224
 225       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 226        *
 227        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 228        *    by one for each increase from zero of Minimum Array Element. For
 229        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 230        *    the range of this field is reduced to [0,1023].
 231        *
 232        * In other words, 'Depth' is the number of array layers.
 233        */
 234       s.Depth = info->view->array_len - 1;
 235
 236       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 237        *
 238        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 239        *    This field must be set to the same value as the Depth field.
 240        */
 241       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 242                                ISL_SURF_USAGE_STORAGE_BIT))
 243          s.RenderTargetViewExtent = s.Depth;
 244       break;
 245    case SURFTYPE_CUBE:
 246       s.MinimumArrayElement = info->view->base_array_layer;
 247       /* Same as SURFTYPE_2D, but divided by 6 */
 248       s.Depth = info->view->array_len / 6 - 1;
 249       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 250                                ISL_SURF_USAGE_STORAGE_BIT))
 251          s.RenderTargetViewExtent = s.Depth;
 252       break;
 253    case SURFTYPE_3D:
 254       s.MinimumArrayElement = info->view->base_array_layer;
 255
 256       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 257        *
 258        *    If the volume texture is MIP-mapped, this field specifies the
 259        *    depth of the base MIP level.
 260        */
 261       s.Depth = info->surf->logical_level0_px.depth - 1;
 262
 263       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 264        *
 265        *    For Render Target and Typed Dataport 3D Surfaces: This field
 266        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 267        *    the LOD currently being rendered to.
 268        *
 269        * The docs specify that this only matters for render targets and
 270        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 271        * Depth field has more bits than RenderTargetViewExtent so we can have
 272        * textures with more levels than we can render to.  In order to prevent
 273        * assert-failures in the packing function below, we only set the field
 274        * when it's actually going to be used by the hardware.
 275        */
 276       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 277                                ISL_SURF_USAGE_STORAGE_BIT)) {
 278          s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 279                                                info->view->base_level) - 1;
 280       }
 281       break;
 282    default:
 283       unreachable("bad SurfaceType");
 284    }
 285
 286    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 287
 288    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 289       /* For render target surfaces, the hardware interprets field
 290        * MIPCount/LOD as LOD. The Broadwell PRM says:
 291        *
 292        *    MIPCountLOD defines the LOD that will be rendered into.
 293        *    SurfaceMinLOD is ignored.
 294        */
 295       s.MIPCountLOD = info->view->base_level;
 296       s.SurfaceMinLOD = 0;
 297    } else {
 298       /* For non render target surfaces, the hardware interprets field
 299        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 300        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 301        */
 302       s.SurfaceMinLOD = info->view->base_level;
 303       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 304    }
 305
 306 #if GEN_GEN >= 9
 307    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 308     * Start LOD" to 15 to prevent the hardware from trying to use them.
 309     */
 310    s.TiledResourceMode = NONE;
 311    s.MipTailStartLOD = 15;
 312 #endif
 313
 314    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 315    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 316    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 317
 318    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 319       /* For gen9 1-D textures, surface pitch is ignored */
 320       s.SurfacePitch = 0;
 321    } else {
 322       s.SurfacePitch = info->surf->row_pitch - 1;
 323    }
 324
 325 #if GEN_GEN >= 8
 326    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 327 #elif GEN_GEN == 7
 328    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 329                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 330 #endif
 331
 332 #if GEN_GEN >= 8
 333    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 334 #else
 335    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 336    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 337                                                       TILEWALK_XMAJOR,
 338 #endif
 339
 340 #if GEN_GEN >= 8
 341    s.RenderCacheReadWriteMode = WriteOnlyCache;
 342 #else
 343    s.RenderCacheReadWriteMode = 0;
 344 #endif
 345
 346    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 347 #if GEN_GEN >= 8
 348       s.CubeFaceEnablePositiveZ = 1;
 349       s.CubeFaceEnableNegativeZ = 1;
 350       s.CubeFaceEnablePositiveY = 1;
 351       s.CubeFaceEnableNegativeY = 1;
 352       s.CubeFaceEnablePositiveX = 1;
 353       s.CubeFaceEnableNegativeX = 1;
 354 #else
 355       s.CubeFaceEnables = 0x3f;
 356 #endif
 357    }
 358
 359    s.MultisampledSurfaceStorageFormat =
 360       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 361    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 362
 363 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 364    s.ShaderChannelSelectRed = info->view->channel_select[0];
 365    s.ShaderChannelSelectGreen = info->view->channel_select[1];
 366    s.ShaderChannelSelectBlue = info->view->channel_select[2];
 367    s.ShaderChannelSelectAlpha = info->view->channel_select[3];
 368 #endif
 369
 370    s.SurfaceBaseAddress = info->address;
 371    s.MOCS = info->mocs;
 372
 373 #if GEN_GEN >= 7
 374    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 375       struct isl_tile_info tile_info;
 376       isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
 377       uint32_t pitch_in_tiles =
 378          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 379
 380 #if GEN_GEN >= 8
 381       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 382       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 383       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 384        * doesn't expect our definition of the compression, it expects qpitch
 385        * in units of samples on the main surface.
 386        */
 387       s.AuxiliarySurfaceQPitch =
 388          isl_surf_get_array_pitch_sa_rows(info->aux_surf);
 389       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 390       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 391 #else
 392       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 393              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 394       s.MCSBaseAddress = info->aux_address,
 395       s.MCSSurfacePitch = pitch_in_tiles - 1;
 396       s.MCSEnable = true;
 397 #endif
 398    }
 399 #endif
 400
 401 #if GEN_GEN >= 8
 402    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 403     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 404     *
 405     *    This bit must be set for the following surface types: BC2_UNORM
 406     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 407     */
 408    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 409       switch (info->view->format) {
 410       case ISL_FORMAT_BC2_UNORM:
 411       case ISL_FORMAT_BC3_UNORM:
 412       case ISL_FORMAT_BC5_UNORM:
 413       case ISL_FORMAT_BC5_SNORM:
 414       case ISL_FORMAT_BC7_UNORM:
 415          s.SamplerL2BypassModeDisable = true;
 416          break;
 417       default:
 418          break;
 419       }
 420    }
 421 #endif
 422
 423 #if GEN_GEN >= 9
 424    s.RedClearColor = info->clear_color.u32[0];
 425    s.GreenClearColor = info->clear_color.u32[1];
 426    s.BlueClearColor = info->clear_color.u32[2];
 427    s.AlphaClearColor = info->clear_color.u32[3];
 428 #elif GEN_GEN >= 7
 429    /* Prior to Sky Lake, we only have one bit for the clear color which
 430     * gives us 0 or 1 in whatever the surface's format happens to be.
 431     */
 432    if (isl_format_has_int_channel(info->view->format)) {
 433       for (unsigned i = 0; i < 4; i++) {
 434          assert(info->clear_color.u32[i] == 0 ||
 435                 info->clear_color.u32[i] == 1);
 436       }
 437       s.RedClearColor = info->clear_color.u32[0] != 0;
 438       s.GreenClearColor = info->clear_color.u32[1] != 0;
 439       s.BlueClearColor = info->clear_color.u32[2] != 0;
 440       s.AlphaClearColor = info->clear_color.u32[3] != 0;
 441    } else {
 442       for (unsigned i = 0; i < 4; i++) {
 443          assert(info->clear_color.f32[i] == 0.0f ||
 444                 info->clear_color.f32[i] == 1.0f);
 445       }
 446       s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 447       s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 448       s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 449       s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 450    }
 451 #endif
 452
 453    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 454 }
 455
 456 void
 457 isl_genX(buffer_fill_state_s)(void *state,
 458                               const struct isl_buffer_fill_state_info *restrict info)
 459 {
 460    uint32_t num_elements = info->size / info->stride;
 461
 462    if (GEN_GEN >= 7) {
 463       if (info->format == ISL_FORMAT_RAW) {
 464          assert(num_elements <= (1ull << 31));
 465          assert((num_elements & 3) == 0);
 466       } else {
 467          assert(num_elements <= (1ull << 27));
 468       }
 469    } else {
 470       assert(num_elements <= (1ull << 27));
 471    }
 472
 473    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 474
 475    s.SurfaceType = SURFTYPE_BUFFER;
 476    s.SurfaceArray = false;
 477    s.SurfaceFormat = info->format;
 478    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 479    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 480    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 481    s.Width = (num_elements - 1) & 0x7f;
 482    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 483    s.SurfacePitch = info->stride - 1;
 484    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 485
 486 #if (GEN_GEN >= 8)
 487    s.TileMode = LINEAR;
 488 #else
 489    s.TiledSurface = false;
 490 #endif
 491
 492 #if (GEN_GEN >= 8)
 493    s.RenderCacheReadWriteMode = WriteOnlyCache;
 494 #else
 495    s.RenderCacheReadWriteMode = 0;
 496 #endif
 497
 498    s.SurfaceBaseAddress = info->address;
 499    s.MOCS = info->mocs;
 500
 501 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 502    s.ShaderChannelSelectRed = SCS_RED;
 503    s.ShaderChannelSelectGreen = SCS_GREEN;
 504    s.ShaderChannelSelectBlue = SCS_BLUE;
 505    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 506 #endif
 507
 508    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 509 }