intel/genxml,isl: Add gen12 render surface state changes
[mesa.git] / src / intel / isl / isl_surface_state.c
1 /*
2 * Copyright 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <stdint.h>
25
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
28
29 static uint64_t
30 __gen_combine_address(__attribute__((unused)) void *data,
31 __attribute__((unused)) void *loc, uint64_t addr,
32 uint32_t delta)
33 {
34 return addr + delta;
35 }
36
37 #include "genxml/gen_macros.h"
38 #include "genxml/genX_pack.h"
39
40 #include "isl_priv.h"
41
42 #if GEN_GEN >= 8
43 static const uint8_t isl_to_gen_halign[] = {
44 [4] = HALIGN4,
45 [8] = HALIGN8,
46 [16] = HALIGN16,
47 };
48 #elif GEN_GEN >= 7
49 static const uint8_t isl_to_gen_halign[] = {
50 [4] = HALIGN_4,
51 [8] = HALIGN_8,
52 };
53 #endif
54
55 #if GEN_GEN >= 8
56 static const uint8_t isl_to_gen_valign[] = {
57 [4] = VALIGN4,
58 [8] = VALIGN8,
59 [16] = VALIGN16,
60 };
61 #elif GEN_GEN >= 6
62 static const uint8_t isl_to_gen_valign[] = {
63 [2] = VALIGN_2,
64 [4] = VALIGN_4,
65 };
66 #endif
67
68 #if GEN_GEN >= 8
69 static const uint8_t isl_to_gen_tiling[] = {
70 [ISL_TILING_LINEAR] = LINEAR,
71 [ISL_TILING_X] = XMAJOR,
72 [ISL_TILING_Y0] = YMAJOR,
73 [ISL_TILING_Yf] = YMAJOR,
74 [ISL_TILING_Ys] = YMAJOR,
75 [ISL_TILING_W] = WMAJOR,
76 };
77 #endif
78
79 #if GEN_GEN >= 7
80 static const uint32_t isl_to_gen_multisample_layout[] = {
81 [ISL_MSAA_LAYOUT_NONE] = MSFMT_MSS,
82 [ISL_MSAA_LAYOUT_INTERLEAVED] = MSFMT_DEPTH_STENCIL,
83 [ISL_MSAA_LAYOUT_ARRAY] = MSFMT_MSS,
84 };
85 #endif
86
87 #if GEN_GEN >= 12
88 static const uint32_t isl_to_gen_aux_mode[] = {
89 [ISL_AUX_USAGE_NONE] = AUX_NONE,
90 [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
91 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
92 };
93 #elif GEN_GEN >= 9
94 static const uint32_t isl_to_gen_aux_mode[] = {
95 [ISL_AUX_USAGE_NONE] = AUX_NONE,
96 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
97 [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
98 [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
99 [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
100 };
101 #elif GEN_GEN >= 8
102 static const uint32_t isl_to_gen_aux_mode[] = {
103 [ISL_AUX_USAGE_NONE] = AUX_NONE,
104 [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
105 [ISL_AUX_USAGE_MCS] = AUX_MCS,
106 [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
107 };
108 #endif
109
110 static uint8_t
111 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
112 {
113 switch (dim) {
114 default:
115 unreachable("bad isl_surf_dim");
116 case ISL_SURF_DIM_1D:
117 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
118 return SURFTYPE_1D;
119 case ISL_SURF_DIM_2D:
120 if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
121 (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
122 /* We need SURFTYPE_CUBE to make cube sampling work */
123 return SURFTYPE_CUBE;
124 } else {
125 /* Everything else (render and storage) treat cubes as plain
126 * 2D array textures
127 */
128 return SURFTYPE_2D;
129 }
130 case ISL_SURF_DIM_3D:
131 assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
132 return SURFTYPE_3D;
133 }
134 }
135
136 /**
137 * Get the horizontal and vertical alignment in the units expected by the
138 * hardware. Note that this does NOT give you the actual hardware enum values
139 * but an index into the isl_to_gen_[hv]align arrays above.
140 */
141 UNUSED static struct isl_extent3d
142 get_image_alignment(const struct isl_surf *surf)
143 {
144 if (GEN_GEN >= 9) {
145 if (isl_tiling_is_std_y(surf->tiling) ||
146 surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
147 /* The hardware ignores the alignment values. Anyway, the surface's
148 * true alignment is likely outside the enum range of HALIGN* and
149 * VALIGN*.
150 */
151 return isl_extent3d(4, 4, 1);
152 } else {
153 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
154 * of surface elements (not pixels nor samples). For compressed formats,
155 * a "surface element" is defined as a compression block. For example,
156 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
157 * format (ETC2 has a block height of 4), then the vertical alignment is
158 * 4 compression blocks or, equivalently, 16 pixels.
159 */
160 return isl_surf_get_image_alignment_el(surf);
161 }
162 } else {
163 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
164 * units of surface samples. For example, if SurfaceVerticalAlignment
165 * is VALIGN_4 and the surface is singlesampled, then for any surface
166 * format (compressed or not) the vertical alignment is
167 * 4 pixels.
168 */
169 return isl_surf_get_image_alignment_sa(surf);
170 }
171 }
172
173 #if GEN_GEN >= 8
174 static uint32_t
175 get_qpitch(const struct isl_surf *surf)
176 {
177 switch (surf->dim_layout) {
178 default:
179 unreachable("Bad isl_surf_dim");
180 case ISL_DIM_LAYOUT_GEN4_2D:
181 if (GEN_GEN >= 9) {
182 if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
183 /* This is rather annoying and completely undocumented. It
184 * appears that the hardware has a bug (or undocumented feature)
185 * regarding stencil buffers most likely related to the way
186 * W-tiling is handled as modified Y-tiling. If you bind a 3-D
187 * stencil buffer normally, and use texelFetch on it, the z or
188 * array index will get implicitly multiplied by 2 for no obvious
189 * reason. The fix appears to be to divide qpitch by 2 for
190 * W-tiled surfaces.
191 */
192 return isl_surf_get_array_pitch_el_rows(surf) / 2;
193 } else {
194 return isl_surf_get_array_pitch_el_rows(surf);
195 }
196 } else {
197 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
198 *
199 * "This field must be set to an integer multiple of the Surface
200 * Vertical Alignment. For compressed textures (BC*, FXT1,
201 * ETC*, and EAC* Surface Formats), this field is in units of
202 * rows in the uncompressed surface, and must be set to an
203 * integer multiple of the vertical alignment parameter "j"
204 * defined in the Common Surface Formats section."
205 */
206 return isl_surf_get_array_pitch_sa_rows(surf);
207 }
208 case ISL_DIM_LAYOUT_GEN9_1D:
209 /* QPitch is usually expressed as rows of surface elements (where
210 * a surface element is an compression block or a single surface
211 * sample). Skylake 1D is an outlier.
212 *
213 * From the Skylake BSpec >> Memory Views >> Common Surface
214 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
215 *
216 * Surface QPitch specifies the distance in pixels between array
217 * slices.
218 */
219 return isl_surf_get_array_pitch_el(surf);
220 case ISL_DIM_LAYOUT_GEN4_3D:
221 /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
222 * different pitch at each LOD. Also, the QPitch field is ignored for
223 * these surfaces. From the Broadwell PRM documentation for QPitch:
224 *
225 * This field specifies the distance in rows between array slices. It
226 * is used only in the following cases:
227 * - Surface Array is enabled OR
228 * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
229 * Surface Storage Format set to MSFMT_MSS OR
230 * - Surface Type is SURFTYPE_CUBE
231 *
232 * None of the three conditions above can possibly apply to a 3D surface
233 * so it is safe to just set QPitch to 0.
234 */
235 return 0;
236 }
237 }
238 #endif /* GEN_GEN >= 8 */
239
240 void
241 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
242 const struct isl_surf_fill_state_info *restrict info)
243 {
244 struct GENX(RENDER_SURFACE_STATE) s = { 0 };
245
246 s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
247
248 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
249 assert(isl_format_supports_rendering(dev->info, info->view->format));
250 else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
251 assert(isl_format_supports_sampling(dev->info, info->view->format));
252
253 /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
254 *
255 * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
256 * format if the Surface Type is SURFTYPE_1D
257 */
258 if (info->surf->dim == ISL_SURF_DIM_1D)
259 assert(!isl_format_is_compressed(info->view->format));
260
261 if (isl_format_is_compressed(info->surf->format)) {
262 /* You're not allowed to make a view of a compressed format with any
263 * format other than the surface format. None of the userspace APIs
264 * allow for this directly and doing so would mess up a number of
265 * surface parameters such as Width, Height, and alignments. Ideally,
266 * we'd like to assert that the two formats match. However, we have an
267 * S3TC workaround that requires us to do reinterpretation. So assert
268 * that they're at least the same bpb and block size.
269 */
270 ASSERTED const struct isl_format_layout *surf_fmtl =
271 isl_format_get_layout(info->surf->format);
272 ASSERTED const struct isl_format_layout *view_fmtl =
273 isl_format_get_layout(info->surf->format);
274 assert(surf_fmtl->bpb == view_fmtl->bpb);
275 assert(surf_fmtl->bw == view_fmtl->bw);
276 assert(surf_fmtl->bh == view_fmtl->bh);
277 }
278
279 s.SurfaceFormat = info->view->format;
280
281 #if GEN_GEN <= 5
282 s.ColorBufferComponentWriteDisables = info->write_disables;
283 #else
284 assert(info->write_disables == 0);
285 #endif
286
287 #if GEN_IS_HASWELL
288 s.IntegerSurfaceFormat =
289 isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
290 #endif
291
292 assert(info->surf->logical_level0_px.width > 0 &&
293 info->surf->logical_level0_px.height > 0);
294
295 s.Width = info->surf->logical_level0_px.width - 1;
296 s.Height = info->surf->logical_level0_px.height - 1;
297
298 /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
299 * (Surface Arrays For all surfaces other than separate stencil buffer):
300 *
301 * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
302 * calculated in the equation above , for every other odd Surface Height
303 * starting from 1 i.e. 1,5,9,13"
304 *
305 * Since this Qpitch errata only impacts the sampler, we have to adjust the
306 * input for the rendering surface to achieve the same qpitch. For the
307 * affected heights, we increment the height by 1 for the rendering
308 * surface.
309 */
310 if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
311 info->surf->samples > 1 &&
312 (info->surf->logical_level0_px.height % 4) == 1)
313 s.Height++;
314
315 switch (s.SurfaceType) {
316 case SURFTYPE_1D:
317 case SURFTYPE_2D:
318 /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
319 *
320 * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
321 * must be set to zero if this surface is used with sampling engine
322 * messages."
323 *
324 * This restriction appears to exist only on Ivy Bridge.
325 */
326 if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
327 (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
328 info->surf->samples > 1)
329 assert(info->view->base_array_layer == 0);
330
331 s.MinimumArrayElement = info->view->base_array_layer;
332
333 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
334 *
335 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
336 * by one for each increase from zero of Minimum Array Element. For
337 * example, if Minimum Array Element is set to 1024 on a 2D surface,
338 * the range of this field is reduced to [0,1023].
339 *
340 * In other words, 'Depth' is the number of array layers.
341 */
342 s.Depth = info->view->array_len - 1;
343
344 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
345 *
346 * For Render Target and Typed Dataport 1D and 2D Surfaces:
347 * This field must be set to the same value as the Depth field.
348 */
349 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
350 ISL_SURF_USAGE_STORAGE_BIT))
351 s.RenderTargetViewExtent = s.Depth;
352 break;
353 case SURFTYPE_CUBE:
354 s.MinimumArrayElement = info->view->base_array_layer;
355 /* Same as SURFTYPE_2D, but divided by 6 */
356 s.Depth = info->view->array_len / 6 - 1;
357 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
358 ISL_SURF_USAGE_STORAGE_BIT))
359 s.RenderTargetViewExtent = s.Depth;
360 break;
361 case SURFTYPE_3D:
362 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
363 *
364 * If the volume texture is MIP-mapped, this field specifies the
365 * depth of the base MIP level.
366 */
367 s.Depth = info->surf->logical_level0_px.depth - 1;
368
369 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
370 *
371 * For Render Target and Typed Dataport 3D Surfaces: This field
372 * indicates the extent of the accessible 'R' coordinates minus 1 on
373 * the LOD currently being rendered to.
374 *
375 * The docs specify that this only matters for render targets and
376 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
377 * Depth field has more bits than RenderTargetViewExtent so we can have
378 * textures with more levels than we can render to. In order to prevent
379 * assert-failures in the packing function below, we only set the field
380 * when it's actually going to be used by the hardware.
381 *
382 * Similaraly, the MinimumArrayElement field is ignored by all hardware
383 * prior to Sky Lake when texturing and we want it set to 0 anyway.
384 * Since it's already initialized to 0, we can just leave it alone for
385 * texture surfaces.
386 */
387 if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
388 ISL_SURF_USAGE_STORAGE_BIT)) {
389 s.MinimumArrayElement = info->view->base_array_layer;
390 s.RenderTargetViewExtent = info->view->array_len - 1;
391 }
392 break;
393 default:
394 unreachable("bad SurfaceType");
395 }
396
397 #if GEN_GEN >= 7
398 s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
399 #endif
400
401 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
402 /* For render target surfaces, the hardware interprets field
403 * MIPCount/LOD as LOD. The Broadwell PRM says:
404 *
405 * MIPCountLOD defines the LOD that will be rendered into.
406 * SurfaceMinLOD is ignored.
407 */
408 s.MIPCountLOD = info->view->base_level;
409 s.SurfaceMinLOD = 0;
410 } else {
411 /* For non render target surfaces, the hardware interprets field
412 * MIPCount/LOD as MIPCount. The range of levels accessible by the
413 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
414 */
415 s.SurfaceMinLOD = info->view->base_level;
416 s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
417 }
418
419 #if GEN_GEN >= 9
420 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
421 * Start LOD" to 15 to prevent the hardware from trying to use them.
422 */
423 s.TiledResourceMode = NONE;
424 s.MipTailStartLOD = 15;
425 #endif
426
427 #if GEN_GEN >= 6
428 const struct isl_extent3d image_align = get_image_alignment(info->surf);
429 s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
430 #if GEN_GEN >= 7
431 s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
432 #endif
433 #endif
434
435 if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
436 /* For gen9 1-D textures, surface pitch is ignored */
437 s.SurfacePitch = 0;
438 } else {
439 s.SurfacePitch = info->surf->row_pitch_B - 1;
440 }
441
442 #if GEN_GEN >= 8
443 s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
444 #elif GEN_GEN == 7
445 s.SurfaceArraySpacing = info->surf->array_pitch_span ==
446 ISL_ARRAY_PITCH_SPAN_COMPACT;
447 #endif
448
449 #if GEN_GEN >= 8
450 s.TileMode = isl_to_gen_tiling[info->surf->tiling];
451 #else
452 s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
453 s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
454 TILEWALK_XMAJOR,
455 #endif
456
457 #if GEN_GEN >= 8
458 s.RenderCacheReadWriteMode = WriteOnlyCache;
459 #else
460 s.RenderCacheReadWriteMode = 0;
461 #endif
462
463 #if GEN_GEN >= 11
464 /* We've seen dEQP failures when enabling this bit with UINT formats,
465 * which particularly affects blorp_copy() operations. It shouldn't
466 * have any effect on UINT textures anyway, so disable it for them.
467 */
468 s.EnableUnormPathInColorPipe =
469 !isl_format_has_int_channel(info->view->format);
470 #endif
471
472 s.CubeFaceEnablePositiveZ = 1;
473 s.CubeFaceEnableNegativeZ = 1;
474 s.CubeFaceEnablePositiveY = 1;
475 s.CubeFaceEnableNegativeY = 1;
476 s.CubeFaceEnablePositiveX = 1;
477 s.CubeFaceEnableNegativeX = 1;
478
479 #if GEN_GEN >= 6
480 s.NumberofMultisamples = ffs(info->surf->samples) - 1;
481 #if GEN_GEN >= 7
482 s.MultisampledSurfaceStorageFormat =
483 isl_to_gen_multisample_layout[info->surf->msaa_layout];
484 #endif
485 #endif
486
487 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
488 if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
489 assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
490
491 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
492 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
493 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
494 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
495 #else
496 assert(isl_swizzle_is_identity(info->view->swizzle));
497 #endif
498
499 s.SurfaceBaseAddress = info->address;
500
501 #if GEN_GEN >= 6
502 s.MOCS = info->mocs;
503 #endif
504
505 #if GEN_GEN > 4 || GEN_IS_G4X
506 if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
507 /* There are fairly strict rules about when the offsets can be used.
508 * These are mostly taken from the Sky Lake PRM documentation for
509 * RENDER_SURFACE_STATE.
510 */
511 assert(info->surf->tiling != ISL_TILING_LINEAR);
512 assert(info->surf->dim == ISL_SURF_DIM_2D);
513 assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
514 assert(info->surf->levels == 1);
515 assert(info->surf->logical_level0_px.array_len == 1);
516 assert(info->aux_usage == ISL_AUX_USAGE_NONE);
517
518 if (GEN_GEN >= 8) {
519 /* Broadwell added more rules. */
520 assert(info->surf->samples == 1);
521 if (isl_format_get_layout(info->view->format)->bpb == 8)
522 assert(info->x_offset_sa % 16 == 0);
523 if (isl_format_get_layout(info->view->format)->bpb == 16)
524 assert(info->x_offset_sa % 8 == 0);
525 }
526
527 #if GEN_GEN >= 7
528 s.SurfaceArray = false;
529 #endif
530 }
531
532 const unsigned x_div = 4;
533 const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
534 assert(info->x_offset_sa % x_div == 0);
535 assert(info->y_offset_sa % y_div == 0);
536 s.XOffset = info->x_offset_sa / x_div;
537 s.YOffset = info->y_offset_sa / y_div;
538 #else
539 assert(info->x_offset_sa == 0);
540 assert(info->y_offset_sa == 0);
541 #endif
542
543 #if GEN_GEN >= 7
544 if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
545 /* The docs don't appear to say anything whatsoever about compression
546 * and the data port. Testing seems to indicate that the data port
547 * completely ignores the AuxiliarySurfaceMode field.
548 */
549 assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
550
551 struct isl_tile_info tile_info;
552 isl_surf_get_tile_info(info->aux_surf, &tile_info);
553 uint32_t pitch_in_tiles =
554 info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
555
556 s.AuxiliarySurfaceBaseAddress = info->aux_address;
557 s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
558
559 #if GEN_GEN >= 8
560 assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
561 /* Auxiliary surfaces in ISL have compressed formats but the hardware
562 * doesn't expect our definition of the compression, it expects qpitch
563 * in units of samples on the main surface.
564 */
565 s.AuxiliarySurfaceQPitch =
566 isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
567
568 if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
569 /* The number of samples must be 1 */
570 assert(info->surf->samples == 1);
571
572 /* The dimension must not be 3D */
573 assert(info->surf->dim != ISL_SURF_DIM_3D);
574
575 /* The format must be one of the following: */
576 switch (info->view->format) {
577 case ISL_FORMAT_R32_FLOAT:
578 case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
579 case ISL_FORMAT_R16_UNORM:
580 break;
581 default:
582 assert(!"Incompatible HiZ Sampling format");
583 break;
584 }
585 }
586
587 s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
588 #else
589 assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
590 info->aux_usage == ISL_AUX_USAGE_CCS_D);
591 s.MCSEnable = true;
592 #endif
593 }
594 #endif
595
596 #if GEN_GEN >= 8 && GEN_GEN < 11
597 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
598 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
599 *
600 * This bit must be set for the following surface types: BC2_UNORM
601 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
602 */
603 if (GEN_GEN >= 9 || dev->info->is_cherryview) {
604 switch (info->view->format) {
605 case ISL_FORMAT_BC2_UNORM:
606 case ISL_FORMAT_BC3_UNORM:
607 case ISL_FORMAT_BC5_UNORM:
608 case ISL_FORMAT_BC5_SNORM:
609 case ISL_FORMAT_BC7_UNORM:
610 s.SamplerL2BypassModeDisable = true;
611 break;
612 default:
613 /* From the SKL PRM, Programming Note under Sampler Output Channel
614 * Mapping:
615 *
616 * If a surface has an associated HiZ Auxilliary surface, the
617 * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
618 * must be set.
619 */
620 if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
621 s.SamplerL2BypassModeDisable = true;
622 break;
623 }
624 }
625 #endif
626
627 if (info->aux_usage != ISL_AUX_USAGE_NONE) {
628 if (info->use_clear_address) {
629 #if GEN_GEN >= 10
630 s.ClearValueAddressEnable = true;
631 s.ClearValueAddress = info->clear_address;
632 #else
633 unreachable("Gen9 and earlier do not support indirect clear colors");
634 #endif
635 }
636
637 #if GEN_GEN == 11
638 /*
639 * From BXML > GT > Shared Functions > vol5c Shared Functions >
640 * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
641 *
642 * Project: Gen11
643 *
644 * "Enables Pixel backend hw to convert clear values into native format
645 * and write back to clear address, so that display and sampler can use
646 * the converted value for resolving fast cleared RTs."
647 *
648 * Summary:
649 * Clear color conversion must be enabled if the clear color is stored
650 * indirectly and fast color clears are enabled.
651 */
652 if (info->use_clear_address) {
653 s.ClearColorConversionEnable = true;
654 }
655 #endif
656
657 #if GEN_GEN >= 12
658 assert(info->use_clear_address);
659 #elif GEN_GEN >= 9
660 if (!info->use_clear_address) {
661 s.RedClearColor = info->clear_color.u32[0];
662 s.GreenClearColor = info->clear_color.u32[1];
663 s.BlueClearColor = info->clear_color.u32[2];
664 s.AlphaClearColor = info->clear_color.u32[3];
665 }
666 #elif GEN_GEN >= 7
667 /* Prior to Sky Lake, we only have one bit for the clear color which
668 * gives us 0 or 1 in whatever the surface's format happens to be.
669 */
670 if (isl_format_has_int_channel(info->view->format)) {
671 for (unsigned i = 0; i < 4; i++) {
672 assert(info->clear_color.u32[i] == 0 ||
673 info->clear_color.u32[i] == 1);
674 }
675 s.RedClearColor = info->clear_color.u32[0] != 0;
676 s.GreenClearColor = info->clear_color.u32[1] != 0;
677 s.BlueClearColor = info->clear_color.u32[2] != 0;
678 s.AlphaClearColor = info->clear_color.u32[3] != 0;
679 } else {
680 for (unsigned i = 0; i < 4; i++) {
681 assert(info->clear_color.f32[i] == 0.0f ||
682 info->clear_color.f32[i] == 1.0f);
683 }
684 s.RedClearColor = info->clear_color.f32[0] != 0.0f;
685 s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
686 s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
687 s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
688 }
689 #endif
690 }
691
692 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
693 }
694
695 void
696 isl_genX(buffer_fill_state_s)(void *state,
697 const struct isl_buffer_fill_state_info *restrict info)
698 {
699 uint64_t buffer_size = info->size_B;
700
701 /* Uniform and Storage buffers need to have surface size not less that the
702 * aligned 32-bit size of the buffer. To calculate the array lenght on
703 * unsized arrays in StorageBuffer the last 2 bits store the padding size
704 * added to the surface, so we can calculate latter the original buffer
705 * size to know the number of elements.
706 *
707 * surface_size = isl_align(buffer_size, 4) +
708 * (isl_align(buffer_size) - buffer_size)
709 *
710 * buffer_size = (surface_size & ~3) - (surface_size & 3)
711 */
712 if (info->format == ISL_FORMAT_RAW ||
713 info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
714 assert(info->stride_B == 1);
715 uint64_t aligned_size = isl_align(buffer_size, 4);
716 buffer_size = aligned_size + (aligned_size - buffer_size);
717 }
718
719 uint32_t num_elements = buffer_size / info->stride_B;
720
721 if (GEN_GEN >= 7) {
722 /* From the IVB PRM, SURFACE_STATE::Height,
723 *
724 * For typed buffer and structured buffer surfaces, the number
725 * of entries in the buffer ranges from 1 to 2^27. For raw buffer
726 * surfaces, the number of entries in the buffer is the number of bytes
727 * which can range from 1 to 2^30.
728 */
729 if (info->format == ISL_FORMAT_RAW) {
730 assert(num_elements <= (1ull << 30));
731 assert(num_elements > 0);
732 } else {
733 assert(num_elements <= (1ull << 27));
734 }
735 } else {
736 assert(num_elements <= (1ull << 27));
737 }
738
739 struct GENX(RENDER_SURFACE_STATE) s = { 0, };
740
741 s.SurfaceType = SURFTYPE_BUFFER;
742 s.SurfaceFormat = info->format;
743
744 #if GEN_GEN >= 6
745 s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
746 #if GEN_GEN >= 7
747 s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
748 s.SurfaceArray = false;
749 #endif
750 #endif
751
752 #if GEN_GEN >= 7
753 s.Height = ((num_elements - 1) >> 7) & 0x3fff;
754 s.Width = (num_elements - 1) & 0x7f;
755 s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
756 #else
757 s.Height = ((num_elements - 1) >> 7) & 0x1fff;
758 s.Width = (num_elements - 1) & 0x7f;
759 s.Depth = ((num_elements - 1) >> 20) & 0x7f;
760 #endif
761
762 s.SurfacePitch = info->stride_B - 1;
763
764 #if GEN_GEN >= 6
765 s.NumberofMultisamples = MULTISAMPLECOUNT_1;
766 #endif
767
768 #if (GEN_GEN >= 8)
769 s.TileMode = LINEAR;
770 #else
771 s.TiledSurface = false;
772 #endif
773
774 #if (GEN_GEN >= 8)
775 s.RenderCacheReadWriteMode = WriteOnlyCache;
776 #else
777 s.RenderCacheReadWriteMode = 0;
778 #endif
779
780 s.SurfaceBaseAddress = info->address;
781 #if GEN_GEN >= 6
782 s.MOCS = info->mocs;
783 #endif
784
785 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
786 s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
787 s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
788 s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
789 s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
790 #endif
791
792 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
793 }
794
795 void
796 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
797 {
798 struct GENX(RENDER_SURFACE_STATE) s = {
799 .SurfaceType = SURFTYPE_NULL,
800 /* We previously had this format set to B8G8R8A8_UNORM but ran into
801 * hangs on IVB. R32_UINT seems to work for everybody.
802 *
803 * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
804 */
805 .SurfaceFormat = ISL_FORMAT_R32_UINT,
806 #if GEN_GEN >= 7
807 .SurfaceArray = size.depth > 1,
808 #endif
809 #if GEN_GEN >= 8
810 .TileMode = YMAJOR,
811 #else
812 .TiledSurface = true,
813 .TileWalk = TILEWALK_YMAJOR,
814 #endif
815 #if GEN_GEN == 7
816 /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
817 * Functions"
818 *
819 * RENDER_SURFACE_STATE::Surface Vertical Alignment
820 *
821 * "This field must be set to VALIGN_4 for all tiled Y Render Target
822 * surfaces."
823 *
824 * Affect IVB, HSW.
825 */
826 .SurfaceVerticalAlignment = VALIGN_4,
827 #endif
828 .Width = size.width - 1,
829 .Height = size.height - 1,
830 .Depth = size.depth - 1,
831 .RenderTargetViewExtent = size.depth - 1,
832 #if GEN_GEN <= 5
833 .ColorBufferComponentWriteDisables = 0xf,
834 #endif
835 };
836 GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
837 }