src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static uint64_t
  30 __gen_combine_address(__attribute__((unused)) void *data,
  31                       __attribute__((unused)) void *loc, uint64_t addr,
  32                       uint32_t delta)
  33 {
  34    return addr + delta;
  35 }
  36
  37 #include "genxml/gen_macros.h"
  38 #include "genxml/genX_pack.h"
  39
  40 #include "isl_priv.h"
  41
  42 #if GEN_GEN >= 8
  43 static const uint8_t isl_to_gen_halign[] = {
  44     [4] = HALIGN4,
  45     [8] = HALIGN8,
  46     [16] = HALIGN16,
  47 };
  48 #elif GEN_GEN >= 7
  49 static const uint8_t isl_to_gen_halign[] = {
  50     [4] = HALIGN_4,
  51     [8] = HALIGN_8,
  52 };
  53 #endif
  54
  55 #if GEN_GEN >= 8
  56 static const uint8_t isl_to_gen_valign[] = {
  57     [4] = VALIGN4,
  58     [8] = VALIGN8,
  59     [16] = VALIGN16,
  60 };
  61 #elif GEN_GEN >= 6
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75 #if GEN_GEN <= 11
  76    [ISL_TILING_W]       = WMAJOR,
  77 #endif
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 12
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
  93    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  94    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
  95 };
  96 #elif GEN_GEN >= 9
  97 static const uint32_t isl_to_gen_aux_mode[] = {
  98    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  99    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 100    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
 101    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
 102    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
 103 };
 104 #elif GEN_GEN >= 8
 105 static const uint32_t isl_to_gen_aux_mode[] = {
 106    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 107    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 108    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 109    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 110 };
 111 #endif
 112
 113 static uint8_t
 114 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 115 {
 116    switch (dim) {
 117    default:
 118       unreachable("bad isl_surf_dim");
 119    case ISL_SURF_DIM_1D:
 120       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 121       return SURFTYPE_1D;
 122    case ISL_SURF_DIM_2D:
 123       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 124           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 125          /* We need SURFTYPE_CUBE to make cube sampling work */
 126          return SURFTYPE_CUBE;
 127       } else {
 128          /* Everything else (render and storage) treat cubes as plain
 129           * 2D array textures
 130           */
 131          return SURFTYPE_2D;
 132       }
 133    case ISL_SURF_DIM_3D:
 134       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 135       return SURFTYPE_3D;
 136    }
 137 }
 138
 139 /**
 140  * Get the horizontal and vertical alignment in the units expected by the
 141  * hardware.  Note that this does NOT give you the actual hardware enum values
 142  * but an index into the isl_to_gen_[hv]align arrays above.
 143  */
 144 UNUSED static struct isl_extent3d
 145 get_image_alignment(const struct isl_surf *surf)
 146 {
 147    if (GEN_GEN >= 9) {
 148       if (isl_tiling_is_std_y(surf->tiling) ||
 149           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 150          /* The hardware ignores the alignment values. Anyway, the surface's
 151           * true alignment is likely outside the enum range of HALIGN* and
 152           * VALIGN*.
 153           */
 154          return isl_extent3d(4, 4, 1);
 155       } else {
 156          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 157           * of surface elements (not pixels nor samples). For compressed formats,
 158           * a "surface element" is defined as a compression block.  For example,
 159           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 160           * format (ETC2 has a block height of 4), then the vertical alignment is
 161           * 4 compression blocks or, equivalently, 16 pixels.
 162           */
 163          return isl_surf_get_image_alignment_el(surf);
 164       }
 165    } else {
 166       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 167        * units of surface samples.  For example, if SurfaceVerticalAlignment
 168        * is VALIGN_4 and the surface is singlesampled, then for any surface
 169        * format (compressed or not) the vertical alignment is
 170        * 4 pixels.
 171        */
 172       return isl_surf_get_image_alignment_sa(surf);
 173    }
 174 }
 175
 176 #if GEN_GEN >= 8
 177 static uint32_t
 178 get_qpitch(const struct isl_surf *surf)
 179 {
 180    switch (surf->dim_layout) {
 181    default:
 182       unreachable("Bad isl_surf_dim");
 183    case ISL_DIM_LAYOUT_GEN4_2D:
 184       if (GEN_GEN >= 9) {
 185          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 186             /* This is rather annoying and completely undocumented.  It
 187              * appears that the hardware has a bug (or undocumented feature)
 188              * regarding stencil buffers most likely related to the way
 189              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 190              * stencil buffer normally, and use texelFetch on it, the z or
 191              * array index will get implicitly multiplied by 2 for no obvious
 192              * reason.  The fix appears to be to divide qpitch by 2 for
 193              * W-tiled surfaces.
 194              */
 195             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 196          } else {
 197             return isl_surf_get_array_pitch_el_rows(surf);
 198          }
 199       } else {
 200          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 201           *
 202           *    "This field must be set to an integer multiple of the Surface
 203           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 204           *    ETC*, and EAC* Surface Formats), this field is in units of
 205           *    rows in the uncompressed surface, and must be set to an
 206           *    integer multiple of the vertical alignment parameter "j"
 207           *    defined in the Common Surface Formats section."
 208           */
 209          return isl_surf_get_array_pitch_sa_rows(surf);
 210       }
 211    case ISL_DIM_LAYOUT_GEN9_1D:
 212       /* QPitch is usually expressed as rows of surface elements (where
 213        * a surface element is an compression block or a single surface
 214        * sample). Skylake 1D is an outlier.
 215        *
 216        * From the Skylake BSpec >> Memory Views >> Common Surface
 217        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 218        *
 219        *    Surface QPitch specifies the distance in pixels between array
 220        *    slices.
 221        */
 222       return isl_surf_get_array_pitch_el(surf);
 223    case ISL_DIM_LAYOUT_GEN4_3D:
 224       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 225        * different pitch at each LOD.  Also, the QPitch field is ignored for
 226        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 227        *
 228        *    This field specifies the distance in rows between array slices. It
 229        *    is used only in the following cases:
 230        *     - Surface Array is enabled OR
 231        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 232        *       Surface Storage Format set to MSFMT_MSS OR
 233        *     - Surface Type is SURFTYPE_CUBE
 234        *
 235        * None of the three conditions above can possibly apply to a 3D surface
 236        * so it is safe to just set QPitch to 0.
 237        */
 238       return 0;
 239    }
 240 }
 241 #endif /* GEN_GEN >= 8 */
 242
 243 void
 244 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 245                             const struct isl_surf_fill_state_info *restrict info)
 246 {
 247    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 248
 249    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 250
 251    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 252       assert(isl_format_supports_rendering(dev->info, info->view->format));
 253    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 254       assert(isl_format_supports_sampling(dev->info, info->view->format));
 255
 256    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 257     *
 258     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 259     *    format if the Surface Type is SURFTYPE_1D
 260     */
 261    if (info->surf->dim == ISL_SURF_DIM_1D)
 262       assert(!isl_format_is_compressed(info->view->format));
 263
 264    if (isl_format_is_compressed(info->surf->format)) {
 265       /* You're not allowed to make a view of a compressed format with any
 266        * format other than the surface format.  None of the userspace APIs
 267        * allow for this directly and doing so would mess up a number of
 268        * surface parameters such as Width, Height, and alignments.  Ideally,
 269        * we'd like to assert that the two formats match.  However, we have an
 270        * S3TC workaround that requires us to do reinterpretation.  So assert
 271        * that they're at least the same bpb and block size.
 272        */
 273       ASSERTED const struct isl_format_layout *surf_fmtl =
 274          isl_format_get_layout(info->surf->format);
 275       ASSERTED const struct isl_format_layout *view_fmtl =
 276          isl_format_get_layout(info->surf->format);
 277       assert(surf_fmtl->bpb == view_fmtl->bpb);
 278       assert(surf_fmtl->bw == view_fmtl->bw);
 279       assert(surf_fmtl->bh == view_fmtl->bh);
 280    }
 281
 282    s.SurfaceFormat = info->view->format;
 283
 284 #if GEN_GEN <= 5
 285    s.ColorBufferComponentWriteDisables = info->write_disables;
 286 #else
 287    assert(info->write_disables == 0);
 288 #endif
 289
 290 #if GEN_IS_HASWELL
 291    s.IntegerSurfaceFormat =
 292       isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 293 #endif
 294
 295    assert(info->surf->logical_level0_px.width > 0 &&
 296           info->surf->logical_level0_px.height > 0);
 297
 298    s.Width = info->surf->logical_level0_px.width - 1;
 299    s.Height = info->surf->logical_level0_px.height - 1;
 300
 301    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 302     * (Surface Arrays For all surfaces other than separate stencil buffer):
 303     *
 304     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 305     *  calculated in the equation above , for every other odd Surface Height
 306     *  starting from 1 i.e. 1,5,9,13"
 307     *
 308     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 309     * input for the rendering surface to achieve the same qpitch. For the
 310     * affected heights, we increment the height by 1 for the rendering
 311     * surface.
 312     */
 313    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 314        info->surf->samples > 1 &&
 315        (info->surf->logical_level0_px.height % 4) == 1)
 316       s.Height++;
 317
 318    switch (s.SurfaceType) {
 319    case SURFTYPE_1D:
 320    case SURFTYPE_2D:
 321       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 322        *
 323        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 324        *    must be set to zero if this surface is used with sampling engine
 325        *    messages."
 326        *
 327        * This restriction appears to exist only on Ivy Bridge.
 328        */
 329       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 330           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 331           info->surf->samples > 1)
 332          assert(info->view->base_array_layer == 0);
 333
 334       s.MinimumArrayElement = info->view->base_array_layer;
 335
 336       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 337        *
 338        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 339        *    by one for each increase from zero of Minimum Array Element. For
 340        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 341        *    the range of this field is reduced to [0,1023].
 342        *
 343        * In other words, 'Depth' is the number of array layers.
 344        */
 345       s.Depth = info->view->array_len - 1;
 346
 347       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 348        *
 349        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 350        *    This field must be set to the same value as the Depth field.
 351        */
 352       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 353                                ISL_SURF_USAGE_STORAGE_BIT))
 354          s.RenderTargetViewExtent = s.Depth;
 355       break;
 356    case SURFTYPE_CUBE:
 357       s.MinimumArrayElement = info->view->base_array_layer;
 358       /* Same as SURFTYPE_2D, but divided by 6 */
 359       s.Depth = info->view->array_len / 6 - 1;
 360       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 361                                ISL_SURF_USAGE_STORAGE_BIT))
 362          s.RenderTargetViewExtent = s.Depth;
 363       break;
 364    case SURFTYPE_3D:
 365       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 366        *
 367        *    If the volume texture is MIP-mapped, this field specifies the
 368        *    depth of the base MIP level.
 369        */
 370       s.Depth = info->surf->logical_level0_px.depth - 1;
 371
 372       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 373        *
 374        *    For Render Target and Typed Dataport 3D Surfaces: This field
 375        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 376        *    the LOD currently being rendered to.
 377        *
 378        * The docs specify that this only matters for render targets and
 379        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 380        * Depth field has more bits than RenderTargetViewExtent so we can have
 381        * textures with more levels than we can render to.  In order to prevent
 382        * assert-failures in the packing function below, we only set the field
 383        * when it's actually going to be used by the hardware.
 384        *
 385        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 386        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 387        * Since it's already initialized to 0, we can just leave it alone for
 388        * texture surfaces.
 389        */
 390       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 391                                ISL_SURF_USAGE_STORAGE_BIT)) {
 392          s.MinimumArrayElement = info->view->base_array_layer;
 393          s.RenderTargetViewExtent = info->view->array_len - 1;
 394       }
 395       break;
 396    default:
 397       unreachable("bad SurfaceType");
 398    }
 399
 400 #if GEN_GEN >= 7
 401    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 402 #endif
 403
 404    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 405       /* For render target surfaces, the hardware interprets field
 406        * MIPCount/LOD as LOD. The Broadwell PRM says:
 407        *
 408        *    MIPCountLOD defines the LOD that will be rendered into.
 409        *    SurfaceMinLOD is ignored.
 410        */
 411       s.MIPCountLOD = info->view->base_level;
 412       s.SurfaceMinLOD = 0;
 413    } else {
 414       /* For non render target surfaces, the hardware interprets field
 415        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 416        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 417        */
 418       s.SurfaceMinLOD = info->view->base_level;
 419       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 420    }
 421
 422 #if GEN_GEN >= 9
 423    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 424     * Start LOD" to 15 to prevent the hardware from trying to use them.
 425     */
 426    s.TiledResourceMode = NONE;
 427    s.MipTailStartLOD = 15;
 428 #endif
 429
 430 #if GEN_GEN >= 6
 431    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 432    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 433 #if GEN_GEN >= 7
 434    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 435 #endif
 436 #endif
 437
 438    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 439       /* For gen9 1-D textures, surface pitch is ignored */
 440       s.SurfacePitch = 0;
 441    } else {
 442       s.SurfacePitch = info->surf->row_pitch_B - 1;
 443    }
 444
 445 #if GEN_GEN >= 8
 446    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 447 #elif GEN_GEN == 7
 448    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 449                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 450 #endif
 451
 452 #if GEN_GEN >= 8
 453    assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
 454    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 455 #else
 456    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 457    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 458                                                       TILEWALK_XMAJOR,
 459 #endif
 460
 461 #if GEN_GEN >= 8
 462    s.RenderCacheReadWriteMode = WriteOnlyCache;
 463 #else
 464    s.RenderCacheReadWriteMode = 0;
 465 #endif
 466
 467 #if GEN_GEN >= 11
 468    /* We've seen dEQP failures when enabling this bit with UINT formats,
 469     * which particularly affects blorp_copy() operations.  It shouldn't
 470     * have any effect on UINT textures anyway, so disable it for them.
 471     */
 472    s.EnableUnormPathInColorPipe =
 473       !isl_format_has_int_channel(info->view->format);
 474 #endif
 475
 476    s.CubeFaceEnablePositiveZ = 1;
 477    s.CubeFaceEnableNegativeZ = 1;
 478    s.CubeFaceEnablePositiveY = 1;
 479    s.CubeFaceEnableNegativeY = 1;
 480    s.CubeFaceEnablePositiveX = 1;
 481    s.CubeFaceEnableNegativeX = 1;
 482
 483 #if GEN_GEN >= 6
 484    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 485 #if GEN_GEN >= 7
 486    s.MultisampledSurfaceStorageFormat =
 487       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 488 #endif
 489 #endif
 490
 491 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 492    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 493       assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
 494
 495    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
 496    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
 497    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
 498    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
 499 #else
 500    assert(isl_swizzle_is_identity(info->view->swizzle));
 501 #endif
 502
 503    s.SurfaceBaseAddress = info->address;
 504
 505 #if GEN_GEN >= 6
 506    s.MOCS = info->mocs;
 507 #endif
 508
 509 #if GEN_GEN > 4 || GEN_IS_G4X
 510    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 511       /* There are fairly strict rules about when the offsets can be used.
 512        * These are mostly taken from the Sky Lake PRM documentation for
 513        * RENDER_SURFACE_STATE.
 514        */
 515       assert(info->surf->tiling != ISL_TILING_LINEAR);
 516       assert(info->surf->dim == ISL_SURF_DIM_2D);
 517       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 518       assert(info->surf->levels == 1);
 519       assert(info->surf->logical_level0_px.array_len == 1);
 520       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 521
 522       if (GEN_GEN >= 8) {
 523          /* Broadwell added more rules. */
 524          assert(info->surf->samples == 1);
 525          if (isl_format_get_layout(info->view->format)->bpb == 8)
 526             assert(info->x_offset_sa % 16 == 0);
 527          if (isl_format_get_layout(info->view->format)->bpb == 16)
 528             assert(info->x_offset_sa % 8 == 0);
 529       }
 530
 531 #if GEN_GEN >= 7
 532       s.SurfaceArray = false;
 533 #endif
 534    }
 535
 536    const unsigned x_div = 4;
 537    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 538    assert(info->x_offset_sa % x_div == 0);
 539    assert(info->y_offset_sa % y_div == 0);
 540    s.XOffset = info->x_offset_sa / x_div;
 541    s.YOffset = info->y_offset_sa / y_div;
 542 #else
 543    assert(info->x_offset_sa == 0);
 544    assert(info->y_offset_sa == 0);
 545 #endif
 546
 547 #if GEN_GEN >= 7
 548    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 549       /* Check valid aux usages per-gen */
 550       if (GEN_GEN >= 12) {
 551          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 552                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
 553                 info->aux_usage == ISL_AUX_USAGE_MCS_CCS);
 554       } else if (GEN_GEN >= 9) {
 555          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 556                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 557                 info->aux_usage == ISL_AUX_USAGE_CCS_D ||
 558                 info->aux_usage == ISL_AUX_USAGE_CCS_E);
 559       } else if (GEN_GEN >= 8) {
 560          assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
 561                 info->aux_usage == ISL_AUX_USAGE_MCS ||
 562                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 563       } else if (GEN_GEN >= 7) {
 564          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 565                 info->aux_usage == ISL_AUX_USAGE_CCS_D);
 566       }
 567
 568       if (GEN_GEN >= 12) {
 569          /* We don't need an auxiliary surface for CCS on gen12+ */
 570          assert (info->aux_usage == ISL_AUX_USAGE_CCS_E ||
 571                  info->aux_usage == ISL_AUX_USAGE_MC || info->aux_surf);
 572       } else {
 573          /* We must have an auxiliary surface */
 574          assert(info->aux_surf);
 575       }
 576
 577       /* The docs don't appear to say anything whatsoever about compression
 578        * and the data port.  Testing seems to indicate that the data port
 579        * completely ignores the AuxiliarySurfaceMode field.
 580        */
 581       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 582
 583       if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
 584          /* The number of samples must be 1 */
 585          assert(info->surf->samples == 1);
 586
 587          /* The dimension must not be 3D */
 588          assert(info->surf->dim != ISL_SURF_DIM_3D);
 589
 590          /* The format must be one of the following: */
 591          switch (info->view->format) {
 592          case ISL_FORMAT_R32_FLOAT:
 593          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 594          case ISL_FORMAT_R16_UNORM:
 595             break;
 596          default:
 597             assert(!"Incompatible HiZ Sampling format");
 598             break;
 599          }
 600       }
 601
 602 #if GEN_GEN >= 8
 603       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 604 #else
 605       s.MCSEnable = true;
 606 #endif
 607    }
 608
 609    /* The auxiliary buffer info is filled when it's useable by the HW. On
 610     * gen12 and above, CCS is controlled by the aux table and not the
 611     * auxiliary surface information in SURFACE_STATE.
 612     */
 613    if (info->aux_usage != ISL_AUX_USAGE_NONE &&
 614        ((info->aux_usage != ISL_AUX_USAGE_MC &&
 615          info->aux_usage != ISL_AUX_USAGE_CCS_E) || GEN_GEN <= 11)) {
 616
 617       assert(info->aux_surf != NULL);
 618
 619       struct isl_tile_info tile_info;
 620       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 621       uint32_t pitch_in_tiles =
 622          info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 623
 624       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 625       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 626
 627 #if GEN_GEN >= 8
 628       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 629        * doesn't expect our definition of the compression, it expects qpitch
 630        * in units of samples on the main surface.
 631        */
 632       s.AuxiliarySurfaceQPitch =
 633          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 634 #endif
 635    }
 636 #endif
 637
 638 #if GEN_GEN >= 8 && GEN_GEN < 11
 639    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 640     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 641     *
 642     *    This bit must be set for the following surface types: BC2_UNORM
 643     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 644     */
 645    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 646       switch (info->view->format) {
 647       case ISL_FORMAT_BC2_UNORM:
 648       case ISL_FORMAT_BC3_UNORM:
 649       case ISL_FORMAT_BC5_UNORM:
 650       case ISL_FORMAT_BC5_SNORM:
 651       case ISL_FORMAT_BC7_UNORM:
 652          s.SamplerL2BypassModeDisable = true;
 653          break;
 654       default:
 655          /* From the SKL PRM, Programming Note under Sampler Output Channel
 656           * Mapping:
 657           *
 658           *    If a surface has an associated HiZ Auxilliary surface, the
 659           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 660           *    must be set.
 661           */
 662          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 663             s.SamplerL2BypassModeDisable = true;
 664          break;
 665       }
 666    }
 667 #endif
 668
 669    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 670       if (info->use_clear_address) {
 671 #if GEN_GEN >= 10
 672          s.ClearValueAddressEnable = true;
 673          s.ClearValueAddress = info->clear_address;
 674 #else
 675          unreachable("Gen9 and earlier do not support indirect clear colors");
 676 #endif
 677       }
 678
 679 #if GEN_GEN == 11
 680       /*
 681        * From BXML > GT > Shared Functions > vol5c Shared Functions >
 682        * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
 683        *
 684        *   Project: Gen11
 685        *
 686        *   "Enables Pixel backend hw to convert clear values into native format
 687        *    and write back to clear address, so that display and sampler can use
 688        *    the converted value for resolving fast cleared RTs."
 689        *
 690        * Summary:
 691        *   Clear color conversion must be enabled if the clear color is stored
 692        *   indirectly and fast color clears are enabled.
 693        */
 694       if (info->use_clear_address) {
 695          s.ClearColorConversionEnable = true;
 696       }
 697 #endif
 698
 699 #if GEN_GEN >= 12
 700       assert(info->use_clear_address);
 701 #elif GEN_GEN >= 9
 702       if (!info->use_clear_address) {
 703          s.RedClearColor = info->clear_color.u32[0];
 704          s.GreenClearColor = info->clear_color.u32[1];
 705          s.BlueClearColor = info->clear_color.u32[2];
 706          s.AlphaClearColor = info->clear_color.u32[3];
 707       }
 708 #elif GEN_GEN >= 7
 709       /* Prior to Sky Lake, we only have one bit for the clear color which
 710        * gives us 0 or 1 in whatever the surface's format happens to be.
 711        */
 712       if (isl_format_has_int_channel(info->view->format)) {
 713          for (unsigned i = 0; i < 4; i++) {
 714             assert(info->clear_color.u32[i] == 0 ||
 715                    info->clear_color.u32[i] == 1);
 716          }
 717          s.RedClearColor = info->clear_color.u32[0] != 0;
 718          s.GreenClearColor = info->clear_color.u32[1] != 0;
 719          s.BlueClearColor = info->clear_color.u32[2] != 0;
 720          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 721       } else {
 722          for (unsigned i = 0; i < 4; i++) {
 723             assert(info->clear_color.f32[i] == 0.0f ||
 724                    info->clear_color.f32[i] == 1.0f);
 725          }
 726          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 727          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 728          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 729          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 730       }
 731 #endif
 732    }
 733
 734    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 735 }
 736
 737 void
 738 isl_genX(buffer_fill_state_s)(void *state,
 739                               const struct isl_buffer_fill_state_info *restrict info)
 740 {
 741    uint64_t buffer_size = info->size_B;
 742
 743    /* Uniform and Storage buffers need to have surface size not less that the
 744     * aligned 32-bit size of the buffer. To calculate the array lenght on
 745     * unsized arrays in StorageBuffer the last 2 bits store the padding size
 746     * added to the surface, so we can calculate latter the original buffer
 747     * size to know the number of elements.
 748     *
 749     *  surface_size = isl_align(buffer_size, 4) +
 750     *                 (isl_align(buffer_size) - buffer_size)
 751     *
 752     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
 753     */
 754    if (info->format == ISL_FORMAT_RAW  ||
 755        info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
 756       assert(info->stride_B == 1);
 757       uint64_t aligned_size = isl_align(buffer_size, 4);
 758       buffer_size = aligned_size + (aligned_size - buffer_size);
 759    }
 760
 761    uint32_t num_elements = buffer_size / info->stride_B;
 762
 763    if (GEN_GEN >= 7) {
 764       /* From the IVB PRM, SURFACE_STATE::Height,
 765        *
 766        *    For typed buffer and structured buffer surfaces, the number
 767        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 768        *    surfaces, the number of entries in the buffer is the number of bytes
 769        *    which can range from 1 to 2^30.
 770        */
 771       if (info->format == ISL_FORMAT_RAW) {
 772          assert(num_elements <= (1ull << 30));
 773          assert(num_elements > 0);
 774       } else {
 775          assert(num_elements <= (1ull << 27));
 776       }
 777    } else {
 778       assert(num_elements <= (1ull << 27));
 779    }
 780
 781    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 782
 783    s.SurfaceType = SURFTYPE_BUFFER;
 784    s.SurfaceFormat = info->format;
 785
 786 #if GEN_GEN >= 6
 787    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 788 #if GEN_GEN >= 7
 789    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 790    s.SurfaceArray = false;
 791 #endif
 792 #endif
 793
 794 #if GEN_GEN >= 7
 795    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 796    s.Width = (num_elements - 1) & 0x7f;
 797    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 798 #else
 799    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 800    s.Width = (num_elements - 1) & 0x7f;
 801    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 802 #endif
 803
 804    s.SurfacePitch = info->stride_B - 1;
 805
 806 #if GEN_GEN >= 6
 807    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 808 #endif
 809
 810 #if (GEN_GEN >= 8)
 811    s.TileMode = LINEAR;
 812 #else
 813    s.TiledSurface = false;
 814 #endif
 815
 816 #if (GEN_GEN >= 8)
 817    s.RenderCacheReadWriteMode = WriteOnlyCache;
 818 #else
 819    s.RenderCacheReadWriteMode = 0;
 820 #endif
 821
 822    s.SurfaceBaseAddress = info->address;
 823 #if GEN_GEN >= 6
 824    s.MOCS = info->mocs;
 825 #endif
 826
 827 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 828    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
 829    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
 830    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
 831    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
 832 #endif
 833
 834    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 835 }
 836
 837 void
 838 isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
 839 {
 840    struct GENX(RENDER_SURFACE_STATE) s = {
 841       .SurfaceType = SURFTYPE_NULL,
 842       /* We previously had this format set to B8G8R8A8_UNORM but ran into
 843        * hangs on IVB. R32_UINT seems to work for everybody.
 844        *
 845        * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
 846        */
 847       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 848 #if GEN_GEN >= 7
 849       .SurfaceArray = size.depth > 1,
 850 #endif
 851 #if GEN_GEN >= 8
 852       .TileMode = YMAJOR,
 853 #else
 854       .TiledSurface = true,
 855       .TileWalk = TILEWALK_YMAJOR,
 856 #endif
 857 #if GEN_GEN == 7
 858       /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
 859        * Functions"
 860        *
 861        * RENDER_SURFACE_STATE::Surface Vertical Alignment
 862        *
 863        *    "This field must be set to VALIGN_4 for all tiled Y Render Target
 864        *     surfaces."
 865        *
 866        * Affect IVB, HSW.
 867        */
 868       .SurfaceVerticalAlignment = VALIGN_4,
 869 #endif
 870       .Width = size.width - 1,
 871       .Height = size.height - 1,
 872       .Depth = size.depth - 1,
 873       .RenderTargetViewExtent = size.depth - 1,
 874 #if GEN_GEN <= 5
 875       .ColorBufferComponentWriteDisables = 0xf,
 876 #endif
 877    };
 878    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 879 }