2 * Copyright 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #define __gen_address_type uint64_t
27 #define __gen_user_data void
29 static inline uint64_t
30 __gen_combine_address(void *data
, void *loc
, uint64_t addr
, uint32_t delta
)
35 #include "genxml/gen_macros.h"
36 #include "genxml/genX_pack.h"
40 #define __PASTE2(x, y) x ## y
41 #define __PASTE(x, y) __PASTE2(x, y)
42 #define isl_genX(x) __PASTE(isl_, genX(x))
45 static const uint8_t isl_to_gen_halign
[] = {
51 static const uint8_t isl_to_gen_halign
[] = {
58 static const uint8_t isl_to_gen_valign
[] = {
64 static const uint8_t isl_to_gen_valign
[] = {
71 static const uint8_t isl_to_gen_tiling
[] = {
72 [ISL_TILING_LINEAR
] = LINEAR
,
73 [ISL_TILING_X
] = XMAJOR
,
74 [ISL_TILING_Y0
] = YMAJOR
,
75 [ISL_TILING_Yf
] = YMAJOR
,
76 [ISL_TILING_Ys
] = YMAJOR
,
77 [ISL_TILING_W
] = WMAJOR
,
81 static const uint32_t isl_to_gen_multisample_layout
[] = {
82 [ISL_MSAA_LAYOUT_NONE
] = MSFMT_MSS
,
83 [ISL_MSAA_LAYOUT_INTERLEAVED
] = MSFMT_DEPTH_STENCIL
,
84 [ISL_MSAA_LAYOUT_ARRAY
] = MSFMT_MSS
,
88 get_surftype(enum isl_surf_dim dim
, isl_surf_usage_flags_t usage
)
92 unreachable("bad isl_surf_dim");
94 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
97 if (usage
& ISL_SURF_USAGE_STORAGE_BIT
) {
98 /* Storage images are always plain 2-D, not cube */
100 } else if (usage
& ISL_SURF_USAGE_CUBE_BIT
) {
101 return SURFTYPE_CUBE
;
105 case ISL_SURF_DIM_3D
:
106 assert(!(usage
& ISL_SURF_USAGE_CUBE_BIT
));
112 * Get the horizontal and vertical alignment in the units expected by the
113 * hardware. Note that this does NOT give you the actual hardware enum values
114 * but an index into the isl_to_gen_[hv]align arrays above.
116 static struct isl_extent3d
117 get_image_alignment(const struct isl_surf
*surf
)
120 if (isl_tiling_is_std_y(surf
->tiling
) ||
121 surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
122 /* The hardware ignores the alignment values. Anyway, the surface's
123 * true alignment is likely outside the enum range of HALIGN* and
126 return isl_extent3d(0, 0, 0);
128 /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
129 * of surface elements (not pixels nor samples). For compressed formats,
130 * a "surface element" is defined as a compression block. For example,
131 * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
132 * format (ETC2 has a block height of 4), then the vertical alignment is
133 * 4 compression blocks or, equivalently, 16 pixels.
135 return isl_surf_get_image_alignment_el(surf
);
138 /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
139 * units of surface samples. For example, if SurfaceVerticalAlignment
140 * is VALIGN_4 and the surface is singlesampled, then for any surface
141 * format (compressed or not) the vertical alignment is
144 return isl_surf_get_image_alignment_sa(surf
);
150 get_qpitch(const struct isl_surf
*surf
)
152 switch (surf
->dim_layout
) {
154 unreachable("Bad isl_surf_dim");
155 case ISL_DIM_LAYOUT_GEN4_2D
:
156 case ISL_DIM_LAYOUT_GEN4_3D
:
158 return isl_surf_get_array_pitch_el_rows(surf
);
160 /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
162 * "This field must be set to an integer multiple of the Surface
163 * Vertical Alignment. For compressed textures (BC*, FXT1,
164 * ETC*, and EAC* Surface Formats), this field is in units of
165 * rows in the uncompressed surface, and must be set to an
166 * integer multiple of the vertical alignment parameter "j"
167 * defined in the Common Surface Formats section."
169 return isl_surf_get_array_pitch_sa_rows(surf
);
171 case ISL_DIM_LAYOUT_GEN9_1D
:
172 /* QPitch is usually expressed as rows of surface elements (where
173 * a surface element is an compression block or a single surface
174 * sample). Skylake 1D is an outlier.
176 * From the Skylake BSpec >> Memory Views >> Common Surface
177 * Formats >> Surface Layout and Tiling >> 1D Surfaces:
179 * Surface QPitch specifies the distance in pixels between array
182 return isl_surf_get_array_pitch_el(surf
);
185 #endif /* GEN_GEN >= 8 */
188 isl_genX(surf_fill_state_s
)(const struct isl_device
*dev
, void *state
,
189 const struct isl_surf_fill_state_info
*restrict info
)
191 struct GENX(RENDER_SURFACE_STATE
) s
= { 0 };
193 s
.SurfaceType
= get_surftype(info
->surf
->dim
, info
->view
->usage
);
195 if (info
->view
->usage
& ISL_SURF_USAGE_STORAGE_BIT
) {
197 isl_lower_storage_image_format(dev
->info
, info
->view
->format
);
199 s
.SurfaceFormat
= info
->view
->format
;
203 s
.IntegerSurfaceFormat
= isl_format_has_int_channel(s
.SurfaceFormat
);
206 s
.Width
= info
->surf
->logical_level0_px
.width
- 1;
207 s
.Height
= info
->surf
->logical_level0_px
.height
- 1;
209 switch (s
.SurfaceType
) {
212 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
214 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
216 * For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
217 * by one for each increase from zero of Minimum Array Element. For
218 * example, if Minimum Array Element is set to 1024 on a 2D surface,
219 * the range of this field is reduced to [0,1023].
221 * In other words, 'Depth' is the number of array layers.
223 s
.Depth
= info
->view
->array_len
- 1;
225 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
227 * For Render Target and Typed Dataport 1D and 2D Surfaces:
228 * This field must be set to the same value as the Depth field.
230 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
231 ISL_SURF_USAGE_STORAGE_BIT
))
232 s
.RenderTargetViewExtent
= s
.Depth
;
235 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
236 /* Same as SURFTYPE_2D, but divided by 6 */
237 s
.Depth
= info
->view
->array_len
/ 6 - 1;
238 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
239 ISL_SURF_USAGE_STORAGE_BIT
))
240 s
.RenderTargetViewExtent
= s
.Depth
;
243 s
.MinimumArrayElement
= info
->view
->base_array_layer
;
245 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
247 * If the volume texture is MIP-mapped, this field specifies the
248 * depth of the base MIP level.
250 s
.Depth
= info
->surf
->logical_level0_px
.depth
- 1;
252 /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
254 * For Render Target and Typed Dataport 3D Surfaces: This field
255 * indicates the extent of the accessible 'R' coordinates minus 1 on
256 * the LOD currently being rendered to.
258 * The docs specify that this only matters for render targets and
259 * surfaces used with typed dataport messages. Prior to Ivy Bridge, the
260 * Depth field has more bits than RenderTargetViewExtent so we can have
261 * textures with more levels than we can render to. In order to prevent
262 * assert-failures in the packing function below, we only set the field
263 * when it's actually going to be used by the hardware.
265 if (info
->view
->usage
& (ISL_SURF_USAGE_RENDER_TARGET_BIT
|
266 ISL_SURF_USAGE_STORAGE_BIT
)) {
267 s
.RenderTargetViewExtent
= isl_minify(info
->surf
->logical_level0_px
.depth
,
268 info
->view
->base_level
) - 1;
272 unreachable("bad SurfaceType");
275 s
.SurfaceArray
= info
->surf
->dim
!= ISL_SURF_DIM_3D
;
277 if (info
->view
->usage
& ISL_SURF_USAGE_RENDER_TARGET_BIT
) {
278 /* For render target surfaces, the hardware interprets field
279 * MIPCount/LOD as LOD. The Broadwell PRM says:
281 * MIPCountLOD defines the LOD that will be rendered into.
282 * SurfaceMinLOD is ignored.
284 s
.MIPCountLOD
= info
->view
->base_level
;
287 /* For non render target surfaces, the hardware interprets field
288 * MIPCount/LOD as MIPCount. The range of levels accessible by the
289 * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
291 s
.SurfaceMinLOD
= info
->view
->base_level
;
292 s
.MIPCountLOD
= MAX(info
->view
->levels
, 1) - 1;
296 /* We don't use miptails yet. The PRM recommends that you set "Mip Tail
297 * Start LOD" to 15 to prevent the hardware from trying to use them.
299 s
.TiledResourceMode
= NONE
;
300 s
.MipTailStartLOD
= 15;
303 const struct isl_extent3d image_align
= get_image_alignment(info
->surf
);
304 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[image_align
.height
];
305 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[image_align
.width
];
307 if (info
->surf
->tiling
== ISL_TILING_W
) {
308 /* From the Broadwell PRM documentation for this field:
310 * "If the surface is a stencil buffer (and thus has Tile Mode set
311 * to TILEMODE_WMAJOR), the pitch must be set to 2x the value
312 * computed based on width, as the stencil buffer is stored with
313 * two rows interleaved."
315 s
.SurfacePitch
= info
->surf
->row_pitch
* 2 - 1;
316 } else if (info
->surf
->dim_layout
== ISL_DIM_LAYOUT_GEN9_1D
) {
317 /* For gen9 1-D textures, surface pitch is ignored */
320 s
.SurfacePitch
= info
->surf
->row_pitch
- 1;
324 s
.SurfaceQPitch
= get_qpitch(info
->surf
) >> 2;
326 s
.SurfaceArraySpacing
= info
->surf
->array_pitch_span
==
327 ISL_ARRAY_PITCH_SPAN_COMPACT
;
331 s
.TileMode
= isl_to_gen_tiling
[info
->surf
->tiling
];
333 s
.TiledSurface
= info
->surf
->tiling
!= ISL_TILING_LINEAR
,
334 s
.TileWalk
= info
->surf
->tiling
== ISL_TILING_Y0
? TILEWALK_YMAJOR
:
339 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
341 s
.RenderCacheReadWriteMode
= 0;
344 if (info
->view
->usage
& ISL_SURF_USAGE_CUBE_BIT
) {
346 s
.CubeFaceEnablePositiveZ
= 1;
347 s
.CubeFaceEnableNegativeZ
= 1;
348 s
.CubeFaceEnablePositiveY
= 1;
349 s
.CubeFaceEnableNegativeY
= 1;
350 s
.CubeFaceEnablePositiveX
= 1;
351 s
.CubeFaceEnableNegativeX
= 1;
353 s
.CubeFaceEnables
= 0x3f;
357 s
.MultisampledSurfaceStorageFormat
=
358 isl_to_gen_multisample_layout
[info
->surf
->msaa_layout
];
359 s
.NumberofMultisamples
= ffs(info
->surf
->samples
) - 1;
361 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
362 s
.ShaderChannelSelectRed
= info
->view
->channel_select
[0];
363 s
.ShaderChannelSelectGreen
= info
->view
->channel_select
[1];
364 s
.ShaderChannelSelectBlue
= info
->view
->channel_select
[2];
365 s
.ShaderChannelSelectAlpha
= info
->view
->channel_select
[3];
368 s
.SurfaceBaseAddress
= info
->address
;
372 s
.AuxiliarySurfaceMode
= AUX_NONE
;
378 /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
379 * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
381 * This bit must be set for the following surface types: BC2_UNORM
382 * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
384 if (GEN_GEN
>= 9 || dev
->info
->is_cherryview
) {
385 switch (info
->view
->format
) {
386 case ISL_FORMAT_BC2_UNORM
:
387 case ISL_FORMAT_BC3_UNORM
:
388 case ISL_FORMAT_BC5_UNORM
:
389 case ISL_FORMAT_BC5_SNORM
:
390 case ISL_FORMAT_BC7_UNORM
:
391 s
.SamplerL2BypassModeDisable
= true;
400 s
.RedClearColor
= info
->clear_color
.u32
[0];
401 s
.GreenClearColor
= info
->clear_color
.u32
[1];
402 s
.BlueClearColor
= info
->clear_color
.u32
[2];
403 s
.AlphaClearColor
= info
->clear_color
.u32
[3];
405 /* Prior to Sky Lake, we only have one bit for the clear color which
406 * gives us 0 or 1 in whatever the surface's format happens to be.
408 if (isl_format_has_int_channel(info
->view
->format
)) {
409 for (unsigned i
= 0; i
< 4; i
++) {
410 assert(info
->clear_color
.u32
[i
] == 0 ||
411 info
->clear_color
.u32
[i
] == 1);
413 s
.RedClearColor
= info
->clear_color
.u32
[0] != 0;
414 s
.GreenClearColor
= info
->clear_color
.u32
[1] != 0;
415 s
.BlueClearColor
= info
->clear_color
.u32
[2] != 0;
416 s
.AlphaClearColor
= info
->clear_color
.u32
[3] != 0;
418 for (unsigned i
= 0; i
< 4; i
++) {
419 assert(info
->clear_color
.f32
[i
] == 0.0f
||
420 info
->clear_color
.f32
[i
] == 1.0f
);
422 s
.RedClearColor
= info
->clear_color
.f32
[0] != 0.0f
;
423 s
.GreenClearColor
= info
->clear_color
.f32
[1] != 0.0f
;
424 s
.BlueClearColor
= info
->clear_color
.f32
[2] != 0.0f
;
425 s
.AlphaClearColor
= info
->clear_color
.f32
[3] != 0.0f
;
429 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);
433 isl_genX(buffer_fill_state_s
)(void *state
,
434 const struct isl_buffer_fill_state_info
*restrict info
)
436 uint32_t num_elements
= info
->size
/ info
->stride
;
439 if (info
->format
== ISL_FORMAT_RAW
) {
440 assert(num_elements
<= (1ull << 31));
441 assert((num_elements
& 3) == 0);
443 assert(num_elements
<= (1ull << 27));
446 assert(num_elements
<= (1ull << 27));
449 struct GENX(RENDER_SURFACE_STATE
) s
= { 0, };
451 s
.SurfaceType
= SURFTYPE_BUFFER
;
452 s
.SurfaceArray
= false;
453 s
.SurfaceFormat
= info
->format
;
454 s
.SurfaceVerticalAlignment
= isl_to_gen_valign
[4];
455 s
.SurfaceHorizontalAlignment
= isl_to_gen_halign
[4];
456 s
.Height
= ((num_elements
- 1) >> 7) & 0x3fff;
457 s
.Width
= (num_elements
- 1) & 0x7f;
458 s
.Depth
= ((num_elements
- 1) >> 21) & 0x3ff;
459 s
.SurfacePitch
= info
->stride
- 1;
460 s
.NumberofMultisamples
= MULTISAMPLECOUNT_1
;
465 s
.TiledSurface
= false;
469 s
.RenderCacheReadWriteMode
= WriteOnlyCache
;
471 s
.RenderCacheReadWriteMode
= 0;
474 s
.SurfaceBaseAddress
= info
->address
;
477 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
478 s
.ShaderChannelSelectRed
= SCS_RED
;
479 s
.ShaderChannelSelectGreen
= SCS_GREEN
;
480 s
.ShaderChannelSelectBlue
= SCS_BLUE
;
481 s
.ShaderChannelSelectAlpha
= SCS_ALPHA
;
484 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
, &s
);