src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 9
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  93    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  94    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  95    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  96 };
  97 #elif GEN_GEN >= 8
  98 static const uint32_t isl_to_gen_aux_mode[] = {
  99    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 100    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 101    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 102    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 103 };
 104 #endif
 105
 106 static uint8_t
 107 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 108 {
 109    switch (dim) {
 110    default:
 111       unreachable("bad isl_surf_dim");
 112    case ISL_SURF_DIM_1D:
 113       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 114       return SURFTYPE_1D;
 115    case ISL_SURF_DIM_2D:
 116       if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
 117           (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
 118          /* We need SURFTYPE_CUBE to make cube sampling work */
 119          return SURFTYPE_CUBE;
 120       } else {
 121          /* Everything else (render and storage) treat cubes as plain
 122           * 2D array textures
 123           */
 124          return SURFTYPE_2D;
 125       }
 126    case ISL_SURF_DIM_3D:
 127       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 128       return SURFTYPE_3D;
 129    }
 130 }
 131
 132 /**
 133  * Get the horizontal and vertical alignment in the units expected by the
 134  * hardware.  Note that this does NOT give you the actual hardware enum values
 135  * but an index into the isl_to_gen_[hv]align arrays above.
 136  */
 137 static inline struct isl_extent3d
 138 get_image_alignment(const struct isl_surf *surf)
 139 {
 140    if (GEN_GEN >= 9) {
 141       if (isl_tiling_is_std_y(surf->tiling) ||
 142           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 143          /* The hardware ignores the alignment values. Anyway, the surface's
 144           * true alignment is likely outside the enum range of HALIGN* and
 145           * VALIGN*.
 146           */
 147          return isl_extent3d(4, 4, 1);
 148       } else {
 149          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 150           * of surface elements (not pixels nor samples). For compressed formats,
 151           * a "surface element" is defined as a compression block.  For example,
 152           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 153           * format (ETC2 has a block height of 4), then the vertical alignment is
 154           * 4 compression blocks or, equivalently, 16 pixels.
 155           */
 156          return isl_surf_get_image_alignment_el(surf);
 157       }
 158    } else {
 159       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 160        * units of surface samples.  For example, if SurfaceVerticalAlignment
 161        * is VALIGN_4 and the surface is singlesampled, then for any surface
 162        * format (compressed or not) the vertical alignment is
 163        * 4 pixels.
 164        */
 165       return isl_surf_get_image_alignment_sa(surf);
 166    }
 167 }
 168
 169 #if GEN_GEN >= 8
 170 static uint32_t
 171 get_qpitch(const struct isl_surf *surf)
 172 {
 173    switch (surf->dim_layout) {
 174    default:
 175       unreachable("Bad isl_surf_dim");
 176    case ISL_DIM_LAYOUT_GEN4_2D:
 177       if (GEN_GEN >= 9) {
 178          if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
 179             /* This is rather annoying and completely undocumented.  It
 180              * appears that the hardware has a bug (or undocumented feature)
 181              * regarding stencil buffers most likely related to the way
 182              * W-tiling is handled as modified Y-tiling.  If you bind a 3-D
 183              * stencil buffer normally, and use texelFetch on it, the z or
 184              * array index will get implicitly multiplied by 2 for no obvious
 185              * reason.  The fix appears to be to divide qpitch by 2 for
 186              * W-tiled surfaces.
 187              */
 188             return isl_surf_get_array_pitch_el_rows(surf) / 2;
 189          } else {
 190             return isl_surf_get_array_pitch_el_rows(surf);
 191          }
 192       } else {
 193          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 194           *
 195           *    "This field must be set to an integer multiple of the Surface
 196           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 197           *    ETC*, and EAC* Surface Formats), this field is in units of
 198           *    rows in the uncompressed surface, and must be set to an
 199           *    integer multiple of the vertical alignment parameter "j"
 200           *    defined in the Common Surface Formats section."
 201           */
 202          return isl_surf_get_array_pitch_sa_rows(surf);
 203       }
 204    case ISL_DIM_LAYOUT_GEN9_1D:
 205       /* QPitch is usually expressed as rows of surface elements (where
 206        * a surface element is an compression block or a single surface
 207        * sample). Skylake 1D is an outlier.
 208        *
 209        * From the Skylake BSpec >> Memory Views >> Common Surface
 210        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 211        *
 212        *    Surface QPitch specifies the distance in pixels between array
 213        *    slices.
 214        */
 215       return isl_surf_get_array_pitch_el(surf);
 216    case ISL_DIM_LAYOUT_GEN4_3D:
 217       /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
 218        * different pitch at each LOD.  Also, the QPitch field is ignored for
 219        * these surfaces.  From the Broadwell PRM documentation for QPitch:
 220        *
 221        *    This field specifies the distance in rows between array slices. It
 222        *    is used only in the following cases:
 223        *     - Surface Array is enabled OR
 224        *     - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
 225        *       Surface Storage Format set to MSFMT_MSS OR
 226        *     - Surface Type is SURFTYPE_CUBE
 227        *
 228        * None of the three conditions above can possibly apply to a 3D surface
 229        * so it is safe to just set QPitch to 0.
 230        */
 231       return 0;
 232    }
 233 }
 234 #endif /* GEN_GEN >= 8 */
 235
 236 void
 237 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 238                             const struct isl_surf_fill_state_info *restrict info)
 239 {
 240    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 241
 242    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 243
 244    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 245       assert(isl_format_supports_rendering(dev->info, info->view->format));
 246    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 247       assert(isl_format_supports_sampling(dev->info, info->view->format));
 248
 249    /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
 250     *
 251     *    This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
 252     *    format if the Surface Type is SURFTYPE_1D
 253     */
 254    if (info->surf->dim == ISL_SURF_DIM_1D)
 255       assert(!isl_format_is_compressed(info->view->format));
 256
 257    s.SurfaceFormat = info->view->format;
 258
 259 #if GEN_GEN <= 5
 260    s.ColorBufferComponentWriteDisables = info->write_disables;
 261 #else
 262    assert(info->write_disables == 0);
 263 #endif
 264
 265 #if GEN_IS_HASWELL
 266    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 267 #endif
 268
 269    assert(info->surf->logical_level0_px.width > 0 &&
 270           info->surf->logical_level0_px.height > 0);
 271
 272    s.Width = info->surf->logical_level0_px.width - 1;
 273    s.Height = info->surf->logical_level0_px.height - 1;
 274
 275    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 276     * (Surface Arrays For all surfaces other than separate stencil buffer):
 277     *
 278     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 279     *  calculated in the equation above , for every other odd Surface Height
 280     *  starting from 1 i.e. 1,5,9,13"
 281     *
 282     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 283     * input for the rendering surface to achieve the same qpitch. For the
 284     * affected heights, we increment the height by 1 for the rendering
 285     * surface.
 286     */
 287    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 288        info->surf->samples > 1 &&
 289        (info->surf->logical_level0_px.height % 4) == 1)
 290       s.Height++;
 291
 292    switch (s.SurfaceType) {
 293    case SURFTYPE_1D:
 294    case SURFTYPE_2D:
 295       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 296        *
 297        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 298        *    must be set to zero if this surface is used with sampling engine
 299        *    messages."
 300        *
 301        * This restriction appears to exist only on Ivy Bridge.
 302        */
 303       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 304           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 305           info->surf->samples > 1)
 306          assert(info->view->base_array_layer == 0);
 307
 308       s.MinimumArrayElement = info->view->base_array_layer;
 309
 310       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 311        *
 312        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 313        *    by one for each increase from zero of Minimum Array Element. For
 314        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 315        *    the range of this field is reduced to [0,1023].
 316        *
 317        * In other words, 'Depth' is the number of array layers.
 318        */
 319       s.Depth = info->view->array_len - 1;
 320
 321       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 322        *
 323        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 324        *    This field must be set to the same value as the Depth field.
 325        */
 326       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 327                                ISL_SURF_USAGE_STORAGE_BIT))
 328          s.RenderTargetViewExtent = s.Depth;
 329       break;
 330    case SURFTYPE_CUBE:
 331       s.MinimumArrayElement = info->view->base_array_layer;
 332       /* Same as SURFTYPE_2D, but divided by 6 */
 333       s.Depth = info->view->array_len / 6 - 1;
 334       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 335                                ISL_SURF_USAGE_STORAGE_BIT))
 336          s.RenderTargetViewExtent = s.Depth;
 337       break;
 338    case SURFTYPE_3D:
 339       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 340        *
 341        *    If the volume texture is MIP-mapped, this field specifies the
 342        *    depth of the base MIP level.
 343        */
 344       s.Depth = info->surf->logical_level0_px.depth - 1;
 345
 346       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 347        *
 348        *    For Render Target and Typed Dataport 3D Surfaces: This field
 349        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 350        *    the LOD currently being rendered to.
 351        *
 352        * The docs specify that this only matters for render targets and
 353        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 354        * Depth field has more bits than RenderTargetViewExtent so we can have
 355        * textures with more levels than we can render to.  In order to prevent
 356        * assert-failures in the packing function below, we only set the field
 357        * when it's actually going to be used by the hardware.
 358        *
 359        * Similaraly, the MinimumArrayElement field is ignored by all hardware
 360        * prior to Sky Lake when texturing and we want it set to 0 anyway.
 361        * Since it's already initialized to 0, we can just leave it alone for
 362        * texture surfaces.
 363        */
 364       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 365                                ISL_SURF_USAGE_STORAGE_BIT)) {
 366          s.MinimumArrayElement = info->view->base_array_layer;
 367          s.RenderTargetViewExtent = info->view->array_len - 1;
 368       }
 369       break;
 370    default:
 371       unreachable("bad SurfaceType");
 372    }
 373
 374 #if GEN_GEN >= 7
 375    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 376 #endif
 377
 378    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 379       /* For render target surfaces, the hardware interprets field
 380        * MIPCount/LOD as LOD. The Broadwell PRM says:
 381        *
 382        *    MIPCountLOD defines the LOD that will be rendered into.
 383        *    SurfaceMinLOD is ignored.
 384        */
 385       s.MIPCountLOD = info->view->base_level;
 386       s.SurfaceMinLOD = 0;
 387    } else {
 388       /* For non render target surfaces, the hardware interprets field
 389        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 390        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 391        */
 392       s.SurfaceMinLOD = info->view->base_level;
 393       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 394    }
 395
 396 #if GEN_GEN >= 9
 397    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 398     * Start LOD" to 15 to prevent the hardware from trying to use them.
 399     */
 400    s.TiledResourceMode = NONE;
 401    s.MipTailStartLOD = 15;
 402 #endif
 403
 404 #if GEN_GEN >= 6
 405    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 406    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 407 #if GEN_GEN >= 7
 408    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 409 #endif
 410 #endif
 411
 412    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 413       /* For gen9 1-D textures, surface pitch is ignored */
 414       s.SurfacePitch = 0;
 415    } else {
 416       s.SurfacePitch = info->surf->row_pitch - 1;
 417    }
 418
 419 #if GEN_GEN >= 8
 420    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 421 #elif GEN_GEN == 7
 422    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 423                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 424 #endif
 425
 426 #if GEN_GEN >= 8
 427    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 428 #else
 429    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 430    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 431                                                       TILEWALK_XMAJOR,
 432 #endif
 433
 434 #if GEN_GEN >= 8
 435    s.RenderCacheReadWriteMode = WriteOnlyCache;
 436 #else
 437    s.RenderCacheReadWriteMode = 0;
 438 #endif
 439
 440    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 441 #if GEN_GEN >= 8
 442       s.CubeFaceEnablePositiveZ = 1;
 443       s.CubeFaceEnableNegativeZ = 1;
 444       s.CubeFaceEnablePositiveY = 1;
 445       s.CubeFaceEnableNegativeY = 1;
 446       s.CubeFaceEnablePositiveX = 1;
 447       s.CubeFaceEnableNegativeX = 1;
 448 #else
 449       s.CubeFaceEnables = 0x3f;
 450 #endif
 451    }
 452
 453 #if GEN_GEN >= 6
 454    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 455 #if GEN_GEN >= 7
 456    s.MultisampledSurfaceStorageFormat =
 457       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 458 #endif
 459 #endif
 460
 461 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 462    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 463       /* From the Sky Lake PRM Vol. 2d,
 464        * RENDER_SURFACE_STATE::Shader Channel Select Red
 465        *
 466        *    "For Render Target, Red, Green and Blue Shader Channel Selects
 467        *    MUST be such that only valid components can be swapped i.e. only
 468        *    change the order of components in the pixel. Any other values for
 469        *    these Shader Channel Select fields are not valid for Render
 470        *    Targets. This also means that there MUST not be multiple shader
 471        *    channels mapped to the same RT channel."
 472        */
 473       assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
 474              info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
 475              info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
 476       assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
 477              info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
 478              info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
 479       assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
 480              info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
 481              info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
 482       assert(info->view->swizzle.r != info->view->swizzle.g);
 483       assert(info->view->swizzle.r != info->view->swizzle.b);
 484       assert(info->view->swizzle.g != info->view->swizzle.b);
 485
 486       /* From the Sky Lake PRM Vol. 2d,
 487        * RENDER_SURFACE_STATE::Shader Channel Select Alpha
 488        *
 489        *    "For Render Target, this field MUST be programmed to
 490        *    value = SCS_ALPHA."
 491        */
 492       assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
 493    }
 494    s.ShaderChannelSelectRed = info->view->swizzle.r;
 495    s.ShaderChannelSelectGreen = info->view->swizzle.g;
 496    s.ShaderChannelSelectBlue = info->view->swizzle.b;
 497    s.ShaderChannelSelectAlpha = info->view->swizzle.a;
 498 #endif
 499
 500    s.SurfaceBaseAddress = info->address;
 501
 502 #if GEN_GEN >= 6
 503    s.MOCS = info->mocs;
 504 #endif
 505
 506 #if GEN_GEN > 4 || GEN_IS_G4X
 507    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 508       /* There are fairly strict rules about when the offsets can be used.
 509        * These are mostly taken from the Sky Lake PRM documentation for
 510        * RENDER_SURFACE_STATE.
 511        */
 512       assert(info->surf->tiling != ISL_TILING_LINEAR);
 513       assert(info->surf->dim == ISL_SURF_DIM_2D);
 514       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 515       assert(info->surf->levels == 1);
 516       assert(info->surf->logical_level0_px.array_len == 1);
 517       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 518
 519       if (GEN_GEN >= 8) {
 520          /* Broadwell added more rules. */
 521          assert(info->surf->samples == 1);
 522          if (isl_format_get_layout(info->view->format)->bpb == 8)
 523             assert(info->x_offset_sa % 16 == 0);
 524          if (isl_format_get_layout(info->view->format)->bpb == 16)
 525             assert(info->x_offset_sa % 8 == 0);
 526       }
 527
 528 #if GEN_GEN >= 7
 529       s.SurfaceArray = false;
 530 #endif
 531    }
 532
 533    const unsigned x_div = 4;
 534    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 535    assert(info->x_offset_sa % x_div == 0);
 536    assert(info->y_offset_sa % y_div == 0);
 537    s.XOffset = info->x_offset_sa / x_div;
 538    s.YOffset = info->y_offset_sa / y_div;
 539 #else
 540    assert(info->x_offset_sa == 0);
 541    assert(info->y_offset_sa == 0);
 542 #endif
 543
 544 #if GEN_GEN >= 7
 545    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 546       /* The docs don't appear to say anything whatsoever about compression
 547        * and the data port.  Testing seems to indicate that the data port
 548        * completely ignores the AuxiliarySurfaceMode field.
 549        */
 550       assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 551
 552       struct isl_tile_info tile_info;
 553       isl_surf_get_tile_info(info->aux_surf, &tile_info);
 554       uint32_t pitch_in_tiles =
 555          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 556
 557       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 558       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 559
 560 #if GEN_GEN >= 8
 561       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 562       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 563        * doesn't expect our definition of the compression, it expects qpitch
 564        * in units of samples on the main surface.
 565        */
 566       s.AuxiliarySurfaceQPitch =
 567          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 568
 569       if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
 570          /* The number of samples must be 1 */
 571          assert(info->surf->samples == 1);
 572
 573          /* The dimension must not be 3D */
 574          assert(info->surf->dim != ISL_SURF_DIM_3D);
 575
 576          /* The format must be one of the following: */
 577          switch (info->view->format) {
 578          case ISL_FORMAT_R32_FLOAT:
 579          case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
 580          case ISL_FORMAT_R16_UNORM:
 581             break;
 582          default:
 583             assert(!"Incompatible HiZ Sampling format");
 584             break;
 585          }
 586       }
 587
 588       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 589 #else
 590       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 591              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 592       s.MCSEnable = true;
 593 #endif
 594    }
 595 #endif
 596
 597 #if GEN_GEN >= 8
 598    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 599     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 600     *
 601     *    This bit must be set for the following surface types: BC2_UNORM
 602     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 603     */
 604    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 605       switch (info->view->format) {
 606       case ISL_FORMAT_BC2_UNORM:
 607       case ISL_FORMAT_BC3_UNORM:
 608       case ISL_FORMAT_BC5_UNORM:
 609       case ISL_FORMAT_BC5_SNORM:
 610       case ISL_FORMAT_BC7_UNORM:
 611          s.SamplerL2BypassModeDisable = true;
 612          break;
 613       default:
 614          /* From the SKL PRM, Programming Note under Sampler Output Channel
 615           * Mapping:
 616           *
 617           *    If a surface has an associated HiZ Auxilliary surface, the
 618           *    Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
 619           *    must be set.
 620           */
 621          if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
 622             s.SamplerL2BypassModeDisable = true;
 623          break;
 624       }
 625    }
 626 #endif
 627
 628    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 629 #if GEN_GEN >= 9
 630       s.RedClearColor = info->clear_color.u32[0];
 631       s.GreenClearColor = info->clear_color.u32[1];
 632       s.BlueClearColor = info->clear_color.u32[2];
 633       s.AlphaClearColor = info->clear_color.u32[3];
 634 #elif GEN_GEN >= 7
 635       /* Prior to Sky Lake, we only have one bit for the clear color which
 636        * gives us 0 or 1 in whatever the surface's format happens to be.
 637        */
 638       if (isl_format_has_int_channel(info->view->format)) {
 639          for (unsigned i = 0; i < 4; i++) {
 640             assert(info->clear_color.u32[i] == 0 ||
 641                    info->clear_color.u32[i] == 1);
 642          }
 643          s.RedClearColor = info->clear_color.u32[0] != 0;
 644          s.GreenClearColor = info->clear_color.u32[1] != 0;
 645          s.BlueClearColor = info->clear_color.u32[2] != 0;
 646          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 647       } else {
 648          for (unsigned i = 0; i < 4; i++) {
 649             assert(info->clear_color.f32[i] == 0.0f ||
 650                    info->clear_color.f32[i] == 1.0f);
 651          }
 652          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 653          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 654          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 655          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 656       }
 657 #endif
 658    }
 659
 660    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 661 }
 662
 663 void
 664 isl_genX(buffer_fill_state_s)(void *state,
 665                               const struct isl_buffer_fill_state_info *restrict info)
 666 {
 667    uint32_t num_elements = info->size / info->stride;
 668
 669    if (GEN_GEN >= 7) {
 670       /* From the IVB PRM, SURFACE_STATE::Height,
 671        *
 672        *    For typed buffer and structured buffer surfaces, the number
 673        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 674        *    surfaces, the number of entries in the buffer is the number of bytes
 675        *    which can range from 1 to 2^30.
 676        */
 677       if (info->format == ISL_FORMAT_RAW) {
 678          assert(num_elements <= (1ull << 30));
 679          assert(num_elements > 0);
 680       } else {
 681          assert(num_elements <= (1ull << 27));
 682       }
 683    } else {
 684       assert(num_elements <= (1ull << 27));
 685    }
 686
 687    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 688
 689    s.SurfaceType = SURFTYPE_BUFFER;
 690    s.SurfaceFormat = info->format;
 691
 692 #if GEN_GEN >= 6
 693    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 694 #if GEN_GEN >= 7
 695    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 696    s.SurfaceArray = false;
 697 #endif
 698 #endif
 699
 700 #if GEN_GEN >= 7
 701    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 702    s.Width = (num_elements - 1) & 0x7f;
 703    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 704 #else
 705    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 706    s.Width = (num_elements - 1) & 0x7f;
 707    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 708 #endif
 709
 710    s.SurfacePitch = info->stride - 1;
 711
 712 #if GEN_GEN >= 6
 713    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 714 #endif
 715
 716 #if (GEN_GEN >= 8)
 717    s.TileMode = LINEAR;
 718 #else
 719    s.TiledSurface = false;
 720 #endif
 721
 722 #if (GEN_GEN >= 8)
 723    s.RenderCacheReadWriteMode = WriteOnlyCache;
 724 #else
 725    s.RenderCacheReadWriteMode = 0;
 726 #endif
 727
 728    s.SurfaceBaseAddress = info->address;
 729 #if GEN_GEN >= 6
 730    s.MOCS = info->mocs;
 731 #endif
 732
 733 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 734    s.ShaderChannelSelectRed = SCS_RED;
 735    s.ShaderChannelSelectGreen = SCS_GREEN;
 736    s.ShaderChannelSelectBlue = SCS_BLUE;
 737    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 738 #endif
 739
 740    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 741 }