src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50
  51 static const uint8_t isl_to_gen_valign[] = {
  52     [4] = VALIGN4,
  53     [8] = VALIGN8,
  54     [16] = VALIGN16,
  55 };
  56 #else
  57 static const uint8_t isl_to_gen_halign[] = {
  58     [4] = HALIGN_4,
  59     [8] = HALIGN_8,
  60 };
  61
  62 static const uint8_t isl_to_gen_valign[] = {
  63     [2] = VALIGN_2,
  64     [4] = VALIGN_4,
  65 };
  66 #endif
  67
  68 #if GEN_GEN >= 8
  69 static const uint8_t isl_to_gen_tiling[] = {
  70    [ISL_TILING_LINEAR]  = LINEAR,
  71    [ISL_TILING_X]       = XMAJOR,
  72    [ISL_TILING_Y0]      = YMAJOR,
  73    [ISL_TILING_Yf]      = YMAJOR,
  74    [ISL_TILING_Ys]      = YMAJOR,
  75    [ISL_TILING_W]       = WMAJOR,
  76 };
  77 #endif
  78
  79 static const uint32_t isl_to_gen_multisample_layout[] = {
  80    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  81    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  82    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  83 };
  84
  85 static uint8_t
  86 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
  87 {
  88    switch (dim) {
  89    default:
  90       unreachable("bad isl_surf_dim");
  91    case ISL_SURF_DIM_1D:
  92       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
  93       return SURFTYPE_1D;
  94    case ISL_SURF_DIM_2D:
  95       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
  96          /* Storage images are always plain 2-D, not cube */
  97          return SURFTYPE_2D;
  98       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
  99          return SURFTYPE_CUBE;
 100       } else {
 101          return SURFTYPE_2D;
 102       }
 103    case ISL_SURF_DIM_3D:
 104       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 105       return SURFTYPE_3D;
 106    }
 107 }
 108
 109 /**
 110  * Get the values to pack into RENDER_SUFFACE_STATE.SurfaceHorizontalAlignment
 111  * and SurfaceVerticalAlignment.
 112  */
 113 static void
 114 get_halign_valign(const struct isl_surf *surf,
 115                   uint32_t *halign, uint32_t *valign)
 116 {
 117    if (GEN_GEN >= 9) {
 118       if (isl_tiling_is_std_y(surf->tiling) ||
 119           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 120          /* The hardware ignores the alignment values. Anyway, the surface's
 121           * true alignment is likely outside the enum range of HALIGN* and
 122           * VALIGN*.
 123           */
 124          *halign = 0;
 125          *valign = 0;
 126       } else {
 127          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 128           * of surface elements (not pixels nor samples). For compressed formats,
 129           * a "surface element" is defined as a compression block.  For example,
 130           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 131           * format (ETC2 has a block height of 4), then the vertical alignment is
 132           * 4 compression blocks or, equivalently, 16 pixels.
 133           */
 134          struct isl_extent3d image_align_el
 135             = isl_surf_get_image_alignment_el(surf);
 136
 137          *halign = isl_to_gen_halign[image_align_el.width];
 138          *valign = isl_to_gen_valign[image_align_el.height];
 139       }
 140    } else {
 141       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 142        * units of surface samples.  For example, if SurfaceVerticalAlignment
 143        * is VALIGN_4 and the surface is singlesampled, then for any surface
 144        * format (compressed or not) the vertical alignment is
 145        * 4 pixels.
 146        */
 147       struct isl_extent3d image_align_sa
 148          = isl_surf_get_image_alignment_sa(surf);
 149
 150       *halign = isl_to_gen_halign[image_align_sa.width];
 151       *valign = isl_to_gen_valign[image_align_sa.height];
 152    }
 153 }
 154
 155 #if GEN_GEN >= 8
 156 static uint32_t
 157 get_qpitch(const struct isl_surf *surf)
 158 {
 159    switch (surf->dim) {
 160    default:
 161       unreachable("Bad isl_surf_dim");
 162    case ISL_SURF_DIM_1D:
 163       if (GEN_GEN >= 9) {
 164          /* QPitch is usually expressed as rows of surface elements (where
 165           * a surface element is an compression block or a single surface
 166           * sample). Skylake 1D is an outlier.
 167           *
 168           * From the Skylake BSpec >> Memory Views >> Common Surface
 169           * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 170           *
 171           *    Surface QPitch specifies the distance in pixels between array
 172           *    slices.
 173           */
 174          return isl_surf_get_array_pitch_el(surf);
 175       } else {
 176          return isl_surf_get_array_pitch_el_rows(surf);
 177       }
 178    case ISL_SURF_DIM_2D:
 179    case ISL_SURF_DIM_3D:
 180       if (GEN_GEN >= 9) {
 181          return isl_surf_get_array_pitch_el_rows(surf);
 182       } else {
 183          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 184           *
 185           *    "This field must be set to an integer multiple of the Surface
 186           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 187           *    ETC*, and EAC* Surface Formats), this field is in units of
 188           *    rows in the uncompressed surface, and must be set to an
 189           *    integer multiple of the vertical alignment parameter "j"
 190           *    defined in the Common Surface Formats section."
 191           */
 192          return isl_surf_get_array_pitch_sa_rows(surf);
 193       }
 194    }
 195 }
 196 #endif /* GEN_GEN >= 8 */
 197
 198 void
 199 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 200                             const struct isl_surf_fill_state_info *restrict info)
 201 {
 202    uint32_t halign, valign;
 203    get_halign_valign(info->surf, &halign, &valign);
 204
 205    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 206
 207    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 208
 209    if (info->view->usage & ISL_SURF_USAGE_STORAGE_BIT) {
 210       s.SurfaceFormat =
 211          isl_lower_storage_image_format(dev->info, info->view->format);
 212    } else {
 213       s.SurfaceFormat = info->view->format;
 214    }
 215
 216    s.SurfaceArray = info->surf->phys_level0_sa.array_len > 1;
 217    s.SurfaceVerticalAlignment = valign;
 218    s.SurfaceHorizontalAlignment = halign;
 219
 220 #if GEN_GEN >= 8
 221    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 222 #else
 223    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 224    s.TileWalk = info->surf->tiling == ISL_TILING_X ? TILEWALK_XMAJOR :
 225                                                      TILEWALK_YMAJOR;
 226 #endif
 227
 228 #if (GEN_GEN == 7)
 229    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 230                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 231 #endif
 232
 233 #if GEN_GEN >= 8
 234    s.SamplerL2BypassModeDisable = true;
 235 #endif
 236
 237 #if GEN_GEN >= 8
 238    s.RenderCacheReadWriteMode = WriteOnlyCache;
 239 #else
 240    s.RenderCacheReadWriteMode = 0;
 241 #endif
 242
 243 #if GEN_GEN >= 8
 244    s.CubeFaceEnablePositiveZ = 1;
 245    s.CubeFaceEnableNegativeZ = 1;
 246    s.CubeFaceEnablePositiveY = 1;
 247    s.CubeFaceEnableNegativeY = 1;
 248    s.CubeFaceEnablePositiveX = 1;
 249    s.CubeFaceEnableNegativeX = 1;
 250 #else
 251    s.CubeFaceEnables = 0x3f;
 252 #endif
 253
 254 #if GEN_GEN >= 8
 255    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 256 #endif
 257
 258    s.Width = info->surf->logical_level0_px.width - 1;
 259    s.Height = info->surf->logical_level0_px.height - 1;
 260    s.Depth = 0; /* TEMPLATE */
 261
 262    s.RenderTargetViewExtent = 0; /* TEMPLATE */
 263    s.MinimumArrayElement = 0; /* TEMPLATE */
 264
 265    s.MultisampledSurfaceStorageFormat =
 266       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 267    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 268
 269    s.MIPCountLOD = 0; /* TEMPLATE */
 270    s.SurfaceMinLOD = 0; /* TEMPLATE */
 271
 272 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 273    s.ShaderChannelSelectRed = info->view->channel_select[0];
 274    s.ShaderChannelSelectGreen = info->view->channel_select[1];
 275    s.ShaderChannelSelectBlue = info->view->channel_select[2];
 276    s.ShaderChannelSelectAlpha = info->view->channel_select[3];
 277 #endif
 278
 279    s.SurfaceBaseAddress = info->address;
 280    s.MOCS = info->mocs;
 281
 282 #if GEN_GEN >= 8
 283    s.AuxiliarySurfaceMode = AUX_NONE;
 284 #else
 285    s.MCSEnable = false;
 286 #endif
 287
 288    if (info->surf->tiling == ISL_TILING_W) {
 289       /* From the Broadwell PRM documentation for this field:
 290        *
 291        *    "If the surface is a stencil buffer (and thus has Tile Mode set
 292        *    to TILEMODE_WMAJOR), the pitch must be set to 2x the value
 293        *    computed based on width, as the stencil buffer is stored with
 294        *    two rows interleaved."
 295        */
 296       s.SurfacePitch = info->surf->row_pitch * 2 - 1;
 297    } else {
 298       s.SurfacePitch = info->surf->row_pitch - 1;
 299    }
 300
 301    switch (s.SurfaceType) {
 302    case SURFTYPE_1D:
 303    case SURFTYPE_2D:
 304       s.MinimumArrayElement = info->view->base_array_layer;
 305
 306       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 307        *
 308        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 309        *    by one for each increase from zero of Minimum Array Element. For
 310        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 311        *    the range of this field is reduced to [0,1023].
 312        *
 313        * In other words, 'Depth' is the number of array layers.
 314        */
 315       s.Depth = info->view->array_len - 1;
 316
 317       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 318        *
 319        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 320        *    This field must be set to the same value as the Depth field.
 321        */
 322       s.RenderTargetViewExtent = s.Depth;
 323       break;
 324    case SURFTYPE_CUBE:
 325       s.MinimumArrayElement = info->view->base_array_layer;
 326       /* Same as SURFTYPE_2D, but divided by 6 */
 327       s.Depth = info->view->array_len / 6 - 1;
 328       s.RenderTargetViewExtent = s.Depth;
 329       break;
 330    case SURFTYPE_3D:
 331       s.MinimumArrayElement = info->view->base_array_layer;
 332
 333       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 334        *
 335        *    If the volume texture is MIP-mapped, this field specifies the
 336        *    depth of the base MIP level.
 337        */
 338       s.Depth = info->surf->logical_level0_px.depth - 1;
 339
 340       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 341        *
 342        *    For Render Target and Typed Dataport 3D Surfaces: This field
 343        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 344        *    the LOD currently being rendered to.
 345        */
 346       s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 347                                             info->view->base_level) - 1;
 348       break;
 349    default:
 350       unreachable("bad SurfaceType");
 351    }
 352
 353    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 354       /* For render target surfaces, the hardware interprets field
 355        * MIPCount/LOD as LOD. The Broadwell PRM says:
 356        *
 357        *    MIPCountLOD defines the LOD that will be rendered into.
 358        *    SurfaceMinLOD is ignored.
 359        */
 360       s.MIPCountLOD = info->view->base_level;
 361       s.SurfaceMinLOD = 0;
 362    } else {
 363       /* For non render target surfaces, the hardware interprets field
 364        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 365        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 366        */
 367       s.SurfaceMinLOD = info->view->base_level;
 368       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 369    }
 370
 371 #if GEN_GEN >= 8
 372    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 373     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 374     *
 375     *    This bit must be set for the following surface types: BC2_UNORM
 376     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 377     */
 378    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 379       switch (info->view->format) {
 380       case ISL_FORMAT_BC2_UNORM:
 381       case ISL_FORMAT_BC3_UNORM:
 382       case ISL_FORMAT_BC5_UNORM:
 383       case ISL_FORMAT_BC5_SNORM:
 384       case ISL_FORMAT_BC7_UNORM:
 385          s.SamplerL2BypassModeDisable = true;
 386          break;
 387       default:
 388          break;
 389       }
 390    }
 391 #endif
 392
 393    if (GEN_GEN <= 8) {
 394       /* Prior to Sky Lake, we only have one bit for the clear color which
 395        * gives us 0 or 1 in whatever the surface's format happens to be.
 396        */
 397       if (isl_format_has_int_channel(info->view->format)) {
 398          for (unsigned i = 0; i < 4; i++) {
 399             assert(info->clear_color.u32[i] == 0 ||
 400                    info->clear_color.u32[i] == 1);
 401          }
 402       } else {
 403          for (unsigned i = 0; i < 4; i++) {
 404             assert(info->clear_color.f32[i] == 0.0f ||
 405                    info->clear_color.f32[i] == 1.0f);
 406          }
 407       }
 408       s.RedClearColor = info->clear_color.u32[0] != 0;
 409       s.GreenClearColor = info->clear_color.u32[1] != 0;
 410       s.BlueClearColor = info->clear_color.u32[2] != 0;
 411       s.AlphaClearColor = info->clear_color.u32[3] != 0;
 412    } else {
 413       s.RedClearColor = info->clear_color.u32[0];
 414       s.GreenClearColor = info->clear_color.u32[1];
 415       s.BlueClearColor = info->clear_color.u32[2];
 416       s.AlphaClearColor = info->clear_color.u32[3];
 417    }
 418
 419    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 420 }
 421
 422 void
 423 isl_genX(buffer_fill_state_s)(void *state,
 424                               const struct isl_buffer_fill_state_info *restrict info)
 425 {
 426    uint32_t num_elements = info->size / info->stride;
 427
 428    struct GENX(RENDER_SURFACE_STATE) surface_state = {
 429       .SurfaceType = SURFTYPE_BUFFER,
 430       .SurfaceArray = false,
 431       .SurfaceFormat = info->format,
 432       .SurfaceVerticalAlignment = isl_to_gen_valign[4],
 433       .SurfaceHorizontalAlignment = isl_to_gen_halign[4],
 434       .Height = ((num_elements - 1) >> 7) & 0x3fff,
 435       .Width = (num_elements - 1) & 0x7f,
 436       .Depth = ((num_elements - 1) >> 21) & 0x3f,
 437       .SurfacePitch = info->stride - 1,
 438       .NumberofMultisamples = MULTISAMPLECOUNT_1,
 439
 440 #if (GEN_GEN >= 8)
 441       .TileMode = LINEAR,
 442 #else
 443       .TiledSurface = false,
 444 #endif
 445
 446 #if (GEN_GEN >= 8)
 447       .SamplerL2BypassModeDisable = true,
 448       .RenderCacheReadWriteMode = WriteOnlyCache,
 449 #else
 450       .RenderCacheReadWriteMode = 0,
 451 #endif
 452
 453       .MOCS = info->mocs,
 454
 455 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 456       .ShaderChannelSelectRed = SCS_RED,
 457       .ShaderChannelSelectGreen = SCS_GREEN,
 458       .ShaderChannelSelectBlue = SCS_BLUE,
 459       .ShaderChannelSelectAlpha = SCS_ALPHA,
 460 #endif
 461       .SurfaceBaseAddress = info->address,
 462    };
 463
 464    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state);
 465 }