src/intel/isl/isl_surface_state.c

   1 /*
   2  * Copyright 2016 Intel Corporation
   3  *
   4  *  Permission is hereby granted, free of charge, to any person obtaining a
   5  *  copy of this software and associated documentation files (the "Software"),
   6  *  to deal in the Software without restriction, including without limitation
   7  *  the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  *  and/or sell copies of the Software, and to permit persons to whom the
   9  *  Software is furnished to do so, subject to the following conditions:
  10  *
  11  *  The above copyright notice and this permission notice (including the next
  12  *  paragraph) shall be included in all copies or substantial portions of the
  13  *  Software.
  14  *
  15  *  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  *  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  *  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  *  THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  *  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  *  FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  *  IN THE SOFTWARE.
  22  */
  23
  24 #include <stdint.h>
  25
  26 #define __gen_address_type uint64_t
  27 #define __gen_user_data void
  28
  29 static inline uint64_t
  30 __gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
  31 {
  32    return addr + delta;
  33 }
  34
  35 #include "genxml/gen_macros.h"
  36 #include "genxml/genX_pack.h"
  37
  38 #include "isl_priv.h"
  39
  40 #define __PASTE2(x, y) x ## y
  41 #define __PASTE(x, y) __PASTE2(x, y)
  42 #define isl_genX(x) __PASTE(isl_, genX(x))
  43
  44 #if GEN_GEN >= 8
  45 static const uint8_t isl_to_gen_halign[] = {
  46     [4] = HALIGN4,
  47     [8] = HALIGN8,
  48     [16] = HALIGN16,
  49 };
  50 #elif GEN_GEN >= 7
  51 static const uint8_t isl_to_gen_halign[] = {
  52     [4] = HALIGN_4,
  53     [8] = HALIGN_8,
  54 };
  55 #endif
  56
  57 #if GEN_GEN >= 8
  58 static const uint8_t isl_to_gen_valign[] = {
  59     [4] = VALIGN4,
  60     [8] = VALIGN8,
  61     [16] = VALIGN16,
  62 };
  63 #elif GEN_GEN >= 6
  64 static const uint8_t isl_to_gen_valign[] = {
  65     [2] = VALIGN_2,
  66     [4] = VALIGN_4,
  67 };
  68 #endif
  69
  70 #if GEN_GEN >= 8
  71 static const uint8_t isl_to_gen_tiling[] = {
  72    [ISL_TILING_LINEAR]  = LINEAR,
  73    [ISL_TILING_X]       = XMAJOR,
  74    [ISL_TILING_Y0]      = YMAJOR,
  75    [ISL_TILING_Yf]      = YMAJOR,
  76    [ISL_TILING_Ys]      = YMAJOR,
  77    [ISL_TILING_W]       = WMAJOR,
  78 };
  79 #endif
  80
  81 #if GEN_GEN >= 7
  82 static const uint32_t isl_to_gen_multisample_layout[] = {
  83    [ISL_MSAA_LAYOUT_NONE]           = MSFMT_MSS,
  84    [ISL_MSAA_LAYOUT_INTERLEAVED]    = MSFMT_DEPTH_STENCIL,
  85    [ISL_MSAA_LAYOUT_ARRAY]          = MSFMT_MSS,
  86 };
  87 #endif
  88
  89 #if GEN_GEN >= 9
  90 static const uint32_t isl_to_gen_aux_mode[] = {
  91    [ISL_AUX_USAGE_NONE] = AUX_NONE,
  92    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
  93    [ISL_AUX_USAGE_MCS] = AUX_CCS_D,
  94    [ISL_AUX_USAGE_CCS_D] = AUX_CCS_D,
  95    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
  96 };
  97 #elif GEN_GEN >= 8
  98 static const uint32_t isl_to_gen_aux_mode[] = {
  99    [ISL_AUX_USAGE_NONE] = AUX_NONE,
 100    [ISL_AUX_USAGE_HIZ] = AUX_HIZ,
 101    [ISL_AUX_USAGE_MCS] = AUX_MCS,
 102    [ISL_AUX_USAGE_CCS_D] = AUX_MCS,
 103 };
 104 #endif
 105
 106 static uint8_t
 107 get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
 108 {
 109    switch (dim) {
 110    default:
 111       unreachable("bad isl_surf_dim");
 112    case ISL_SURF_DIM_1D:
 113       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 114       return SURFTYPE_1D;
 115    case ISL_SURF_DIM_2D:
 116       if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
 117          /* Storage images are always plain 2-D, not cube */
 118          return SURFTYPE_2D;
 119       } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
 120          return SURFTYPE_CUBE;
 121       } else {
 122          return SURFTYPE_2D;
 123       }
 124    case ISL_SURF_DIM_3D:
 125       assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
 126       return SURFTYPE_3D;
 127    }
 128 }
 129
 130 /**
 131  * Get the horizontal and vertical alignment in the units expected by the
 132  * hardware.  Note that this does NOT give you the actual hardware enum values
 133  * but an index into the isl_to_gen_[hv]align arrays above.
 134  */
 135 static inline struct isl_extent3d
 136 get_image_alignment(const struct isl_surf *surf)
 137 {
 138    if (GEN_GEN >= 9) {
 139       if (isl_tiling_is_std_y(surf->tiling) ||
 140           surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 141          /* The hardware ignores the alignment values. Anyway, the surface's
 142           * true alignment is likely outside the enum range of HALIGN* and
 143           * VALIGN*.
 144           */
 145          return isl_extent3d(4, 4, 1);
 146       } else {
 147          /* In Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in units
 148           * of surface elements (not pixels nor samples). For compressed formats,
 149           * a "surface element" is defined as a compression block.  For example,
 150           * if SurfaceVerticalAlignment is VALIGN_4 and SurfaceFormat is an ETC2
 151           * format (ETC2 has a block height of 4), then the vertical alignment is
 152           * 4 compression blocks or, equivalently, 16 pixels.
 153           */
 154          return isl_surf_get_image_alignment_el(surf);
 155       }
 156    } else {
 157       /* Pre-Skylake, RENDER_SUFFACE_STATE.SurfaceVerticalAlignment is in
 158        * units of surface samples.  For example, if SurfaceVerticalAlignment
 159        * is VALIGN_4 and the surface is singlesampled, then for any surface
 160        * format (compressed or not) the vertical alignment is
 161        * 4 pixels.
 162        */
 163       return isl_surf_get_image_alignment_sa(surf);
 164    }
 165 }
 166
 167 #if GEN_GEN >= 8
 168 static uint32_t
 169 get_qpitch(const struct isl_surf *surf)
 170 {
 171    switch (surf->dim_layout) {
 172    default:
 173       unreachable("Bad isl_surf_dim");
 174    case ISL_DIM_LAYOUT_GEN4_2D:
 175    case ISL_DIM_LAYOUT_GEN4_3D:
 176       if (GEN_GEN >= 9) {
 177          return isl_surf_get_array_pitch_el_rows(surf);
 178       } else {
 179          /* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
 180           *
 181           *    "This field must be set to an integer multiple of the Surface
 182           *    Vertical Alignment. For compressed textures (BC*, FXT1,
 183           *    ETC*, and EAC* Surface Formats), this field is in units of
 184           *    rows in the uncompressed surface, and must be set to an
 185           *    integer multiple of the vertical alignment parameter "j"
 186           *    defined in the Common Surface Formats section."
 187           */
 188          return isl_surf_get_array_pitch_sa_rows(surf);
 189       }
 190    case ISL_DIM_LAYOUT_GEN9_1D:
 191       /* QPitch is usually expressed as rows of surface elements (where
 192        * a surface element is an compression block or a single surface
 193        * sample). Skylake 1D is an outlier.
 194        *
 195        * From the Skylake BSpec >> Memory Views >> Common Surface
 196        * Formats >> Surface Layout and Tiling >> 1D Surfaces:
 197        *
 198        *    Surface QPitch specifies the distance in pixels between array
 199        *    slices.
 200        */
 201       return isl_surf_get_array_pitch_el(surf);
 202    }
 203 }
 204 #endif /* GEN_GEN >= 8 */
 205
 206 void
 207 isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 208                             const struct isl_surf_fill_state_info *restrict info)
 209 {
 210    struct GENX(RENDER_SURFACE_STATE) s = { 0 };
 211
 212    s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
 213
 214    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
 215       assert(isl_format_supports_rendering(dev->info, info->view->format));
 216    else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
 217       assert(isl_format_supports_sampling(dev->info, info->view->format));
 218    s.SurfaceFormat = info->view->format;
 219
 220 #if GEN_IS_HASWELL
 221    s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
 222 #endif
 223
 224    s.Width = info->surf->logical_level0_px.width - 1;
 225    s.Height = info->surf->logical_level0_px.height - 1;
 226
 227    /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1
 228     * (Surface Arrays For all surfaces other than separate stencil buffer):
 229     *
 230     * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value
 231     *  calculated in the equation above , for every other odd Surface Height
 232     *  starting from 1 i.e. 1,5,9,13"
 233     *
 234     * Since this Qpitch errata only impacts the sampler, we have to adjust the
 235     * input for the rendering surface to achieve the same qpitch. For the
 236     * affected heights, we increment the height by 1 for the rendering
 237     * surface.
 238     */
 239    if (GEN_GEN == 6 && (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) &&
 240        info->surf->samples > 1 &&
 241        (info->surf->logical_level0_px.height % 4) == 1)
 242       s.Height++;
 243
 244    switch (s.SurfaceType) {
 245    case SURFTYPE_1D:
 246    case SURFTYPE_2D:
 247       /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
 248        *
 249        *    "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
 250        *    must be set to zero if this surface is used with sampling engine
 251        *    messages."
 252        *
 253        * This restriction appears to exist only on Ivy Bridge.
 254        */
 255       if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
 256           (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
 257           info->surf->samples > 1)
 258          assert(info->view->base_array_layer == 0);
 259
 260       s.MinimumArrayElement = info->view->base_array_layer;
 261
 262       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 263        *
 264        *    For SURFTYPE_1D, 2D, and CUBE: The range of this field is reduced
 265        *    by one for each increase from zero of Minimum Array Element. For
 266        *    example, if Minimum Array Element is set to 1024 on a 2D surface,
 267        *    the range of this field is reduced to [0,1023].
 268        *
 269        * In other words, 'Depth' is the number of array layers.
 270        */
 271       s.Depth = info->view->array_len - 1;
 272
 273       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 274        *
 275        *    For Render Target and Typed Dataport 1D and 2D Surfaces:
 276        *    This field must be set to the same value as the Depth field.
 277        */
 278       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 279                                ISL_SURF_USAGE_STORAGE_BIT))
 280          s.RenderTargetViewExtent = s.Depth;
 281       break;
 282    case SURFTYPE_CUBE:
 283       s.MinimumArrayElement = info->view->base_array_layer;
 284       /* Same as SURFTYPE_2D, but divided by 6 */
 285       s.Depth = info->view->array_len / 6 - 1;
 286       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 287                                ISL_SURF_USAGE_STORAGE_BIT))
 288          s.RenderTargetViewExtent = s.Depth;
 289       break;
 290    case SURFTYPE_3D:
 291       s.MinimumArrayElement = info->view->base_array_layer;
 292
 293       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
 294        *
 295        *    If the volume texture is MIP-mapped, this field specifies the
 296        *    depth of the base MIP level.
 297        */
 298       s.Depth = info->surf->logical_level0_px.depth - 1;
 299
 300       /* From the Broadwell PRM >> RENDER_SURFACE_STATE::RenderTargetViewExtent:
 301        *
 302        *    For Render Target and Typed Dataport 3D Surfaces: This field
 303        *    indicates the extent of the accessible 'R' coordinates minus 1 on
 304        *    the LOD currently being rendered to.
 305        *
 306        * The docs specify that this only matters for render targets and
 307        * surfaces used with typed dataport messages.  Prior to Ivy Bridge, the
 308        * Depth field has more bits than RenderTargetViewExtent so we can have
 309        * textures with more levels than we can render to.  In order to prevent
 310        * assert-failures in the packing function below, we only set the field
 311        * when it's actually going to be used by the hardware.
 312        */
 313       if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
 314                                ISL_SURF_USAGE_STORAGE_BIT)) {
 315          s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
 316                                                info->view->base_level) - 1;
 317       }
 318       break;
 319    default:
 320       unreachable("bad SurfaceType");
 321    }
 322
 323 #if GEN_GEN >= 7
 324    s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
 325 #endif
 326
 327    if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
 328       /* For render target surfaces, the hardware interprets field
 329        * MIPCount/LOD as LOD. The Broadwell PRM says:
 330        *
 331        *    MIPCountLOD defines the LOD that will be rendered into.
 332        *    SurfaceMinLOD is ignored.
 333        */
 334       s.MIPCountLOD = info->view->base_level;
 335       s.SurfaceMinLOD = 0;
 336    } else {
 337       /* For non render target surfaces, the hardware interprets field
 338        * MIPCount/LOD as MIPCount.  The range of levels accessible by the
 339        * sampler engine is [SurfaceMinLOD, SurfaceMinLOD + MIPCountLOD].
 340        */
 341       s.SurfaceMinLOD = info->view->base_level;
 342       s.MIPCountLOD = MAX(info->view->levels, 1) - 1;
 343    }
 344
 345 #if GEN_GEN >= 9
 346    /* We don't use miptails yet.  The PRM recommends that you set "Mip Tail
 347     * Start LOD" to 15 to prevent the hardware from trying to use them.
 348     */
 349    s.TiledResourceMode = NONE;
 350    s.MipTailStartLOD = 15;
 351 #endif
 352
 353 #if GEN_GEN >= 6
 354    const struct isl_extent3d image_align = get_image_alignment(info->surf);
 355    s.SurfaceVerticalAlignment = isl_to_gen_valign[image_align.height];
 356 #if GEN_GEN >= 7
 357    s.SurfaceHorizontalAlignment = isl_to_gen_halign[image_align.width];
 358 #endif
 359 #endif
 360
 361    if (info->surf->dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
 362       /* For gen9 1-D textures, surface pitch is ignored */
 363       s.SurfacePitch = 0;
 364    } else {
 365       s.SurfacePitch = info->surf->row_pitch - 1;
 366    }
 367
 368 #if GEN_GEN >= 8
 369    s.SurfaceQPitch = get_qpitch(info->surf) >> 2;
 370 #elif GEN_GEN == 7
 371    s.SurfaceArraySpacing = info->surf->array_pitch_span ==
 372                            ISL_ARRAY_PITCH_SPAN_COMPACT;
 373 #endif
 374
 375 #if GEN_GEN >= 8
 376    s.TileMode = isl_to_gen_tiling[info->surf->tiling];
 377 #else
 378    s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
 379    s.TileWalk = info->surf->tiling == ISL_TILING_Y0 ? TILEWALK_YMAJOR :
 380                                                       TILEWALK_XMAJOR,
 381 #endif
 382
 383 #if GEN_GEN >= 8
 384    s.RenderCacheReadWriteMode = WriteOnlyCache;
 385 #else
 386    s.RenderCacheReadWriteMode = 0;
 387 #endif
 388
 389    if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
 390 #if GEN_GEN >= 8
 391       s.CubeFaceEnablePositiveZ = 1;
 392       s.CubeFaceEnableNegativeZ = 1;
 393       s.CubeFaceEnablePositiveY = 1;
 394       s.CubeFaceEnableNegativeY = 1;
 395       s.CubeFaceEnablePositiveX = 1;
 396       s.CubeFaceEnableNegativeX = 1;
 397 #else
 398       s.CubeFaceEnables = 0x3f;
 399 #endif
 400    }
 401
 402 #if GEN_GEN >= 6
 403    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
 404 #if GEN_GEN >= 7
 405    s.MultisampledSurfaceStorageFormat =
 406       isl_to_gen_multisample_layout[info->surf->msaa_layout];
 407 #endif
 408 #endif
 409
 410 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 411    s.ShaderChannelSelectRed = info->view->channel_select[0];
 412    s.ShaderChannelSelectGreen = info->view->channel_select[1];
 413    s.ShaderChannelSelectBlue = info->view->channel_select[2];
 414    s.ShaderChannelSelectAlpha = info->view->channel_select[3];
 415 #endif
 416
 417    s.SurfaceBaseAddress = info->address;
 418
 419 #if GEN_GEN >= 6
 420    s.MOCS = info->mocs;
 421 #endif
 422
 423 #if GEN_GEN > 4 || GEN_IS_G4X
 424    if (info->x_offset_sa != 0 || info->y_offset_sa != 0) {
 425       /* There are fairly strict rules about when the offsets can be used.
 426        * These are mostly taken from the Sky Lake PRM documentation for
 427        * RENDER_SURFACE_STATE.
 428        */
 429       assert(info->surf->tiling != ISL_TILING_LINEAR);
 430       assert(info->surf->dim == ISL_SURF_DIM_2D);
 431       assert(isl_is_pow2(isl_format_get_layout(info->view->format)->bpb));
 432       assert(info->surf->levels == 1);
 433       assert(info->surf->logical_level0_px.array_len == 1);
 434       assert(info->aux_usage == ISL_AUX_USAGE_NONE);
 435
 436       if (GEN_GEN >= 8) {
 437          /* Broadwell added more rules. */
 438          assert(info->surf->samples == 1);
 439          if (isl_format_get_layout(info->view->format)->bpb == 8)
 440             assert(info->x_offset_sa % 16 == 0);
 441          if (isl_format_get_layout(info->view->format)->bpb == 16)
 442             assert(info->x_offset_sa % 8 == 0);
 443       }
 444
 445 #if GEN_GEN >= 7
 446       s.SurfaceArray = false;
 447 #endif
 448    }
 449
 450    const unsigned x_div = 4;
 451    const unsigned y_div = GEN_GEN >= 8 ? 4 : 2;
 452    assert(info->x_offset_sa % x_div == 0);
 453    assert(info->y_offset_sa % y_div == 0);
 454    s.XOffset = info->x_offset_sa / x_div;
 455    s.YOffset = info->y_offset_sa / y_div;
 456 #else
 457    assert(info->x_offset_sa == 0);
 458    assert(info->y_offset_sa == 0);
 459 #endif
 460
 461 #if GEN_GEN >= 7
 462    if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
 463       struct isl_tile_info tile_info;
 464       isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
 465       uint32_t pitch_in_tiles =
 466          info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
 467
 468 #if GEN_GEN >= 8
 469       assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
 470       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
 471       /* Auxiliary surfaces in ISL have compressed formats but the hardware
 472        * doesn't expect our definition of the compression, it expects qpitch
 473        * in units of samples on the main surface.
 474        */
 475       s.AuxiliarySurfaceQPitch =
 476          isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
 477       s.AuxiliarySurfaceBaseAddress = info->aux_address;
 478       s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
 479 #else
 480       assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
 481              info->aux_usage == ISL_AUX_USAGE_CCS_D);
 482       s.MCSBaseAddress = info->aux_address,
 483       s.MCSSurfacePitch = pitch_in_tiles - 1;
 484       s.MCSEnable = true;
 485 #endif
 486    }
 487 #endif
 488
 489 #if GEN_GEN >= 8
 490    /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
 491     * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
 492     *
 493     *    This bit must be set for the following surface types: BC2_UNORM
 494     *    BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
 495     */
 496    if (GEN_GEN >= 9 || dev->info->is_cherryview) {
 497       switch (info->view->format) {
 498       case ISL_FORMAT_BC2_UNORM:
 499       case ISL_FORMAT_BC3_UNORM:
 500       case ISL_FORMAT_BC5_UNORM:
 501       case ISL_FORMAT_BC5_SNORM:
 502       case ISL_FORMAT_BC7_UNORM:
 503          s.SamplerL2BypassModeDisable = true;
 504          break;
 505       default:
 506          break;
 507       }
 508    }
 509 #endif
 510
 511    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
 512 #if GEN_GEN >= 9
 513       s.RedClearColor = info->clear_color.u32[0];
 514       s.GreenClearColor = info->clear_color.u32[1];
 515       s.BlueClearColor = info->clear_color.u32[2];
 516       s.AlphaClearColor = info->clear_color.u32[3];
 517 #elif GEN_GEN >= 7
 518       /* Prior to Sky Lake, we only have one bit for the clear color which
 519        * gives us 0 or 1 in whatever the surface's format happens to be.
 520        */
 521       if (isl_format_has_int_channel(info->view->format)) {
 522          for (unsigned i = 0; i < 4; i++) {
 523             assert(info->clear_color.u32[i] == 0 ||
 524                    info->clear_color.u32[i] == 1);
 525          }
 526          s.RedClearColor = info->clear_color.u32[0] != 0;
 527          s.GreenClearColor = info->clear_color.u32[1] != 0;
 528          s.BlueClearColor = info->clear_color.u32[2] != 0;
 529          s.AlphaClearColor = info->clear_color.u32[3] != 0;
 530       } else {
 531          for (unsigned i = 0; i < 4; i++) {
 532             assert(info->clear_color.f32[i] == 0.0f ||
 533                    info->clear_color.f32[i] == 1.0f);
 534          }
 535          s.RedClearColor = info->clear_color.f32[0] != 0.0f;
 536          s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
 537          s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
 538          s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
 539       }
 540 #endif
 541    }
 542
 543    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 544 }
 545
 546 void
 547 isl_genX(buffer_fill_state_s)(void *state,
 548                               const struct isl_buffer_fill_state_info *restrict info)
 549 {
 550    uint32_t num_elements = info->size / info->stride;
 551
 552    if (GEN_GEN >= 7) {
 553       /* From the IVB PRM, SURFACE_STATE::Height,
 554        *
 555        *    For typed buffer and structured buffer surfaces, the number
 556        *    of entries in the buffer ranges from 1 to 2^27. For raw buffer
 557        *    surfaces, the number of entries in the buffer is the number of bytes
 558        *    which can range from 1 to 2^30.
 559        */
 560       if (info->format == ISL_FORMAT_RAW) {
 561          assert(num_elements <= (1ull << 30));
 562          assert((num_elements & 3) == 0);
 563       } else {
 564          assert(num_elements <= (1ull << 27));
 565       }
 566    } else {
 567       assert(num_elements <= (1ull << 27));
 568    }
 569
 570    struct GENX(RENDER_SURFACE_STATE) s = { 0, };
 571
 572    s.SurfaceType = SURFTYPE_BUFFER;
 573    s.SurfaceFormat = info->format;
 574
 575 #if GEN_GEN >= 6
 576    s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
 577 #if GEN_GEN >= 7
 578    s.SurfaceHorizontalAlignment = isl_to_gen_halign[4];
 579    s.SurfaceArray = false;
 580 #endif
 581 #endif
 582
 583 #if GEN_GEN >= 7
 584    s.Height = ((num_elements - 1) >> 7) & 0x3fff;
 585    s.Width = (num_elements - 1) & 0x7f;
 586    s.Depth = ((num_elements - 1) >> 21) & 0x3ff;
 587 #else
 588    s.Height = ((num_elements - 1) >> 7) & 0x1fff;
 589    s.Width = (num_elements - 1) & 0x7f;
 590    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 591 #endif
 592
 593    s.SurfacePitch = info->stride - 1;
 594
 595 #if GEN_GEN >= 6
 596    s.NumberofMultisamples = MULTISAMPLECOUNT_1;
 597 #endif
 598
 599 #if (GEN_GEN >= 8)
 600    s.TileMode = LINEAR;
 601 #else
 602    s.TiledSurface = false;
 603 #endif
 604
 605 #if (GEN_GEN >= 8)
 606    s.RenderCacheReadWriteMode = WriteOnlyCache;
 607 #else
 608    s.RenderCacheReadWriteMode = 0;
 609 #endif
 610
 611    s.SurfaceBaseAddress = info->address;
 612 #if GEN_GEN >= 6
 613    s.MOCS = info->mocs;
 614 #endif
 615
 616 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
 617    s.ShaderChannelSelectRed = SCS_RED;
 618    s.ShaderChannelSelectGreen = SCS_GREEN;
 619    s.ShaderChannelSelectBlue = SCS_BLUE;
 620    s.ShaderChannelSelectAlpha = SCS_ALPHA;
 621 #endif
 622
 623    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 624 }