2 * Copyright © 2018 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <sys/types.h>
32 #ifndef HAVE_DIRENT_D_TYPE
33 #include <limits.h> // PATH_MAX
36 #include <drm-uapi/i915_drm.h>
38 #include "common/gen_gem.h"
40 #include "dev/gen_debug.h"
41 #include "dev/gen_device_info.h"
43 #include "perf/gen_perf.h"
44 #include "perf/gen_perf_regs.h"
45 #include "perf/gen_perf_mdapi.h"
46 #include "perf/gen_perf_metrics.h"
47 #include "perf/gen_perf_private.h"
49 #include "util/bitscan.h"
50 #include "util/mesa-sha1.h"
51 #include "util/u_math.h"
53 #define FILE_DEBUG_FLAG DEBUG_PERFMON
55 #define OA_REPORT_INVALID_CTX_ID (0xffffffff)
58 is_dir_or_link(const struct dirent
*entry
, const char *parent_dir
)
60 #ifdef HAVE_DIRENT_D_TYPE
61 return entry
->d_type
== DT_DIR
|| entry
->d_type
== DT_LNK
;
64 char path
[PATH_MAX
+ 1];
65 snprintf(path
, sizeof(path
), "%s/%s", parent_dir
, entry
->d_name
);
67 return S_ISDIR(st
.st_mode
) || S_ISLNK(st
.st_mode
);
72 get_sysfs_dev_dir(struct gen_perf_config
*perf
, int fd
)
77 struct dirent
*drm_entry
;
80 perf
->sysfs_dev_dir
[0] = '\0';
83 DBG("Failed to stat DRM fd\n");
87 maj
= major(sb
.st_rdev
);
88 min
= minor(sb
.st_rdev
);
90 if (!S_ISCHR(sb
.st_mode
)) {
91 DBG("DRM fd is not a character device as expected\n");
95 len
= snprintf(perf
->sysfs_dev_dir
,
96 sizeof(perf
->sysfs_dev_dir
),
97 "/sys/dev/char/%d:%d/device/drm", maj
, min
);
98 if (len
< 0 || len
>= sizeof(perf
->sysfs_dev_dir
)) {
99 DBG("Failed to concatenate sysfs path to drm device\n");
103 drmdir
= opendir(perf
->sysfs_dev_dir
);
105 DBG("Failed to open %s: %m\n", perf
->sysfs_dev_dir
);
109 while ((drm_entry
= readdir(drmdir
))) {
110 if (is_dir_or_link(drm_entry
, perf
->sysfs_dev_dir
) &&
111 strncmp(drm_entry
->d_name
, "card", 4) == 0)
113 len
= snprintf(perf
->sysfs_dev_dir
,
114 sizeof(perf
->sysfs_dev_dir
),
115 "/sys/dev/char/%d:%d/device/drm/%s",
116 maj
, min
, drm_entry
->d_name
);
118 if (len
< 0 || len
>= sizeof(perf
->sysfs_dev_dir
))
127 DBG("Failed to find cardX directory under /sys/dev/char/%d:%d/device/drm\n",
134 read_file_uint64(const char *file
, uint64_t *val
)
142 while ((n
= read(fd
, buf
, sizeof (buf
) - 1)) < 0 &&
149 *val
= strtoull(buf
, NULL
, 0);
155 read_sysfs_drm_device_file_uint64(struct gen_perf_config
*perf
,
162 len
= snprintf(buf
, sizeof(buf
), "%s/%s", perf
->sysfs_dev_dir
, file
);
163 if (len
< 0 || len
>= sizeof(buf
)) {
164 DBG("Failed to concatenate sys filename to read u64 from\n");
168 return read_file_uint64(buf
, value
);
172 register_oa_config(struct gen_perf_config
*perf
,
173 const struct gen_device_info
*devinfo
,
174 const struct gen_perf_query_info
*query
,
177 struct gen_perf_query_info
*registered_query
=
178 gen_perf_append_query_info(perf
, 0);
180 *registered_query
= *query
;
181 registered_query
->oa_format
= devinfo
->gen
>= 8 ?
182 I915_OA_FORMAT_A32u40_A4u32_B8_C8
: I915_OA_FORMAT_A45_B8_C8
;
183 registered_query
->oa_metrics_set_id
= config_id
;
184 DBG("metric set registered: id = %" PRIu64
", guid = %s\n",
185 registered_query
->oa_metrics_set_id
, query
->guid
);
189 enumerate_sysfs_metrics(struct gen_perf_config
*perf
,
190 const struct gen_device_info
*devinfo
)
192 DIR *metricsdir
= NULL
;
193 struct dirent
*metric_entry
;
197 len
= snprintf(buf
, sizeof(buf
), "%s/metrics", perf
->sysfs_dev_dir
);
198 if (len
< 0 || len
>= sizeof(buf
)) {
199 DBG("Failed to concatenate path to sysfs metrics/ directory\n");
203 metricsdir
= opendir(buf
);
205 DBG("Failed to open %s: %m\n", buf
);
209 while ((metric_entry
= readdir(metricsdir
))) {
210 struct hash_entry
*entry
;
211 if (!is_dir_or_link(metric_entry
, buf
) ||
212 metric_entry
->d_name
[0] == '.')
215 DBG("metric set: %s\n", metric_entry
->d_name
);
216 entry
= _mesa_hash_table_search(perf
->oa_metrics_table
,
217 metric_entry
->d_name
);
220 if (!gen_perf_load_metric_id(perf
, metric_entry
->d_name
, &id
)) {
221 DBG("Failed to read metric set id from %s: %m", buf
);
225 register_oa_config(perf
, devinfo
,
226 (const struct gen_perf_query_info
*)entry
->data
, id
);
228 DBG("metric set not known by mesa (skipping)\n");
231 closedir(metricsdir
);
235 kernel_has_dynamic_config_support(struct gen_perf_config
*perf
, int fd
)
237 uint64_t invalid_config_id
= UINT64_MAX
;
239 return gen_ioctl(fd
, DRM_IOCTL_I915_PERF_REMOVE_CONFIG
,
240 &invalid_config_id
) < 0 && errno
== ENOENT
;
244 i915_query_items(struct gen_perf_config
*perf
, int fd
,
245 struct drm_i915_query_item
*items
, uint32_t n_items
)
247 struct drm_i915_query q
= {
248 .num_items
= n_items
,
249 .items_ptr
= to_user_pointer(items
),
251 return gen_ioctl(fd
, DRM_IOCTL_I915_QUERY
, &q
);
255 i915_query_perf_config_supported(struct gen_perf_config
*perf
, int fd
)
257 struct drm_i915_query_item item
= {
258 .query_id
= DRM_I915_QUERY_PERF_CONFIG
,
259 .flags
= DRM_I915_QUERY_PERF_CONFIG_LIST
,
262 return i915_query_items(perf
, fd
, &item
, 1) == 0 && item
.length
> 0;
266 i915_query_perf_config_data(struct gen_perf_config
*perf
,
267 int fd
, const char *guid
,
268 struct drm_i915_perf_oa_config
*config
)
271 struct drm_i915_query_perf_config query
;
272 struct drm_i915_perf_oa_config config
;
274 struct drm_i915_query_item item
= {
275 .query_id
= DRM_I915_QUERY_PERF_CONFIG
,
276 .flags
= DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
,
277 .data_ptr
= to_user_pointer(&item_data
),
278 .length
= sizeof(item_data
),
281 memset(&item_data
, 0, sizeof(item_data
));
282 memcpy(item_data
.query
.uuid
, guid
, sizeof(item_data
.query
.uuid
));
283 memcpy(&item_data
.config
, config
, sizeof(item_data
.config
));
285 if (!(i915_query_items(perf
, fd
, &item
, 1) == 0 && item
.length
> 0))
288 memcpy(config
, &item_data
.config
, sizeof(item_data
.config
));
294 gen_perf_load_metric_id(struct gen_perf_config
*perf_cfg
,
298 char config_path
[280];
300 snprintf(config_path
, sizeof(config_path
), "%s/metrics/%s/id",
301 perf_cfg
->sysfs_dev_dir
, guid
);
303 /* Don't recreate already loaded configs. */
304 return read_file_uint64(config_path
, metric_id
);
308 i915_add_config(struct gen_perf_config
*perf
, int fd
,
309 const struct gen_perf_registers
*config
,
312 struct drm_i915_perf_oa_config i915_config
= { 0, };
314 memcpy(i915_config
.uuid
, guid
, sizeof(i915_config
.uuid
));
316 i915_config
.n_mux_regs
= config
->n_mux_regs
;
317 i915_config
.mux_regs_ptr
= to_user_pointer(config
->mux_regs
);
319 i915_config
.n_boolean_regs
= config
->n_b_counter_regs
;
320 i915_config
.boolean_regs_ptr
= to_user_pointer(config
->b_counter_regs
);
322 i915_config
.n_flex_regs
= config
->n_flex_regs
;
323 i915_config
.flex_regs_ptr
= to_user_pointer(config
->flex_regs
);
325 int ret
= gen_ioctl(fd
, DRM_IOCTL_I915_PERF_ADD_CONFIG
, &i915_config
);
326 return ret
> 0 ? ret
: 0;
330 init_oa_configs(struct gen_perf_config
*perf
, int fd
,
331 const struct gen_device_info
*devinfo
)
333 hash_table_foreach(perf
->oa_metrics_table
, entry
) {
334 const struct gen_perf_query_info
*query
= entry
->data
;
337 if (gen_perf_load_metric_id(perf
, query
->guid
, &config_id
)) {
338 DBG("metric set: %s (already loaded)\n", query
->guid
);
339 register_oa_config(perf
, devinfo
, query
, config_id
);
343 int ret
= i915_add_config(perf
, fd
, &query
->config
, query
->guid
);
345 DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
346 query
->name
, query
->guid
, strerror(errno
));
350 register_oa_config(perf
, devinfo
, query
, ret
);
351 DBG("metric set: %s (added)\n", query
->guid
);
356 compute_topology_builtins(struct gen_perf_config
*perf
,
357 const struct gen_device_info
*devinfo
)
359 perf
->sys_vars
.slice_mask
= devinfo
->slice_masks
;
360 perf
->sys_vars
.n_eu_slices
= devinfo
->num_slices
;
362 for (int i
= 0; i
< sizeof(devinfo
->subslice_masks
[i
]); i
++) {
363 perf
->sys_vars
.n_eu_sub_slices
+=
364 __builtin_popcount(devinfo
->subslice_masks
[i
]);
367 for (int i
= 0; i
< sizeof(devinfo
->eu_masks
); i
++)
368 perf
->sys_vars
.n_eus
+= __builtin_popcount(devinfo
->eu_masks
[i
]);
370 perf
->sys_vars
.eu_threads_count
= devinfo
->num_thread_per_eu
;
372 /* The subslice mask builtin contains bits for all slices. Prior to Gen11
373 * it had groups of 3bits for each slice, on Gen11 it's 8bits for each
376 * Ideally equations would be updated to have a slice/subslice query
379 perf
->sys_vars
.subslice_mask
= 0;
381 int bits_per_subslice
= devinfo
->gen
== 11 ? 8 : 3;
383 for (int s
= 0; s
< util_last_bit(devinfo
->slice_masks
); s
++) {
384 for (int ss
= 0; ss
< (devinfo
->subslice_slice_stride
* 8); ss
++) {
385 if (gen_device_info_subslice_available(devinfo
, s
, ss
))
386 perf
->sys_vars
.subslice_mask
|= 1ULL << (s
* bits_per_subslice
+ ss
);
392 init_oa_sys_vars(struct gen_perf_config
*perf
, const struct gen_device_info
*devinfo
)
394 uint64_t min_freq_mhz
= 0, max_freq_mhz
= 0;
396 if (!read_sysfs_drm_device_file_uint64(perf
, "gt_min_freq_mhz", &min_freq_mhz
))
399 if (!read_sysfs_drm_device_file_uint64(perf
, "gt_max_freq_mhz", &max_freq_mhz
))
402 memset(&perf
->sys_vars
, 0, sizeof(perf
->sys_vars
));
403 perf
->sys_vars
.gt_min_freq
= min_freq_mhz
* 1000000;
404 perf
->sys_vars
.gt_max_freq
= max_freq_mhz
* 1000000;
405 perf
->sys_vars
.timestamp_frequency
= devinfo
->timestamp_frequency
;
406 perf
->sys_vars
.revision
= devinfo
->revision
;
407 compute_topology_builtins(perf
, devinfo
);
412 typedef void (*perf_register_oa_queries_t
)(struct gen_perf_config
*);
414 static perf_register_oa_queries_t
415 get_register_queries_function(const struct gen_device_info
*devinfo
)
417 if (devinfo
->is_haswell
)
418 return gen_oa_register_queries_hsw
;
419 if (devinfo
->is_cherryview
)
420 return gen_oa_register_queries_chv
;
421 if (devinfo
->is_broadwell
)
422 return gen_oa_register_queries_bdw
;
423 if (devinfo
->is_broxton
)
424 return gen_oa_register_queries_bxt
;
425 if (devinfo
->is_skylake
) {
426 if (devinfo
->gt
== 2)
427 return gen_oa_register_queries_sklgt2
;
428 if (devinfo
->gt
== 3)
429 return gen_oa_register_queries_sklgt3
;
430 if (devinfo
->gt
== 4)
431 return gen_oa_register_queries_sklgt4
;
433 if (devinfo
->is_kabylake
) {
434 if (devinfo
->gt
== 2)
435 return gen_oa_register_queries_kblgt2
;
436 if (devinfo
->gt
== 3)
437 return gen_oa_register_queries_kblgt3
;
439 if (devinfo
->is_geminilake
)
440 return gen_oa_register_queries_glk
;
441 if (devinfo
->is_coffeelake
) {
442 if (devinfo
->gt
== 2)
443 return gen_oa_register_queries_cflgt2
;
444 if (devinfo
->gt
== 3)
445 return gen_oa_register_queries_cflgt3
;
447 if (devinfo
->is_cannonlake
)
448 return gen_oa_register_queries_cnl
;
449 if (devinfo
->gen
== 11) {
450 if (devinfo
->is_elkhartlake
)
451 return gen_oa_register_queries_lkf
;
452 return gen_oa_register_queries_icl
;
454 if (devinfo
->gen
== 12)
455 return gen_oa_register_queries_tgl
;
461 load_pipeline_statistic_metrics(struct gen_perf_config
*perf_cfg
,
462 const struct gen_device_info
*devinfo
)
464 struct gen_perf_query_info
*query
=
465 gen_perf_append_query_info(perf_cfg
, MAX_STAT_COUNTERS
);
467 query
->kind
= GEN_PERF_QUERY_TYPE_PIPELINE
;
468 query
->name
= "Pipeline Statistics Registers";
470 gen_perf_query_add_basic_stat_reg(query
, IA_VERTICES_COUNT
,
471 "N vertices submitted");
472 gen_perf_query_add_basic_stat_reg(query
, IA_PRIMITIVES_COUNT
,
473 "N primitives submitted");
474 gen_perf_query_add_basic_stat_reg(query
, VS_INVOCATION_COUNT
,
475 "N vertex shader invocations");
477 if (devinfo
->gen
== 6) {
478 gen_perf_query_add_stat_reg(query
, GEN6_SO_PRIM_STORAGE_NEEDED
, 1, 1,
479 "SO_PRIM_STORAGE_NEEDED",
480 "N geometry shader stream-out primitives (total)");
481 gen_perf_query_add_stat_reg(query
, GEN6_SO_NUM_PRIMS_WRITTEN
, 1, 1,
482 "SO_NUM_PRIMS_WRITTEN",
483 "N geometry shader stream-out primitives (written)");
485 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(0), 1, 1,
486 "SO_PRIM_STORAGE_NEEDED (Stream 0)",
487 "N stream-out (stream 0) primitives (total)");
488 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(1), 1, 1,
489 "SO_PRIM_STORAGE_NEEDED (Stream 1)",
490 "N stream-out (stream 1) primitives (total)");
491 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(2), 1, 1,
492 "SO_PRIM_STORAGE_NEEDED (Stream 2)",
493 "N stream-out (stream 2) primitives (total)");
494 gen_perf_query_add_stat_reg(query
, GEN7_SO_PRIM_STORAGE_NEEDED(3), 1, 1,
495 "SO_PRIM_STORAGE_NEEDED (Stream 3)",
496 "N stream-out (stream 3) primitives (total)");
497 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(0), 1, 1,
498 "SO_NUM_PRIMS_WRITTEN (Stream 0)",
499 "N stream-out (stream 0) primitives (written)");
500 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(1), 1, 1,
501 "SO_NUM_PRIMS_WRITTEN (Stream 1)",
502 "N stream-out (stream 1) primitives (written)");
503 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(2), 1, 1,
504 "SO_NUM_PRIMS_WRITTEN (Stream 2)",
505 "N stream-out (stream 2) primitives (written)");
506 gen_perf_query_add_stat_reg(query
, GEN7_SO_NUM_PRIMS_WRITTEN(3), 1, 1,
507 "SO_NUM_PRIMS_WRITTEN (Stream 3)",
508 "N stream-out (stream 3) primitives (written)");
511 gen_perf_query_add_basic_stat_reg(query
, HS_INVOCATION_COUNT
,
512 "N TCS shader invocations");
513 gen_perf_query_add_basic_stat_reg(query
, DS_INVOCATION_COUNT
,
514 "N TES shader invocations");
516 gen_perf_query_add_basic_stat_reg(query
, GS_INVOCATION_COUNT
,
517 "N geometry shader invocations");
518 gen_perf_query_add_basic_stat_reg(query
, GS_PRIMITIVES_COUNT
,
519 "N geometry shader primitives emitted");
521 gen_perf_query_add_basic_stat_reg(query
, CL_INVOCATION_COUNT
,
522 "N primitives entering clipping");
523 gen_perf_query_add_basic_stat_reg(query
, CL_PRIMITIVES_COUNT
,
524 "N primitives leaving clipping");
526 if (devinfo
->is_haswell
|| devinfo
->gen
== 8) {
527 gen_perf_query_add_stat_reg(query
, PS_INVOCATION_COUNT
, 1, 4,
528 "N fragment shader invocations",
529 "N fragment shader invocations");
531 gen_perf_query_add_basic_stat_reg(query
, PS_INVOCATION_COUNT
,
532 "N fragment shader invocations");
535 gen_perf_query_add_basic_stat_reg(query
, PS_DEPTH_COUNT
,
536 "N z-pass fragments");
538 if (devinfo
->gen
>= 7) {
539 gen_perf_query_add_basic_stat_reg(query
, CS_INVOCATION_COUNT
,
540 "N compute shader invocations");
543 query
->data_size
= sizeof(uint64_t) * query
->n_counters
;
547 i915_perf_version(int drm_fd
)
550 drm_i915_getparam_t gp
= {
551 .param
= I915_PARAM_PERF_REVISION
,
555 int ret
= gen_ioctl(drm_fd
, DRM_IOCTL_I915_GETPARAM
, &gp
);
557 /* Return 0 if this getparam is not supported, the first version supported
560 return ret
< 0 ? 0 : tmp
;
564 i915_get_sseu(int drm_fd
, struct drm_i915_gem_context_param_sseu
*sseu
)
566 struct drm_i915_gem_context_param arg
= {
567 .param
= I915_CONTEXT_PARAM_SSEU
,
568 .size
= sizeof(*sseu
),
569 .value
= to_user_pointer(sseu
)
572 gen_ioctl(drm_fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &arg
);
576 compare_counters(const void *_c1
, const void *_c2
)
578 const struct gen_perf_query_counter
* const *c1
= _c1
, * const *c2
= _c2
;
579 return strcmp((*c1
)->symbol_name
, (*c2
)->symbol_name
);
583 build_unique_counter_list(struct gen_perf_config
*perf
)
585 assert(perf
->n_queries
< 64);
587 struct hash_table
*counters_table
=
588 _mesa_hash_table_create(perf
,
590 _mesa_key_string_equal
);
591 struct hash_entry
*entry
;
592 for (int q
= 0; q
< perf
->n_queries
; q
++) {
593 struct gen_perf_query_info
*query
= &perf
->queries
[q
];
595 for (int c
= 0; c
< query
->n_counters
; c
++) {
596 struct gen_perf_query_counter
*counter
, *unique_counter
;
598 counter
= &query
->counters
[c
];
599 entry
= _mesa_hash_table_search(counters_table
, counter
->symbol_name
);
602 unique_counter
= entry
->data
;
603 unique_counter
->query_mask
|= BITFIELD64_BIT(q
);
607 unique_counter
= counter
;
608 unique_counter
->query_mask
= BITFIELD64_BIT(q
);
610 _mesa_hash_table_insert(counters_table
, unique_counter
->symbol_name
, unique_counter
);
614 perf
->n_counters
= _mesa_hash_table_num_entries(counters_table
);
615 perf
->counters
= ralloc_array(perf
, struct gen_perf_query_counter
*,
619 hash_table_foreach(counters_table
, entry
) {
620 struct gen_perf_query_counter
*counter
= entry
->data
;
621 perf
->counters
[c
++] = counter
;
624 _mesa_hash_table_destroy(counters_table
, NULL
);
626 qsort(perf
->counters
, perf
->n_counters
, sizeof(perf
->counters
[0]),
631 load_oa_metrics(struct gen_perf_config
*perf
, int fd
,
632 const struct gen_device_info
*devinfo
)
634 perf_register_oa_queries_t oa_register
= get_register_queries_function(devinfo
);
635 bool i915_perf_oa_available
= false;
638 perf
->i915_query_supported
= i915_query_perf_config_supported(perf
, fd
);
639 perf
->i915_perf_version
= i915_perf_version(fd
);
641 /* Record the default SSEU configuration. */
642 i915_get_sseu(fd
, &perf
->sseu
);
644 /* The existence of this sysctl parameter implies the kernel supports
645 * the i915 perf interface.
647 if (stat("/proc/sys/dev/i915/perf_stream_paranoid", &sb
) == 0) {
649 /* If _paranoid == 1 then on Gen8+ we won't be able to access OA
650 * metrics unless running as root.
652 if (devinfo
->is_haswell
)
653 i915_perf_oa_available
= true;
655 uint64_t paranoid
= 1;
657 read_file_uint64("/proc/sys/dev/i915/perf_stream_paranoid", ¶noid
);
659 if (paranoid
== 0 || geteuid() == 0)
660 i915_perf_oa_available
= true;
664 if (!i915_perf_oa_available
||
666 !get_sysfs_dev_dir(perf
, fd
) ||
667 !init_oa_sys_vars(perf
, devinfo
))
670 perf
->oa_metrics_table
=
671 _mesa_hash_table_create(perf
, _mesa_hash_string
,
672 _mesa_key_string_equal
);
674 /* Index all the metric sets mesa knows about before looking to see what
675 * the kernel is advertising.
679 if (likely((INTEL_DEBUG
& DEBUG_NO_OACONFIG
) == 0) &&
680 kernel_has_dynamic_config_support(perf
, fd
))
681 init_oa_configs(perf
, fd
, devinfo
);
683 enumerate_sysfs_metrics(perf
, devinfo
);
685 build_unique_counter_list(perf
);
690 struct gen_perf_registers
*
691 gen_perf_load_configuration(struct gen_perf_config
*perf_cfg
, int fd
, const char *guid
)
693 if (!perf_cfg
->i915_query_supported
)
696 struct drm_i915_perf_oa_config i915_config
= { 0, };
697 if (!i915_query_perf_config_data(perf_cfg
, fd
, guid
, &i915_config
))
700 struct gen_perf_registers
*config
= rzalloc(NULL
, struct gen_perf_registers
);
701 config
->n_flex_regs
= i915_config
.n_flex_regs
;
702 config
->flex_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_flex_regs
);
703 config
->n_mux_regs
= i915_config
.n_mux_regs
;
704 config
->mux_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_mux_regs
);
705 config
->n_b_counter_regs
= i915_config
.n_boolean_regs
;
706 config
->b_counter_regs
= rzalloc_array(config
, struct gen_perf_query_register_prog
, config
->n_b_counter_regs
);
709 * struct gen_perf_query_register_prog maps exactly to the tuple of
710 * (register offset, register value) returned by the i915.
712 i915_config
.flex_regs_ptr
= to_user_pointer(config
->flex_regs
);
713 i915_config
.mux_regs_ptr
= to_user_pointer(config
->mux_regs
);
714 i915_config
.boolean_regs_ptr
= to_user_pointer(config
->b_counter_regs
);
715 if (!i915_query_perf_config_data(perf_cfg
, fd
, guid
, &i915_config
)) {
724 gen_perf_store_configuration(struct gen_perf_config
*perf_cfg
, int fd
,
725 const struct gen_perf_registers
*config
,
729 return i915_add_config(perf_cfg
, fd
, config
, guid
);
731 struct mesa_sha1 sha1_ctx
;
732 _mesa_sha1_init(&sha1_ctx
);
734 if (config
->flex_regs
) {
735 _mesa_sha1_update(&sha1_ctx
, config
->flex_regs
,
736 sizeof(config
->flex_regs
[0]) *
737 config
->n_flex_regs
);
739 if (config
->mux_regs
) {
740 _mesa_sha1_update(&sha1_ctx
, config
->mux_regs
,
741 sizeof(config
->mux_regs
[0]) *
744 if (config
->b_counter_regs
) {
745 _mesa_sha1_update(&sha1_ctx
, config
->b_counter_regs
,
746 sizeof(config
->b_counter_regs
[0]) *
747 config
->n_b_counter_regs
);
751 _mesa_sha1_final(&sha1_ctx
, hash
);
753 char formatted_hash
[41];
754 _mesa_sha1_format(formatted_hash
, hash
);
756 char generated_guid
[37];
757 snprintf(generated_guid
, sizeof(generated_guid
),
758 "%.8s-%.4s-%.4s-%.4s-%.12s",
759 &formatted_hash
[0], &formatted_hash
[8],
760 &formatted_hash
[8 + 4], &formatted_hash
[8 + 4 + 4],
761 &formatted_hash
[8 + 4 + 4 + 4]);
763 /* Check if already present. */
765 if (gen_perf_load_metric_id(perf_cfg
, generated_guid
, &id
))
768 return i915_add_config(perf_cfg
, fd
, config
, generated_guid
);
771 /* Accumulate 32bits OA counters */
773 accumulate_uint32(const uint32_t *report0
,
774 const uint32_t *report1
,
775 uint64_t *accumulator
)
777 *accumulator
+= (uint32_t)(*report1
- *report0
);
780 /* Accumulate 40bits OA counters */
782 accumulate_uint40(int a_index
,
783 const uint32_t *report0
,
784 const uint32_t *report1
,
785 uint64_t *accumulator
)
787 const uint8_t *high_bytes0
= (uint8_t *)(report0
+ 40);
788 const uint8_t *high_bytes1
= (uint8_t *)(report1
+ 40);
789 uint64_t high0
= (uint64_t)(high_bytes0
[a_index
]) << 32;
790 uint64_t high1
= (uint64_t)(high_bytes1
[a_index
]) << 32;
791 uint64_t value0
= report0
[a_index
+ 4] | high0
;
792 uint64_t value1
= report1
[a_index
+ 4] | high1
;
796 delta
= (1ULL << 40) + value1
- value0
;
798 delta
= value1
- value0
;
800 *accumulator
+= delta
;
804 gen8_read_report_clock_ratios(const uint32_t *report
,
805 uint64_t *slice_freq_hz
,
806 uint64_t *unslice_freq_hz
)
808 /* The lower 16bits of the RPT_ID field of the OA reports contains a
809 * snapshot of the bits coming from the RP_FREQ_NORMAL register and is
812 * RPT_ID[31:25]: RP_FREQ_NORMAL[20:14] (low squashed_slice_clock_frequency)
813 * RPT_ID[10:9]: RP_FREQ_NORMAL[22:21] (high squashed_slice_clock_frequency)
814 * RPT_ID[8:0]: RP_FREQ_NORMAL[31:23] (squashed_unslice_clock_frequency)
816 * RP_FREQ_NORMAL[31:23]: Software Unslice Ratio Request
817 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
819 * RP_FREQ_NORMAL[22:14]: Software Slice Ratio Request
820 * Multiple of 33.33MHz 2xclk (16 MHz 1xclk)
823 uint32_t unslice_freq
= report
[0] & 0x1ff;
824 uint32_t slice_freq_low
= (report
[0] >> 25) & 0x7f;
825 uint32_t slice_freq_high
= (report
[0] >> 9) & 0x3;
826 uint32_t slice_freq
= slice_freq_low
| (slice_freq_high
<< 7);
828 *slice_freq_hz
= slice_freq
* 16666667ULL;
829 *unslice_freq_hz
= unslice_freq
* 16666667ULL;
833 gen_perf_query_result_read_frequencies(struct gen_perf_query_result
*result
,
834 const struct gen_device_info
*devinfo
,
835 const uint32_t *start
,
838 /* Slice/Unslice frequency is only available in the OA reports when the
839 * "Disable OA reports due to clock ratio change" field in
840 * OA_DEBUG_REGISTER is set to 1. This is how the kernel programs this
841 * global register (see drivers/gpu/drm/i915/i915_perf.c)
843 * Documentation says this should be available on Gen9+ but experimentation
844 * shows that Gen8 reports similar values, so we enable it there too.
846 if (devinfo
->gen
< 8)
849 gen8_read_report_clock_ratios(start
,
850 &result
->slice_frequency
[0],
851 &result
->unslice_frequency
[0]);
852 gen8_read_report_clock_ratios(end
,
853 &result
->slice_frequency
[1],
854 &result
->unslice_frequency
[1]);
858 gen_perf_query_result_accumulate(struct gen_perf_query_result
*result
,
859 const struct gen_perf_query_info
*query
,
860 const uint32_t *start
,
865 if (result
->hw_id
== OA_REPORT_INVALID_CTX_ID
&&
866 start
[2] != OA_REPORT_INVALID_CTX_ID
)
867 result
->hw_id
= start
[2];
868 if (result
->reports_accumulated
== 0)
869 result
->begin_timestamp
= start
[1];
870 result
->reports_accumulated
++;
872 switch (query
->oa_format
) {
873 case I915_OA_FORMAT_A32u40_A4u32_B8_C8
:
874 accumulate_uint32(start
+ 1, end
+ 1, result
->accumulator
+ idx
++); /* timestamp */
875 accumulate_uint32(start
+ 3, end
+ 3, result
->accumulator
+ idx
++); /* clock */
877 /* 32x 40bit A counters... */
878 for (i
= 0; i
< 32; i
++)
879 accumulate_uint40(i
, start
, end
, result
->accumulator
+ idx
++);
881 /* 4x 32bit A counters... */
882 for (i
= 0; i
< 4; i
++)
883 accumulate_uint32(start
+ 36 + i
, end
+ 36 + i
, result
->accumulator
+ idx
++);
885 /* 8x 32bit B counters + 8x 32bit C counters... */
886 for (i
= 0; i
< 16; i
++)
887 accumulate_uint32(start
+ 48 + i
, end
+ 48 + i
, result
->accumulator
+ idx
++);
890 case I915_OA_FORMAT_A45_B8_C8
:
891 accumulate_uint32(start
+ 1, end
+ 1, result
->accumulator
); /* timestamp */
893 for (i
= 0; i
< 61; i
++)
894 accumulate_uint32(start
+ 3 + i
, end
+ 3 + i
, result
->accumulator
+ 1 + i
);
898 unreachable("Can't accumulate OA counters in unknown format");
904 gen_perf_query_result_clear(struct gen_perf_query_result
*result
)
906 memset(result
, 0, sizeof(*result
));
907 result
->hw_id
= OA_REPORT_INVALID_CTX_ID
; /* invalid */
911 gen_perf_init_metrics(struct gen_perf_config
*perf_cfg
,
912 const struct gen_device_info
*devinfo
,
914 bool include_pipeline_statistics
)
916 if (include_pipeline_statistics
) {
917 load_pipeline_statistic_metrics(perf_cfg
, devinfo
);
918 gen_perf_register_mdapi_statistic_query(perf_cfg
, devinfo
);
920 if (load_oa_metrics(perf_cfg
, drm_fd
, devinfo
))
921 gen_perf_register_mdapi_oa_query(perf_cfg
, devinfo
);