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[mesa.git] / src / intel / tools / gen10_context.h
1 /*
2 * Copyright © 2018 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef GEN10_CONTEXT_H
25 #define GEN10_CONTEXT_H
26
27 static inline void gen10_render_context_init(uint32_t *data, uint32_t *size)
28 {
29 *size = CONTEXT_RENDER_SIZE;
30 if (!data)
31 return;
32
33 *data++ = 0; /* MI_NOOP */
34 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
35 0x2244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
36 0x2034 /* RING_HEAD */, 0,
37 0x2030 /* RING_TAIL */, 0,
38 0x2038 /* RING_BUFFER_START */, RENDER_RING_ADDR,
39 0x203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
40 0x2168 /* BB_HEAD_U */, 0,
41 0x2140 /* BB_HEAD_L */, 0,
42 0x2110 /* BB_STATE */, 0,
43 0x211C /* SECOND_BB_HEAD_U */, 0,
44 0x2114 /* SECOND_BB_HEAD_L */, 0,
45 0x2118 /* SECOND_BB_STATE */, 0,
46 0x21C0 /* BB_PER_CTX_PTR */, 0,
47 0x21C4 /* RCS_INDIRECT_CTX */, 0,
48 0x21C8 /* RCS_INDIRECT_CTX_OFFSET */, 0,
49 0x2180 /* CCID */, 0);
50 *data++ = 0; /* MI_NOOP */
51
52 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
53 0x23A8 /* CTX_TIMESTAMP */, 0,
54 0x228C /* PDP3_UDW */, 0,
55 0x2288 /* PDP3_LDW */, 0,
56 0x2284 /* PDP2_UDW */, 0,
57 0x2280 /* PDP2_LDW */, 0,
58 0x227C /* PDP1_UDW */, 0,
59 0x2278 /* PDP1_LDW */, 0,
60 0x2274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
61 0x2270 /* PDP0_LDW */, PML4_PHYS_ADDR);
62 for (int i = 0; i < 12; i++)
63 *data++ = 0; /* MI_NOOP */
64
65 *data++ = 0; /* MI_NOOP */
66 MI_LOAD_REGISTER_IMM_vals(data, 0,
67 0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
68 0, /* GPGPU_CSR_BASE_ADDRESS ? */ 0);
69 *data++ = 0; /* MI_NOOP */
70
71 for (int i = 0; i < 9; i++)
72 *data++ = 0;
73
74 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
75 }
76
77 static inline void gen10_blitter_context_init(uint32_t *data, uint32_t *size)
78 {
79 *size = CONTEXT_OTHER_SIZE;
80 if (!data)
81 return;
82
83 *data++ = 0 /* MI_NOOP */;
84 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
85 0x22244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
86 0x22034 /* RING_HEAD */, 0,
87 0x22030 /* RING_TAIL */, 0,
88 0x22038 /* RING_BUFFER_START */, BLITTER_RING_ADDR,
89 0x2203C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
90 0x22168 /* BB_HEAD_U */, 0,
91 0x22140 /* BB_HEAD_L */, 0,
92 0x22110 /* BB_STATE */, 0,
93 0x2211C /* SECOND_BB_HEAD_U */, 0,
94 0x22114 /* SECOND_BB_HEAD_L */, 0,
95 0x22118 /* SECOND_BB_STATE */, 0,
96 0x221C0 /* BB_PER_CTX_PTR */, 0,
97 0x221C4 /* INDIRECT_CTX */, 0,
98 0x221C8 /* INDIRECT_CTX_OFFSET */, 0);
99 *data++ = 0 /* MI_NOOP */;
100 *data++ = 0 /* MI_NOOP */;
101
102 *data++ = 0 /* MI_NOOP */;
103 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
104 0x223A8 /* CTX_TIMESTAMP */, 0,
105 0x2228C /* PDP3_UDW */, 0,
106 0x22288 /* PDP3_LDW */, 0,
107 0x22284 /* PDP2_UDW */, 0,
108 0x22280 /* PDP2_LDW */, 0,
109 0x2227C /* PDP1_UDW */, 0,
110 0x22278 /* PDP1_LDW */, 0,
111 0x22274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
112 0x22270 /* PDP0_LDW */, PML4_PHYS_ADDR);
113 for (int i = 0; i < 13; i++)
114 *data++ = 0 /* MI_NOOP */;
115
116 MI_LOAD_REGISTER_IMM_vals(data, 0,
117 0x22200 /* BCS_SWCTRL */, 0);
118
119 for (int i = 0; i < 12; i++)
120 *data++ = 0 /* MI_NOOP */;
121
122
123 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
124 }
125
126 static inline void gen10_video_context_init(uint32_t *data, uint32_t *size)
127 {
128 *size = CONTEXT_OTHER_SIZE;
129 if (!data)
130 return;
131
132 *data++ = 0 /* MI_NOOP */;
133 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
134 0x1C244 /* CONTEXT_CONTROL */, 0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
135 0x1C034 /* RING_HEAD */, 0,
136 0x1C030 /* RING_TAIL */, 0,
137 0x1C038 /* RING_BUFFER_START */, VIDEO_RING_ADDR,
138 0x1C03C /* RING_BUFFER_CONTROL */, (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
139 0x1C168 /* BB_HEAD_U */, 0,
140 0x1C140 /* BB_HEAD_L */, 0,
141 0x1C110 /* BB_STATE */, 0,
142 0x1C11C /* SECOND_BB_HEAD_U */, 0,
143 0x1C114 /* SECOND_BB_HEAD_L */, 0,
144 0x1C118 /* SECOND_BB_STATE */, 0);
145 for (int i = 0; i < 8; i++)
146 *data++ = 0 /* MI_NOOP */;
147
148 *data++ = 0 /* MI_NOOP */;
149 MI_LOAD_REGISTER_IMM_vals(data, MI_LRI_FORCE_POSTED,
150 0x1C3A8 /* CTX_TIMESTAMP */, 0,
151 0x1C28C /* PDP3_UDW */, 0,
152 0x1C288 /* PDP3_LDW */, 0,
153 0x1C284 /* PDP2_UDW */, 0,
154 0x1C280 /* PDP2_LDW */, 0,
155 0x1C27C /* PDP1_UDW */, 0,
156 0x1C278 /* PDP1_LDW */, 0,
157 0x1C274 /* PDP0_UDW */, PML4_PHYS_ADDR >> 32,
158 0x1C270 /* PDP0_LDW */, PML4_PHYS_ADDR);
159 for (int i = 0; i < 12; i++)
160 *data++ = 0 /* MI_NOOP */;
161
162 *data++ = MI_BATCH_BUFFER_END | 1 /* End Context */;
163 }
164
165 #endif /* GEN10_CONTEXT_H */