src/intel/tools/gen10_context.h

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #ifndef GEN10_CONTEXT_H
  25 #define GEN10_CONTEXT_H
  26
  27 static const uint32_t gen10_render_context_init[CONTEXT_RENDER_SIZE / sizeof(uint32_t)] = {
  28    0 /* MI_NOOP */,
  29    MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
  30    0x2244 /* CONTEXT_CONTROL */,      0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
  31    0x2034 /* RING_HEAD */,         0,
  32    0x2030 /* RING_TAIL */,         0,
  33    0x2038 /* RING_BUFFER_START */,      RENDER_RING_ADDR,
  34    0x203C /* RING_BUFFER_CONTROL */,   (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
  35    0x2168 /* BB_HEAD_U */,         0,
  36    0x2140 /* BB_HEAD_L */,         0,
  37    0x2110 /* BB_STATE */,         0,
  38    0x211C /* SECOND_BB_HEAD_U */,      0,
  39    0x2114 /* SECOND_BB_HEAD_L */,      0,
  40    0x2118 /* SECOND_BB_STATE */,      0,
  41    0x21C0 /* BB_PER_CTX_PTR */,      0,
  42    0x21C4 /* RCS_INDIRECT_CTX */,      0,
  43    0x21C8 /* RCS_INDIRECT_CTX_OFFSET */,   0,
  44    0x2180 /* CCID */,           0,
  45
  46    0 /* MI_NOOP */,
  47    MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
  48    0x23A8 /* CTX_TIMESTAMP */,   0,
  49    0x228C /* PDP3_UDW */,      0,
  50    0x2288 /* PDP3_LDW */,      0,
  51    0x2284 /* PDP2_UDW */,      0,
  52    0x2280 /* PDP2_LDW */,      0,
  53    0x227C /* PDP1_UDW */,      0,
  54    0x2278 /* PDP1_LDW */,      0,
  55    0x2274 /* PDP0_UDW */,      PML4_PHYS_ADDR >> 32,
  56    0x2270 /* PDP0_LDW */,      PML4_PHYS_ADDR,
  57    /* MI_NOOP */
  58    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  59
  60    0 /* MI_NOOP */,
  61    MI_LOAD_REGISTER_IMM_n(1),
  62    0x20C8 /* R_PWR_CLK_STATE */, 0x7FFFFFFF,
  63    0, 0, 0 /* GPGPU_CSR_BASE_ADDRESS ? */,
  64    0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
  65
  66    MI_BATCH_BUFFER_END | 1 /* End Context */
  67 };
  68
  69 static const uint32_t gen10_blitter_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
  70    0 /* MI_NOOP */,
  71    MI_LOAD_REGISTER_IMM_n(14) | MI_LRI_FORCE_POSTED,
  72    0x22244 /* CONTEXT_CONTROL */,      0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
  73    0x22034 /* RING_HEAD */,      0,
  74    0x22030 /* RING_TAIL */,      0,
  75    0x22038 /* RING_BUFFER_START */,   BLITTER_RING_ADDR,
  76    0x2203C /* RING_BUFFER_CONTROL */,   (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
  77    0x22168 /* BB_HEAD_U */,      0,
  78    0x22140 /* BB_HEAD_L */,      0,
  79    0x22110 /* BB_STATE */,         0,
  80    0x2211C /* SECOND_BB_HEAD_U */,      0,
  81    0x22114 /* SECOND_BB_HEAD_L */,      0,
  82    0x22118 /* SECOND_BB_STATE */,      0,
  83    0x221C0 /* BB_PER_CTX_PTR */,        0,
  84    0x221C4 /* INDIRECT_CTX */,  0,
  85    0x221C8 /* INDIRECT_CTX_OFFSET */, 0,
  86    0, 0 /* MI_NOOP */,
  87
  88    0 /* MI_NOOP */,
  89    MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
  90    0x223A8 /* CTX_TIMESTAMP */, 0,
  91    0x2228C /* PDP3_UDW */,      0,
  92    0x22288 /* PDP3_LDW */,      0,
  93    0x22284 /* PDP2_UDW */,      0,
  94    0x22280 /* PDP2_LDW */,      0,
  95    0x2227C /* PDP1_UDW */,      0,
  96    0x22278 /* PDP1_LDW */,      0,
  97    0x22274 /* PDP0_UDW */,      PML4_PHYS_ADDR >> 32,
  98    0x22270 /* PDP0_LDW */,      PML4_PHYS_ADDR,
  99    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
 100    MI_LOAD_REGISTER_IMM_n(1),
 101    0x22200 /* BCS_SWCTRL */,    0,
 102    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 /* MI_NOOP */,
 103
 104    MI_BATCH_BUFFER_END | 1 /* End Context */
 105 };
 106
 107 static const uint32_t gen10_video_context_init[CONTEXT_OTHER_SIZE / sizeof(uint32_t)] = {
 108    0 /* MI_NOOP */,
 109    MI_LOAD_REGISTER_IMM_n(11) | MI_LRI_FORCE_POSTED,
 110    0x1C244 /* CONTEXT_CONTROL */,      0x90009 /* Inhibit Synchronous Context Switch | Engine Context Restore Inhibit */,
 111    0x1C034 /* RING_HEAD */,      0,
 112    0x1C030 /* RING_TAIL */,      0,
 113    0x1C038 /* RING_BUFFER_START */,   VIDEO_RING_ADDR,
 114    0x1C03C /* RING_BUFFER_CONTROL */,   (RING_SIZE - 4096) | 1 /* Buffer Length | Ring Buffer Enable */,
 115    0x1C168 /* BB_HEAD_U */,      0,
 116    0x1C140 /* BB_HEAD_L */,      0,
 117    0x1C110 /* BB_STATE */,         0,
 118    0x1C11C /* SECOND_BB_HEAD_U */,      0,
 119    0x1C114 /* SECOND_BB_HEAD_L */,      0,
 120    0x1C118 /* SECOND_BB_STATE */,      0,
 121    /* MI_NOOP */
 122    0, 0, 0, 0, 0, 0, 0, 0,
 123
 124    0 /* MI_NOOP */,
 125    MI_LOAD_REGISTER_IMM_n(9) | MI_LRI_FORCE_POSTED,
 126    0x1C3A8 /* CTX_TIMESTAMP */,   0,
 127    0x1C28C /* PDP3_UDW */,      0,
 128    0x1C288 /* PDP3_LDW */,      0,
 129    0x1C284 /* PDP2_UDW */,      0,
 130    0x1C280 /* PDP2_LDW */,      0,
 131    0x1C27C /* PDP1_UDW */,      0,
 132    0x1C278 /* PDP1_LDW */,      0,
 133    0x1C274 /* PDP0_UDW */,      PML4_PHYS_ADDR >> 32,
 134    0x1C270 /* PDP0_LDW */,      PML4_PHYS_ADDR,
 135    /* MI_NOOP */
 136    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 137
 138    MI_BATCH_BUFFER_END | 1  /* End Context */
 139 };
 140
 141 #endif /* GEN10_CONTEXT_H */