3 * Copyright © 2018 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #define YYLTYPE YYLTYPE
32 typedef struct YYLTYPE
48 message(enum message_level level, YYLTYPE *location,
51 static const char *level_str[] = { "warning", "error" };
55 fprintf(stderr, "%s:%d:%d: %s: ", input_filename,
57 location->first_column, level_str[level]);
59 fprintf(stderr, "%s:%s: ", input_filename, level_str[level]);
62 vfprintf(stderr, fmt, args);
66 #define warn(flag, l, fmt, ...) \
68 if (warning_flags & WARN_ ## flag) \
69 message(WARN, l, fmt, ## __VA_ARGS__); \
72 #define error(l, fmt, ...) \
74 message(ERROR, l, fmt, ## __VA_ARGS__); \
78 isPowerofTwo(unsigned int x)
80 return x && (!(x & (x - 1)));
84 set_direct_src_operand(struct brw_reg *reg, int type)
86 return brw_reg(reg->file,
100 i965_asm_unary_instruction(int opcode, struct brw_codegen *p,
101 struct brw_reg dest, struct brw_reg src0)
104 case BRW_OPCODE_BFREV:
105 brw_BFREV(p, dest, src0);
107 case BRW_OPCODE_CBIT:
108 brw_CBIT(p, dest, src0);
110 case BRW_OPCODE_F32TO16:
111 brw_F32TO16(p, dest, src0);
113 case BRW_OPCODE_F16TO32:
114 brw_F16TO32(p, dest, src0);
117 brw_MOV(p, dest, src0);
120 brw_FBL(p, dest, src0);
123 brw_FRC(p, dest, src0);
126 brw_FBH(p, dest, src0);
129 brw_NOT(p, dest, src0);
131 case BRW_OPCODE_RNDE:
132 brw_RNDE(p, dest, src0);
134 case BRW_OPCODE_RNDZ:
135 brw_RNDZ(p, dest, src0);
137 case BRW_OPCODE_RNDD:
138 brw_RNDD(p, dest, src0);
141 brw_LZD(p, dest, src0);
144 brw_DIM(p, dest, src0);
146 case BRW_OPCODE_RNDU:
147 fprintf(stderr, "Opcode BRW_OPCODE_RNDU unhandled\n");
150 fprintf(stderr, "Unsupported unary opcode\n");
155 i965_asm_binary_instruction(int opcode,
156 struct brw_codegen *p,
162 case BRW_OPCODE_ADDC:
163 brw_ADDC(p, dest, src0, src1);
165 case BRW_OPCODE_BFI1:
166 brw_BFI1(p, dest, src0, src1);
169 brw_DP2(p, dest, src0, src1);
172 brw_DP3(p, dest, src0, src1);
175 brw_DP4(p, dest, src0, src1);
178 brw_DPH(p, dest, src0, src1);
180 case BRW_OPCODE_LINE:
181 brw_LINE(p, dest, src0, src1);
184 brw_MAC(p, dest, src0, src1);
186 case BRW_OPCODE_MACH:
187 brw_MACH(p, dest, src0, src1);
190 brw_PLN(p, dest, src0, src1);
193 brw_ROL(p, dest, src0, src1);
196 brw_ROR(p, dest, src0, src1);
198 case BRW_OPCODE_SAD2:
199 fprintf(stderr, "Opcode BRW_OPCODE_SAD2 unhandled\n");
201 case BRW_OPCODE_SADA2:
202 fprintf(stderr, "Opcode BRW_OPCODE_SADA2 unhandled\n");
204 case BRW_OPCODE_SUBB:
205 brw_SUBB(p, dest, src0, src1);
208 brw_ADD(p, dest, src0, src1);
211 /* Third parameter is conditional modifier
212 * which gets updated later
214 brw_CMP(p, dest, 0, src0, src1);
217 brw_AND(p, dest, src0, src1);
220 brw_ASR(p, dest, src0, src1);
223 brw_AVG(p, dest, src0, src1);
226 brw_OR(p, dest, src0, src1);
229 brw_SEL(p, dest, src0, src1);
232 brw_SHL(p, dest, src0, src1);
235 brw_SHR(p, dest, src0, src1);
238 brw_XOR(p, dest, src0, src1);
241 brw_MUL(p, dest, src0, src1);
244 fprintf(stderr, "Unsupported binary opcode\n");
249 i965_asm_ternary_instruction(int opcode,
250 struct brw_codegen *p,
258 brw_MAD(p, dest, src0, src1, src2);
260 case BRW_OPCODE_CSEL:
261 brw_CSEL(p, dest, src0, src1, src2);
264 brw_LRP(p, dest, src0, src1, src2);
267 brw_BFE(p, dest, src0, src1, src2);
269 case BRW_OPCODE_BFI2:
270 brw_BFI2(p, dest, src0, src1, src2);
273 fprintf(stderr, "Unsupported ternary opcode\n");
278 i965_asm_set_instruction_options(struct brw_codegen *p,
279 struct options options)
281 brw_inst_set_access_mode(p->devinfo, brw_last_inst,
282 options.access_mode);
283 brw_inst_set_mask_control(p->devinfo, brw_last_inst,
284 options.mask_control);
285 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
286 options.thread_control);
287 brw_inst_set_no_dd_check(p->devinfo, brw_last_inst,
288 options.no_dd_check);
289 brw_inst_set_no_dd_clear(p->devinfo, brw_last_inst,
290 options.no_dd_clear);
291 brw_inst_set_debug_control(p->devinfo, brw_last_inst,
292 options.debug_control);
293 if (p->devinfo->gen >= 6)
294 brw_inst_set_acc_wr_control(p->devinfo, brw_last_inst,
295 options.acc_wr_control);
296 brw_inst_set_cmpt_control(p->devinfo, brw_last_inst,
301 i965_asm_set_dst_nr(struct brw_codegen *p,
303 struct options options)
305 if (p->devinfo->gen <= 6) {
306 if (reg->file == BRW_MESSAGE_REGISTER_FILE &&
307 options.qtr_ctrl == BRW_COMPRESSION_COMPRESSED &&
309 reg->nr |= BRW_MRF_COMPR4;
322 unsigned long long int llint;
324 struct brw_codegen *program;
325 struct predicate predicate;
326 struct condition condition;
327 struct options options;
328 brw_inst *instruction;
338 %token LSQUARE RSQUARE
343 %token <integer> TYPE_B TYPE_UB
344 %token <integer> TYPE_W TYPE_UW
345 %token <integer> TYPE_D TYPE_UD
346 %token <integer> TYPE_Q TYPE_UQ
347 %token <integer> TYPE_V TYPE_UV
348 %token <integer> TYPE_F TYPE_HF
349 %token <integer> TYPE_DF TYPE_NF
350 %token <integer> TYPE_VF
353 %token <integer> ADD ADD3 ADDC AND ASR AVG
354 %token <integer> BFE BFI1 BFI2 BFB BFREV BRC BRD BREAK
355 %token <integer> CALL CALLA CASE CBIT CMP CMPN CONT CSEL
356 %token <integer> DIM DO DPAS DPASW DP2 DP3 DP4 DP4A DPH
357 %token <integer> ELSE ENDIF F16TO32 F32TO16 FBH FBL FORK FRC
358 %token <integer> GOTO
359 %token <integer> HALT
360 %token <integer> IF IFF ILLEGAL
361 %token <integer> JMPI JOIN
362 %token <integer> LINE LRP LZD
363 %token <integer> MAC MACH MAD MADM MOV MOVI MUL MREST MSAVE
364 %token <integer> NENOP NOP NOT
366 %token <integer> PLN POP PUSH
367 %token <integer> RET RNDD RNDE RNDU RNDZ ROL ROR
368 %token <integer> SAD2 SADA2 SEL SEND SENDC SENDS SENDSC SHL SHR SMOV SUBB SYNC
369 %token <integer> WAIT WHILE
372 /* extended math functions */
373 %token <integer> COS EXP FDIV INV INVM INTDIV INTDIVMOD INTMOD LOG POW RSQ
374 %token <integer> RSQRTM SIN SINCOS SQRT
376 /* shared functions for send */
377 %token CONST CRE DATA DP_DATA_1 GATEWAY MATH PIXEL_INTERP READ RENDER SAMPLER
378 %token THREAD_SPAWNER URB VME WRITE DP_SAMPLER
380 /* Conditional modifiers */
381 %token <integer> EQUAL GREATER GREATER_EQUAL LESS LESS_EQUAL NOT_EQUAL
382 %token <integer> NOT_ZERO OVERFLOW UNORDERED ZERO
384 /* register Access Modes */
385 %token ALIGN1 ALIGN16
387 /* accumulator write control */
390 /* compaction control */
393 /* compression control */
394 %token COMPR COMPR4 SECHALF
396 /* mask control (WeCtrl) */
402 /* dependency control */
403 %token NODDCLR NODDCHK
411 /* predicate control */
412 %token <integer> ANYV ALLV ANY2H ALL2H ANY4H ALL4H ANY8H ALL8H ANY16H ALL16H
413 %token <integer> ANY32H ALL32H
415 /* round instructions */
416 %token <integer> ROUND_INCREMENT
425 %token QTR_2Q QTR_3Q QTR_4Q QTR_2H QTR_2N QTR_3N QTR_4N QTR_5N
426 %token QTR_6N QTR_7N QTR_8N
429 %token <integer> X Y Z W
432 %token GENREGFILE MSGREGFILE
434 /* vertical stride in register region */
438 %token <integer> GENREG MSGREG ADDRREG ACCREG FLAGREG NOTIFYREG STATEREG
439 %token <integer> CONTROLREG IPREG PERFORMANCEREG THREADREG CHANNELENABLEREG
440 %token <integer> MASKREG
442 %token <integer> INTEGER
446 %precedence SUBREGNUM
449 %precedence EMPTYEXECSIZE
452 %type <integer> execsize simple_int exp
455 /* predicate control */
456 %type <integer> predctrl predstate
457 %type <predicate> predicate
459 /* conditional modifier */
460 %type <condition> cond_mod
461 %type <integer> condModifiers
463 /* instruction options */
464 %type <options> instoptions instoption_list
465 %type <integer> instoption
468 %type <integer> writemask_x writemask_y writemask_z writemask_w
469 %type <reg> writemask
472 %type <reg> dst dstoperand dstoperandex dstoperandex_typed dstreg dsttype
473 %type <reg> dstoperandex_ud_typed
474 %type <integer> dstregion
476 %type <integer> saturate relativelocation rellocation
477 %type <reg> relativelocation2
480 %type <reg> directsrcoperand directsrcaccoperand indirectsrcoperand srcacc
481 %type <reg> srcarcoperandex srcaccimm srcarcoperandex_typed srctype srcimm
482 %type <reg> srcarcoperandex_ud_typed srcimmtype indirectgenreg indirectregion
483 %type <reg> immreg src reg32 payload directgenreg_list addrparam region
484 %type <reg> region_wh swizzle directgenreg directmsgreg indirectmsgreg
487 %type <reg> accreg addrreg channelenablereg controlreg flagreg ipreg
488 %type <reg> notifyreg nullreg performancereg threadcontrolreg statereg maskreg
489 %type <integer> subregnum
491 /* immediate values */
494 /* instruction opcodes */
495 %type <integer> unaryopcodes binaryopcodes binaryaccopcodes ternaryopcodes
496 %type <integer> sendop
497 %type <instruction> sendopcode
499 %type <integer> negate abs chansel math_function sharedfunction
504 add_instruction_option(struct options *options, int option)
508 options->access_mode = BRW_ALIGN_1;
511 options->access_mode = BRW_ALIGN_16;
514 options->qtr_ctrl |= BRW_COMPRESSION_2NDHALF;
517 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
518 options->is_compr = true;
521 options->qtr_ctrl |= BRW_COMPRESSION_COMPRESSED;
524 options->thread_control |= BRW_THREAD_SWITCH;
527 options->thread_control |= BRW_THREAD_ATOMIC;
530 options->no_dd_check = true;
533 options->no_dd_clear = BRW_DEPENDENCY_NOTCLEARED;
536 options->mask_control |= BRW_MASK_DISABLE;
539 options->debug_control = BRW_DEBUG_BREAKPOINT;
542 options->mask_control |= BRW_WE_ALL;
545 options->compaction = true;
548 options->acc_wr_control = true;
551 options->end_of_thread = true;
553 /* TODO : Figure out how to set instruction group and get rid of
557 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
560 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
563 options->qtr_ctrl = 3;
566 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
569 options->qtr_ctrl = BRW_COMPRESSION_NONE;
570 options->nib_ctrl = true;
573 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
576 options->qtr_ctrl = BRW_COMPRESSION_2NDHALF;
577 options->nib_ctrl = true;
580 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
583 options->qtr_ctrl = BRW_COMPRESSION_COMPRESSED;
584 options->nib_ctrl = true;
587 options->qtr_ctrl = 3;
590 options->qtr_ctrl = 3;
591 options->nib_ctrl = true;
603 instrseq instruction SEMICOLON
604 | instrseq relocatableinstruction SEMICOLON
605 | instruction SEMICOLON
606 | relocatableinstruction SEMICOLON
609 /* Instruction Group */
613 | binaryaccinstruction
621 relocatableinstruction:
628 /* Unary instruction */
630 predicate unaryopcodes saturate cond_mod execsize dst srcaccimm instoptions
632 i965_asm_set_dst_nr(p, &$6, $8);
633 brw_set_default_access_mode(p, $8.access_mode);
634 i965_asm_unary_instruction($2, p, $6, $7);
635 brw_pop_insn_state(p);
636 i965_asm_set_instruction_options(p, $8);
637 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
640 if (p->devinfo->gen >= 7) {
641 if ($2 != BRW_OPCODE_DIM) {
642 brw_inst_set_flag_reg_nr(p->devinfo,
645 brw_inst_set_flag_subreg_nr(p->devinfo,
651 if ($7.file != BRW_IMMEDIATE_VALUE) {
652 brw_inst_set_src0_vstride(p->devinfo, brw_last_inst,
655 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
656 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
657 // TODO: set instruction group instead of qtr and nib ctrl
658 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
661 if (p->devinfo->gen >= 7)
662 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
685 /* Binary instruction */
687 predicate binaryopcodes saturate cond_mod execsize dst srcimm srcimm instoptions
689 i965_asm_set_dst_nr(p, &$6, $9);
690 brw_set_default_access_mode(p, $9.access_mode);
691 i965_asm_binary_instruction($2, p, $6, $7, $8);
692 i965_asm_set_instruction_options(p, $9);
693 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
696 if (p->devinfo->gen >= 7) {
697 brw_inst_set_flag_reg_nr(p->devinfo, brw_last_inst,
699 brw_inst_set_flag_subreg_nr(p->devinfo, brw_last_inst,
703 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
704 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
705 // TODO: set instruction group instead of qtr and nib ctrl
706 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
709 if (p->devinfo->gen >= 7)
710 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
713 brw_pop_insn_state(p);
736 /* Binary acc instruction */
737 binaryaccinstruction:
738 predicate binaryaccopcodes saturate cond_mod execsize dst srcacc srcimm instoptions
740 i965_asm_set_dst_nr(p, &$6, $9);
741 brw_set_default_access_mode(p, $9.access_mode);
742 i965_asm_binary_instruction($2, p, $6, $7, $8);
743 brw_pop_insn_state(p);
744 i965_asm_set_instruction_options(p, $9);
745 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
748 if (p->devinfo->gen >= 7) {
749 if (!brw_inst_flag_reg_nr(p->devinfo, brw_last_inst)) {
750 brw_inst_set_flag_reg_nr(p->devinfo,
753 brw_inst_set_flag_subreg_nr(p->devinfo,
759 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
760 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
761 // TODO: set instruction group instead of qtr and nib ctrl
762 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
765 if (p->devinfo->gen >= 7)
766 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
786 /* Math instruction */
788 predicate MATH saturate math_function execsize dst src srcimm instoptions
790 brw_set_default_access_mode(p, $9.access_mode);
791 gen6_math(p, $6, $4, $7, $8);
792 i965_asm_set_instruction_options(p, $9);
793 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
794 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
795 // TODO: set instruction group instead
796 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
799 if (p->devinfo->gen >= 7)
800 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
803 brw_pop_insn_state(p);
825 /* NOP instruction */
833 /* Ternary operand instruction */
835 predicate ternaryopcodes saturate cond_mod execsize dst src src src instoptions
837 brw_set_default_access_mode(p, $10.access_mode);
838 i965_asm_ternary_instruction($2, p, $6, $7, $8, $9);
839 brw_pop_insn_state(p);
840 i965_asm_set_instruction_options(p, $10);
841 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst,
844 if (p->devinfo->gen >= 7) {
845 brw_inst_set_3src_a16_flag_reg_nr(p->devinfo, brw_last_inst,
847 brw_inst_set_3src_a16_flag_subreg_nr(p->devinfo, brw_last_inst,
851 brw_inst_set_saturate(p->devinfo, brw_last_inst, $3);
852 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $5);
853 // TODO: set instruction group instead of qtr and nib ctrl
854 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
857 if (p->devinfo->gen >= 7)
858 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
871 /* Sync instruction */
873 WAIT execsize src instoptions
875 brw_next_insn(p, $1);
876 i965_asm_set_instruction_options(p, $4);
877 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
878 brw_set_default_access_mode(p, $4.access_mode);
879 struct brw_reg src = brw_notification_reg();
880 brw_set_dest(p, brw_last_inst, src);
881 brw_set_src0(p, brw_last_inst, src);
882 brw_set_src1(p, brw_last_inst, brw_null_reg());
883 brw_inst_set_mask_control(p->devinfo, brw_last_inst, BRW_MASK_DISABLE);
887 /* Send instruction */
889 predicate sendopcode execsize dst payload exp2 sharedfunction instoptions
891 i965_asm_set_instruction_options(p, $8);
892 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
893 brw_set_dest(p, brw_last_inst, $4);
894 brw_set_src0(p, brw_last_inst, $5);
895 brw_inst_set_bits(brw_last_inst, 127, 96, $6);
896 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
898 BRW_REGISTER_TYPE_UD);
899 brw_inst_set_sfid(p->devinfo, brw_last_inst, $7);
900 brw_inst_set_eot(p->devinfo, brw_last_inst, $8.end_of_thread);
901 // TODO: set instruction group instead of qtr and nib ctrl
902 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
905 if (p->devinfo->gen >= 7)
906 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
909 brw_pop_insn_state(p);
911 | predicate sendopcode execsize exp dst payload exp2 sharedfunction instoptions
913 i965_asm_set_instruction_options(p, $9);
914 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
915 brw_inst_set_base_mrf(p->devinfo, brw_last_inst, $4);
916 brw_set_dest(p, brw_last_inst, $5);
917 brw_set_src0(p, brw_last_inst, $6);
918 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
919 brw_inst_set_src1_file_type(p->devinfo, brw_last_inst,
921 BRW_REGISTER_TYPE_UD);
922 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
923 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
924 // TODO: set instruction group instead of qtr and nib ctrl
925 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
928 if (p->devinfo->gen >= 7)
929 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
932 brw_pop_insn_state(p);
934 | predicate sendopcode execsize dst payload payload exp2 sharedfunction instoptions
936 i965_asm_set_instruction_options(p, $9);
937 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
938 brw_set_dest(p, brw_last_inst, $4);
939 brw_set_src0(p, brw_last_inst, $5);
940 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
941 brw_inst_set_sfid(p->devinfo, brw_last_inst, $8);
942 brw_inst_set_eot(p->devinfo, brw_last_inst, $9.end_of_thread);
943 // TODO: set instruction group instead of qtr and nib ctrl
944 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
947 if (p->devinfo->gen >= 7)
948 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
951 brw_pop_insn_state(p);
953 | predicate SENDS execsize dst payload payload exp2 exp2 sharedfunction instoptions
955 brw_next_insn(p, $2);
956 i965_asm_set_instruction_options(p, $10);
957 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
958 brw_set_dest(p, brw_last_inst, $4);
959 brw_set_src0(p, brw_last_inst, $5);
960 brw_set_src1(p, brw_last_inst, $6);
962 if (brw_inst_send_sel_reg32_ex_desc(p->devinfo, brw_last_inst)) {
963 brw_inst_set_send_ex_desc_ia_subreg_nr(p->devinfo, brw_last_inst, $5.subnr);
965 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
968 brw_inst_set_bits(brw_last_inst, 127, 96, $7);
969 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
970 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
971 // TODO: set instruction group instead of qtr and nib ctrl
972 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
975 if (p->devinfo->gen >= 7)
976 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
979 brw_pop_insn_state(p);
981 | predicate SENDS execsize dst payload payload src exp2 sharedfunction instoptions
983 brw_next_insn(p, $2);
984 i965_asm_set_instruction_options(p, $10);
985 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
986 brw_set_dest(p, brw_last_inst, $4);
987 brw_set_src0(p, brw_last_inst, $5);
988 brw_set_src1(p, brw_last_inst, $6);
990 brw_inst_set_send_sel_reg32_desc(p->devinfo, brw_last_inst, 1);
991 brw_inst_set_sends_ex_desc(p->devinfo, brw_last_inst, $8);
993 brw_inst_set_sfid(p->devinfo, brw_last_inst, $9);
994 brw_inst_set_eot(p->devinfo, brw_last_inst, $10.end_of_thread);
995 // TODO: set instruction group instead of qtr and nib ctrl
996 brw_inst_set_qtr_control(p->devinfo, brw_last_inst,
999 if (p->devinfo->gen >= 7)
1000 brw_inst_set_nib_control(p->devinfo, brw_last_inst,
1003 brw_pop_insn_state(p);
1013 sendop { $$ = brw_next_insn(p, $1); }
1017 NULL_TOKEN { $$ = BRW_SFID_NULL; }
1018 | MATH { $$ = BRW_SFID_MATH; }
1019 | GATEWAY { $$ = BRW_SFID_MESSAGE_GATEWAY; }
1020 | READ { $$ = BRW_SFID_DATAPORT_READ; }
1021 | WRITE { $$ = BRW_SFID_DATAPORT_WRITE; }
1022 | URB { $$ = BRW_SFID_URB; }
1023 | THREAD_SPAWNER { $$ = BRW_SFID_THREAD_SPAWNER; }
1024 | VME { $$ = BRW_SFID_VME; }
1025 | RENDER { $$ = GEN6_SFID_DATAPORT_RENDER_CACHE; }
1026 | CONST { $$ = GEN6_SFID_DATAPORT_CONSTANT_CACHE; }
1027 | DATA { $$ = GEN7_SFID_DATAPORT_DATA_CACHE; }
1028 | PIXEL_INTERP { $$ = GEN7_SFID_PIXEL_INTERPOLATOR; }
1029 | DP_DATA_1 { $$ = HSW_SFID_DATAPORT_DATA_CACHE_1; }
1030 | CRE { $$ = HSW_SFID_CRE; }
1031 | SAMPLER { $$ = BRW_SFID_SAMPLER; }
1032 | DP_SAMPLER { $$ = GEN6_SFID_DATAPORT_SAMPLER_CACHE; }
1037 | MINUS LONG { $$ = -$2; }
1040 /* Jump instruction */
1042 predicate JMPI execsize relativelocation2 instoptions
1044 brw_next_insn(p, $2);
1045 i965_asm_set_instruction_options(p, $5);
1046 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1047 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1048 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1049 brw_set_src1(p, brw_last_inst, $4);
1050 brw_inst_set_pred_control(p->devinfo, brw_last_inst,
1051 brw_inst_pred_control(p->devinfo,
1053 brw_pop_insn_state(p);
1057 /* branch instruction */
1059 predicate ENDIF execsize relativelocation instoptions
1061 brw_next_insn(p, $2);
1062 i965_asm_set_instruction_options(p, $5);
1063 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1065 if (p->devinfo->gen < 6) {
1066 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1067 BRW_REGISTER_TYPE_D));
1068 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1069 BRW_REGISTER_TYPE_D));
1070 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1071 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1073 } else if (p->devinfo->gen == 6) {
1074 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1075 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1077 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1078 BRW_REGISTER_TYPE_D));
1079 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1080 BRW_REGISTER_TYPE_D));
1081 } else if (p->devinfo->gen == 7) {
1082 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1083 BRW_REGISTER_TYPE_D));
1084 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1085 BRW_REGISTER_TYPE_D));
1086 brw_set_src1(p, brw_last_inst, brw_imm_w(0x0));
1087 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1089 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1092 if (p->devinfo->gen < 6)
1093 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1095 brw_pop_insn_state(p);
1097 | ELSE execsize relativelocation rellocation instoptions
1099 brw_next_insn(p, $1);
1100 i965_asm_set_instruction_options(p, $5);
1101 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1103 if (p->devinfo->gen < 6) {
1104 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1105 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1106 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1107 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1109 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1111 } else if (p->devinfo->gen == 6) {
1112 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1113 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1115 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1116 BRW_REGISTER_TYPE_D));
1117 brw_set_src1(p, brw_last_inst, retype(brw_null_reg(),
1118 BRW_REGISTER_TYPE_D));
1119 } else if (p->devinfo->gen == 7) {
1120 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1121 BRW_REGISTER_TYPE_D));
1122 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1123 BRW_REGISTER_TYPE_D));
1124 brw_set_src1(p, brw_last_inst, brw_imm_w($3));
1125 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1126 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1128 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1129 BRW_REGISTER_TYPE_D));
1130 brw_set_src0(p, brw_last_inst, brw_imm_d($3));
1131 brw_inst_set_jip(p->devinfo, brw_last_inst, $3);
1132 brw_inst_set_uip(p->devinfo, brw_last_inst, $4);
1135 if (!p->single_program_flow && p->devinfo->gen < 6)
1136 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1139 | predicate IF execsize relativelocation rellocation instoptions
1141 brw_next_insn(p, $2);
1142 i965_asm_set_instruction_options(p, $6);
1143 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1145 if (p->devinfo->gen < 6) {
1146 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1147 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1148 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1149 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1151 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1153 } else if (p->devinfo->gen == 6) {
1154 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1155 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1157 brw_set_src0(p, brw_last_inst,
1158 vec1(retype(brw_null_reg(),
1159 BRW_REGISTER_TYPE_D)));
1160 brw_set_src1(p, brw_last_inst,
1161 vec1(retype(brw_null_reg(),
1162 BRW_REGISTER_TYPE_D)));
1163 } else if (p->devinfo->gen == 7) {
1164 brw_set_dest(p, brw_last_inst,
1165 vec1(retype(brw_null_reg(),
1166 BRW_REGISTER_TYPE_D)));
1167 brw_set_src0(p, brw_last_inst,
1168 vec1(retype(brw_null_reg(),
1169 BRW_REGISTER_TYPE_D)));
1170 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1171 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1172 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1174 brw_set_dest(p, brw_last_inst,
1175 vec1(retype(brw_null_reg(),
1176 BRW_REGISTER_TYPE_D)));
1177 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1178 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1179 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1182 if (!p->single_program_flow && p->devinfo->gen < 6)
1183 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1186 brw_pop_insn_state(p);
1188 | predicate IFF execsize relativelocation instoptions
1190 brw_next_insn(p, $2);
1191 i965_asm_set_instruction_options(p, $5);
1192 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1194 if (p->devinfo->gen < 6) {
1195 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1196 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1197 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1199 brw_set_src1(p, brw_last_inst, brw_imm_d($4));
1200 } else if (p->devinfo->gen == 6) {
1201 brw_set_dest(p, brw_last_inst, brw_imm_w($4));
1202 brw_inst_set_gen6_jump_count(p->devinfo, brw_last_inst,
1204 brw_set_src0(p, brw_last_inst,
1205 vec1(retype(brw_null_reg(),
1206 BRW_REGISTER_TYPE_D)));
1207 brw_set_src1(p, brw_last_inst,
1208 vec1(retype(brw_null_reg(),
1209 BRW_REGISTER_TYPE_D)));
1210 } else if (p->devinfo->gen == 7) {
1211 brw_set_dest(p, brw_last_inst,
1212 vec1(retype(brw_null_reg(),
1213 BRW_REGISTER_TYPE_D)));
1214 brw_set_src0(p, brw_last_inst,
1215 vec1(retype(brw_null_reg(),
1216 BRW_REGISTER_TYPE_D)));
1217 brw_set_src1(p, brw_last_inst, brw_imm_w($4));
1218 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1220 brw_set_dest(p, brw_last_inst,
1221 vec1(retype(brw_null_reg(),
1222 BRW_REGISTER_TYPE_D)));
1223 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1224 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1227 if (!p->single_program_flow && p->devinfo->gen < 6)
1228 brw_inst_set_thread_control(p->devinfo, brw_last_inst,
1231 brw_pop_insn_state(p);
1235 /* break instruction */
1237 predicate BREAK execsize relativelocation relativelocation instoptions
1239 brw_next_insn(p, $2);
1240 i965_asm_set_instruction_options(p, $6);
1241 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1243 if (p->devinfo->gen >= 8) {
1244 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1245 BRW_REGISTER_TYPE_D));
1246 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1247 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1248 } else if (p->devinfo->gen >= 6) {
1249 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1250 BRW_REGISTER_TYPE_D));
1251 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1252 BRW_REGISTER_TYPE_D));
1253 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1254 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1255 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1257 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1258 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1259 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1260 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1262 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1266 brw_pop_insn_state(p);
1268 | predicate HALT execsize relativelocation relativelocation instoptions
1270 brw_next_insn(p, $2);
1271 i965_asm_set_instruction_options(p, $6);
1272 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1273 brw_set_dest(p, brw_last_inst, retype(brw_null_reg(),
1274 BRW_REGISTER_TYPE_D));
1276 if (p->devinfo->gen >= 8) {
1277 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1278 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1280 brw_set_src0(p, brw_last_inst, retype(brw_null_reg(),
1281 BRW_REGISTER_TYPE_D));
1282 brw_set_src1(p, brw_last_inst, brw_imm_d($5));
1285 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1286 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1287 brw_pop_insn_state(p);
1289 | predicate CONT execsize relativelocation relativelocation instoptions
1291 brw_next_insn(p, $2);
1292 i965_asm_set_instruction_options(p, $6);
1293 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1294 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1296 if (p->devinfo->gen >= 8) {
1297 brw_set_src0(p, brw_last_inst, brw_imm_d(0x0));
1298 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1299 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1301 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1302 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1303 if (p->devinfo->gen >= 6) {
1304 brw_inst_set_jip(p->devinfo, brw_last_inst, $4);
1305 brw_inst_set_uip(p->devinfo, brw_last_inst, $5);
1307 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1309 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1314 brw_pop_insn_state(p);
1318 /* loop instruction */
1320 predicate WHILE execsize relativelocation instoptions
1322 brw_next_insn(p, $2);
1323 i965_asm_set_instruction_options(p, $5);
1324 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $3);
1326 if (p->devinfo->gen >= 6) {
1327 if (p->devinfo->gen >= 8) {
1328 brw_set_dest(p, brw_last_inst,
1329 retype(brw_null_reg(),
1330 BRW_REGISTER_TYPE_D));
1331 brw_set_src0(p, brw_last_inst, brw_imm_d($4));
1332 } else if (p->devinfo->gen == 7) {
1333 brw_set_dest(p, brw_last_inst,
1334 retype(brw_null_reg(),
1335 BRW_REGISTER_TYPE_D));
1336 brw_set_src0(p, brw_last_inst,
1337 retype(brw_null_reg(),
1338 BRW_REGISTER_TYPE_D));
1339 brw_set_src1(p, brw_last_inst,
1341 brw_inst_set_jip(p->devinfo, brw_last_inst,
1344 brw_set_dest(p, brw_last_inst, brw_imm_w(0x0));
1345 brw_inst_set_gen6_jump_count(p->devinfo,
1348 brw_set_src0(p, brw_last_inst,
1349 retype(brw_null_reg(),
1350 BRW_REGISTER_TYPE_D));
1351 brw_set_src1(p, brw_last_inst,
1352 retype(brw_null_reg(),
1353 BRW_REGISTER_TYPE_D));
1356 brw_set_dest(p, brw_last_inst, brw_ip_reg());
1357 brw_set_src0(p, brw_last_inst, brw_ip_reg());
1358 brw_set_src1(p, brw_last_inst, brw_imm_d(0x0));
1359 brw_inst_set_gen4_jump_count(p->devinfo, brw_last_inst,
1361 brw_inst_set_gen4_pop_count(p->devinfo, brw_last_inst,
1364 brw_pop_insn_state(p);
1366 | DO execsize instoptions
1368 brw_next_insn(p, $1);
1369 if (p->devinfo->gen < 6) {
1370 brw_inst_set_exec_size(p->devinfo, brw_last_inst, $2);
1371 i965_asm_set_instruction_options(p, $3);
1372 brw_set_dest(p, brw_last_inst, brw_null_reg());
1373 brw_set_src0(p, brw_last_inst, brw_null_reg());
1374 brw_set_src1(p, brw_last_inst, brw_null_reg());
1376 brw_inst_set_qtr_control(p->devinfo, brw_last_inst, BRW_COMPRESSION_NONE);
1381 /* Relative location */
1388 INTEGER { $$ = $1; }
1389 | MINUS INTEGER { $$ = -$2; }
1391 | MINUS LONG { $$ = -$2; }
1396 | %empty { $$ = 0; }
1406 /* Destination register */
1413 dstreg dstregion writemask dsttype
1418 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1419 $$.vstride = BRW_VERTICAL_STRIDE_1;
1420 $$.width = BRW_WIDTH_1;
1425 $$.writemask = $3.writemask;
1426 $$.swizzle = BRW_SWIZZLE_NOOP;
1427 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1432 dstoperandex_typed dstregion writemask dsttype
1437 $$.writemask = $3.writemask;
1438 $$.subnr = $$.subnr * brw_reg_type_to_size($4.type);
1440 | dstoperandex_ud_typed
1444 $$.type = BRW_REGISTER_TYPE_UD;
1446 /* BSpec says "When the conditional modifier is present, updates
1447 * to the selected flag register also occur. In this case, the
1448 * register region fields of the ‘null’ operand are valid."
1450 | nullreg dstregion writemask dsttype
1454 $$.hstride = BRW_HORIZONTAL_STRIDE_1;
1455 $$.vstride = BRW_VERTICAL_STRIDE_1;
1456 $$.width = BRW_WIDTH_1;
1460 $$.writemask = $3.writemask;
1467 $$.type = BRW_REGISTER_TYPE_UW;
1471 dstoperandex_ud_typed:
1490 $$.address_mode = BRW_ADDRESS_DIRECT;
1495 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1500 $$.address_mode = BRW_ADDRESS_DIRECT;
1505 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1509 /* Source register */
1521 case BRW_REGISTER_TYPE_UD:
1523 $$ = brw_imm_ud(u32);
1525 case BRW_REGISTER_TYPE_D:
1528 case BRW_REGISTER_TYPE_UW:
1529 u32 = $1 | ($1 << 16);
1530 $$ = brw_imm_uw(u32);
1532 case BRW_REGISTER_TYPE_W:
1534 $$ = brw_imm_w(u32);
1536 case BRW_REGISTER_TYPE_F:
1537 $$ = brw_imm_reg(BRW_REGISTER_TYPE_F);
1541 case BRW_REGISTER_TYPE_V:
1544 case BRW_REGISTER_TYPE_UV:
1545 $$ = brw_imm_uv($1);
1547 case BRW_REGISTER_TYPE_VF:
1548 $$ = brw_imm_reg(BRW_REGISTER_TYPE_VF);
1551 case BRW_REGISTER_TYPE_Q:
1553 $$ = brw_imm_q(u64);
1555 case BRW_REGISTER_TYPE_UQ:
1557 $$ = brw_imm_uq(u64);
1559 case BRW_REGISTER_TYPE_DF:
1560 $$ = brw_imm_reg(BRW_REGISTER_TYPE_DF);
1564 error(&@2, "Unkown immdediate type %s\n",
1565 brw_reg_type_to_letters($2.type));
1571 directgenreg region srctype
1573 $$ = set_direct_src_operand(&$1, $3.type);
1574 $$ = stride($$, $2.vstride, $2.width, $2.hstride);
1584 | indirectsrcoperand
1589 | indirectsrcoperand
1594 | indirectsrcoperand
1598 directsrcaccoperand:
1600 | accreg region srctype
1602 $$ = set_direct_src_operand(&$1, $3.type);
1603 $$.vstride = $2.vstride;
1604 $$.width = $2.width;
1605 $$.hstride = $2.hstride;
1610 srcarcoperandex_typed region srctype
1612 $$ = brw_reg($1.file,
1624 | srcarcoperandex_ud_typed
1626 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UD);
1628 | nullreg region srctype
1630 $$ = set_direct_src_operand(&$1, $3.type);
1631 $$.vstride = $2.vstride;
1632 $$.width = $2.width;
1633 $$.hstride = $2.hstride;
1637 $$ = set_direct_src_operand(&$1, BRW_REGISTER_TYPE_UW);
1641 srcarcoperandex_ud_typed:
1648 srcarcoperandex_typed:
1654 negate abs indirectgenreg indirectregion swizzle srctype
1656 $$ = brw_reg($3.file,
1668 $$.address_mode = BRW_ADDRESS_REGISTER_INDIRECT_REGISTER;
1669 // brw_reg set indirect_offset to 0 so set it to valid value
1670 $$.indirect_offset = $3.indirect_offset;
1683 negate abs directgenreg_list region swizzle srctype
1685 $$ = brw_reg($3.file,
1700 /* Address register */
1704 memset(&$$, '\0', sizeof($$));
1705 $$.subnr = $1.subnr;
1706 $$.indirect_offset = $2;
1711 /* Register files and register numbers */
1713 INTEGER { $$ = $1; }
1718 DOT exp { $$ = $2; }
1719 | %empty %prec SUBREGNUM { $$ = 0; }
1725 memset(&$$, '\0', sizeof($$));
1726 $$.file = BRW_GENERAL_REGISTER_FILE;
1733 GENREGFILE LSQUARE addrparam RSQUARE
1735 memset(&$$, '\0', sizeof($$));
1736 $$.file = BRW_GENERAL_REGISTER_FILE;
1737 $$.subnr = $3.subnr;
1738 $$.indirect_offset = $3.indirect_offset;
1745 $$ = brw_message_reg($1);
1751 MSGREGFILE LSQUARE addrparam RSQUARE
1753 memset(&$$, '\0', sizeof($$));
1754 $$.file = BRW_MESSAGE_REGISTER_FILE;
1755 $$.subnr = $3.subnr;
1756 $$.indirect_offset = $3.indirect_offset;
1764 error(&@1, "Address register number %d"
1765 "out of range\n", $1);
1767 int subnr = (p->devinfo->gen >= 8) ? 16 : 8;
1770 error(&@2, "Address sub resgister number %d"
1771 "out of range\n", $2);
1773 $$ = brw_address_reg($2);
1781 if (p->devinfo->gen < 8)
1787 error(&@1, "Accumulator register number %d"
1788 " out of range\n", $1);
1790 memset(&$$, '\0', sizeof($$));
1791 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1792 $$.nr = BRW_ARF_ACCUMULATOR;
1800 // SNB = 1 flag reg and IVB+ = 2 flag reg
1801 int nr_reg = (p->devinfo->gen >= 7) ? 2 : 1;
1805 error(&@1, "Flag register number %d"
1806 " out of range \n", $1);
1808 error(&@2, "Flag subregister number %d"
1809 " out of range\n", $2);
1811 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1812 $$.nr = BRW_ARF_FLAG | $1;
1821 error(&@1, "Mask register number %d"
1822 " out of range\n", $1);
1824 $$ = brw_mask_reg($2);
1832 error(&@1, "Notification register number %d"
1833 " out of range\n", $1);
1835 int subnr = (p->devinfo->gen >= 11) ? 2 : 3;
1837 error(&@2, "Notification sub register number %d"
1838 " out of range\n", $2);
1840 $$ = brw_notification_reg();
1849 error(&@1, "State register number %d"
1850 " out of range\n", $1);
1853 error(&@2, "State sub register number %d"
1854 " out of range\n", $2);
1856 $$ = brw_sr0_reg($2);
1862 CONTROLREG subregnum
1865 error(&@1, "Control register number %d"
1866 " out of range\n", $1);
1869 error(&@2, "control sub register number %d"
1870 " out of range\n", $2);
1872 $$ = brw_cr0_reg($2);
1878 IPREG srctype { $$ = brw_ip_reg(); }
1882 NULL_TOKEN { $$ = brw_null_reg(); }
1889 error(&@1, "Thread control register number %d"
1890 " out of range\n", $1);
1893 error(&@2, "Thread control sub register number %d"
1894 " out of range\n", $2);
1902 PERFORMANCEREG subregnum
1905 if (p->devinfo->gen >= 10)
1907 else if (p->devinfo->gen <= 8)
1913 error(&@2, "Performance sub register number %d"
1914 " out of range\n", $2);
1916 $$.file = BRW_ARCHITECTURE_REGISTER_FILE;
1917 $$.nr = BRW_ARF_TIMESTAMP;
1922 CHANNELENABLEREG subregnum
1925 error(&@1, "Channel enable register number %d"
1926 " out of range\n", $1);
1928 $$ = brw_mask_reg($2);
1932 /* Immediate values */
1938 | LSQUARE exp2 COMMA exp2 COMMA exp2 COMMA exp2 RSQUARE
1940 $$ = ($2 << 0) | ($4 << 8) | ($6 << 16) | ($8 << 24);
1949 if ($2 != 0 && ($2 > 4 || !isPowerofTwo($2)))
1950 error(&@2, "Invalid Horizontal stride %d\n", $2);
1964 $$ = stride($$, BRW_VERTICAL_STRIDE_1, BRW_WIDTH_2, BRW_HORIZONTAL_STRIDE_1);
1968 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1969 error(&@2, "Invalid VertStride %d\n", $2);
1971 $$ = stride($$, $2, BRW_WIDTH_1, 0);
1973 | LANGLE exp COMMA exp COMMA exp RANGLE
1976 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1977 error(&@2, "Invalid VertStride %d\n", $2);
1979 if ($4 > 16 || !isPowerofTwo($4))
1980 error(&@4, "Invalid width %d\n", $4);
1982 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1983 error(&@6, "Invalid Horizontal stride in"
1984 " region_wh %d\n", $6);
1986 $$ = stride($$, $2, $4, $6);
1988 | LANGLE exp SEMICOLON exp COMMA exp RANGLE
1990 if ($2 != 0 && ($2 > 32 || !isPowerofTwo($2)))
1991 error(&@2, "Invalid VertStride %d\n", $2);
1993 if ($4 > 16 || !isPowerofTwo($4))
1994 error(&@4, "Invalid width %d\n", $4);
1996 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
1997 error(&@6, "Invalid Horizontal stride in"
1998 " region_wh %d\n", $6);
2000 $$ = stride($$, $2, $4, $6);
2002 | LANGLE VxH COMMA exp COMMA exp RANGLE
2004 if ($4 > 16 || !isPowerofTwo($4))
2005 error(&@4, "Invalid width %d\n", $4);
2007 if ($6 != 0 && ($6 > 4 || !isPowerofTwo($6)))
2008 error(&@6, "Invalid Horizontal stride in"
2009 " region_wh %d\n", $6);
2011 $$ = brw_VxH_indirect(0, 0);
2016 LANGLE exp COMMA exp RANGLE
2018 if ($2 > 16 || !isPowerofTwo($2))
2019 error(&@2, "Invalid width %d\n", $2);
2021 if ($4 != 0 && ($4 > 4 || !isPowerofTwo($4)))
2022 error(&@4, "Invalid Horizontal stride in"
2023 " region_wh %d\n", $4);
2025 $$ = stride($$, BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL, $2, $4);
2030 %empty { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2031 | TYPE_F { $$ = retype($$, BRW_REGISTER_TYPE_F); }
2032 | TYPE_UD { $$ = retype($$, BRW_REGISTER_TYPE_UD); }
2033 | TYPE_D { $$ = retype($$, BRW_REGISTER_TYPE_D); }
2034 | TYPE_UW { $$ = retype($$, BRW_REGISTER_TYPE_UW); }
2035 | TYPE_W { $$ = retype($$, BRW_REGISTER_TYPE_W); }
2036 | TYPE_UB { $$ = retype($$, BRW_REGISTER_TYPE_UB); }
2037 | TYPE_B { $$ = retype($$, BRW_REGISTER_TYPE_B); }
2038 | TYPE_DF { $$ = retype($$, BRW_REGISTER_TYPE_DF); }
2039 | TYPE_UQ { $$ = retype($$, BRW_REGISTER_TYPE_UQ); }
2040 | TYPE_Q { $$ = retype($$, BRW_REGISTER_TYPE_Q); }
2041 | TYPE_HF { $$ = retype($$, BRW_REGISTER_TYPE_HF); }
2042 | TYPE_NF { $$ = retype($$, BRW_REGISTER_TYPE_NF); }
2046 srctype { $$ = $1; }
2047 | TYPE_V { $$ = retype($$, BRW_REGISTER_TYPE_V); }
2048 | TYPE_VF { $$ = retype($$, BRW_REGISTER_TYPE_VF); }
2049 | TYPE_UV { $$ = retype($$, BRW_REGISTER_TYPE_UV); }
2053 srctype { $$ = $1; }
2059 $$= brw_set_writemask($$, WRITEMASK_XYZW);
2061 | DOT writemask_x writemask_y writemask_z writemask_w
2063 $$ = brw_set_writemask($$, $2 | $3 | $4 | $5);
2069 | X { $$ = 1 << BRW_CHANNEL_X; }
2074 | Y { $$ = 1 << BRW_CHANNEL_Y; }
2079 | Z { $$ = 1 << BRW_CHANNEL_Z; }
2084 | W { $$ = 1 << BRW_CHANNEL_W; }
2090 $$.swizzle = BRW_SWIZZLE_NOOP;
2094 $$.swizzle = BRW_SWIZZLE4($2, $2, $2, $2);
2096 | DOT chansel chansel chansel chansel
2098 $$.swizzle = BRW_SWIZZLE4($2, $3, $4, $5);
2109 /* Instruction prediction and modifiers */
2113 brw_push_insn_state(p);
2114 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2115 brw_set_default_flag_reg(p, 0, 0);
2116 brw_set_default_predicate_inverse(p, false);
2118 | LPAREN predstate flagreg predctrl RPAREN
2120 brw_push_insn_state(p);
2121 brw_set_default_predicate_inverse(p, $2);
2122 brw_set_default_flag_reg(p, $3.nr, $3.subnr);
2123 brw_set_default_predicate_control(p, $4);
2134 %empty { $$ = BRW_PREDICATE_NORMAL; }
2135 | DOT X { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_X; }
2136 | DOT Y { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Y; }
2137 | DOT Z { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_Z; }
2138 | DOT W { $$ = BRW_PREDICATE_ALIGN16_REPLICATE_W; }
2153 /* Source Modification */
2164 /* Flag (Conditional) Modifier */
2168 $$.cond_modifier = $1;
2170 $$.flag_subreg_nr = 0;
2172 | condModifiers DOT flagreg
2174 $$.cond_modifier = $1;
2175 $$.flag_reg_nr = $3.nr;
2176 $$.flag_subreg_nr = $3.subnr;
2181 %empty { $$ = BRW_CONDITIONAL_NONE; }
2196 %empty { $$ = BRW_INSTRUCTION_NORMAL; }
2197 | SATURATE { $$ = BRW_INSTRUCTION_SATURATE; }
2200 /* Execution size */
2202 %empty %prec EMPTYEXECSIZE
2206 | LPAREN exp2 RPAREN
2208 if ($2 > 32 || !isPowerofTwo($2))
2209 error(&@2, "Invalid execution size %d\n", $2);
2215 /* Instruction options */
2219 memset(&$$, 0, sizeof($$));
2221 | LCURLY instoption_list RCURLY
2223 memset(&$$, 0, sizeof($$));
2229 instoption_list COMMA instoption
2231 memset(&$$, 0, sizeof($$));
2233 add_instruction_option(&$$, $3);
2235 | instoption_list instoption
2237 memset(&$$, 0, sizeof($$));
2239 add_instruction_option(&$$, $2);
2243 memset(&$$, 0, sizeof($$));
2248 ALIGN1 { $$ = ALIGN1;}
2249 | ALIGN16 { $$ = ALIGN16; }
2250 | ACCWREN { $$ = ACCWREN; }
2251 | SECHALF { $$ = SECHALF; }
2252 | COMPR { $$ = COMPR; }
2253 | COMPR4 { $$ = COMPR4; }
2254 | BREAKPOINT { $$ = BREAKPOINT; }
2255 | NODDCLR { $$ = NODDCLR; }
2256 | NODDCHK { $$ = NODDCHK; }
2257 | MASK_DISABLE { $$ = MASK_DISABLE; }
2259 | SWITCH { $$ = SWITCH; }
2260 | ATOMIC { $$ = ATOMIC; }
2261 | CMPTCTRL { $$ = CMPTCTRL; }
2262 | WECTRL { $$ = WECTRL; }
2263 | QTR_2Q { $$ = QTR_2Q; }
2264 | QTR_3Q { $$ = QTR_3Q; }
2265 | QTR_4Q { $$ = QTR_4Q; }
2266 | QTR_2H { $$ = QTR_2H; }
2267 | QTR_2N { $$ = QTR_2N; }
2268 | QTR_3N { $$ = QTR_3N; }
2269 | QTR_4N { $$ = QTR_4N; }
2270 | QTR_5N { $$ = QTR_5N; }
2271 | QTR_6N { $$ = QTR_6N; }
2272 | QTR_7N { $$ = QTR_7N; }
2273 | QTR_8N { $$ = QTR_8N; }
2278 extern int yylineno;
2283 fprintf(stderr, "%s: %d: %s at \"%s\"\n",
2284 input_filename, yylineno, msg, lex_text());