2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
27 lookup_blorp_shader(struct blorp_context
*blorp
,
28 const void *key
, uint32_t key_size
,
29 uint32_t *kernel_out
, void *prog_data_out
)
31 struct anv_device
*device
= blorp
->driver_ctx
;
33 /* The blorp cache must be a real cache */
34 assert(device
->blorp_shader_cache
.cache
);
36 struct anv_shader_bin
*bin
=
37 anv_pipeline_cache_search(&device
->blorp_shader_cache
, key
, key_size
);
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
44 anv_shader_bin_unref(device
, bin
);
46 *kernel_out
= bin
->kernel
.offset
;
47 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
53 upload_blorp_shader(struct blorp_context
*blorp
,
54 const void *key
, uint32_t key_size
,
55 const void *kernel
, uint32_t kernel_size
,
56 const struct brw_stage_prog_data
*prog_data
,
57 uint32_t prog_data_size
,
58 uint32_t *kernel_out
, void *prog_data_out
)
60 struct anv_device
*device
= blorp
->driver_ctx
;
62 /* The blorp cache must be a real cache */
63 assert(device
->blorp_shader_cache
.cache
);
65 struct anv_pipeline_bind_map bind_map
= {
70 struct anv_shader_bin
*bin
=
71 anv_pipeline_cache_upload_kernel(&device
->blorp_shader_cache
,
72 key
, key_size
, kernel
, kernel_size
,
73 prog_data
, prog_data_size
, &bind_map
);
75 /* The cache already has a reference and it's not going anywhere so there
76 * is no need to hold a second reference.
78 anv_shader_bin_unref(device
, bin
);
80 *kernel_out
= bin
->kernel
.offset
;
81 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
85 anv_device_init_blorp(struct anv_device
*device
)
87 anv_pipeline_cache_init(&device
->blorp_shader_cache
, device
, true);
88 blorp_init(&device
->blorp
, device
, &device
->isl_dev
);
89 device
->blorp
.compiler
= device
->instance
->physicalDevice
.compiler
;
90 device
->blorp
.mocs
.tex
= device
->default_mocs
;
91 device
->blorp
.mocs
.rb
= device
->default_mocs
;
92 device
->blorp
.mocs
.vb
= device
->default_mocs
;
93 device
->blorp
.lookup_shader
= lookup_blorp_shader
;
94 device
->blorp
.upload_shader
= upload_blorp_shader
;
95 switch (device
->info
.gen
) {
97 if (device
->info
.is_haswell
) {
98 device
->blorp
.exec
= gen75_blorp_exec
;
100 device
->blorp
.exec
= gen7_blorp_exec
;
104 device
->blorp
.exec
= gen8_blorp_exec
;
107 device
->blorp
.exec
= gen9_blorp_exec
;
110 unreachable("Unknown hardware generation");
115 anv_device_finish_blorp(struct anv_device
*device
)
117 blorp_finish(&device
->blorp
);
118 anv_pipeline_cache_finish(&device
->blorp_shader_cache
);
122 get_blorp_surf_for_anv_buffer(struct anv_device
*device
,
123 struct anv_buffer
*buffer
, uint64_t offset
,
124 uint32_t width
, uint32_t height
,
125 uint32_t row_pitch
, enum isl_format format
,
126 struct blorp_surf
*blorp_surf
,
127 struct isl_surf
*isl_surf
)
129 const struct isl_format_layout
*fmtl
=
130 isl_format_get_layout(format
);
132 /* ASTC is the only format which doesn't support linear layouts.
133 * Create an equivalently sized surface with ISL to get around this.
135 if (fmtl
->txc
== ISL_TXC_ASTC
) {
136 /* Use an equivalently sized format */
137 format
= ISL_FORMAT_R32G32B32A32_UINT
;
138 assert(fmtl
->bpb
== isl_format_get_layout(format
)->bpb
);
140 /* Shrink the dimensions for the new format */
141 width
= DIV_ROUND_UP(width
, fmtl
->bw
);
142 height
= DIV_ROUND_UP(height
, fmtl
->bh
);
145 *blorp_surf
= (struct blorp_surf
) {
148 .buffer
= buffer
->bo
,
149 .offset
= buffer
->offset
+ offset
,
153 isl_surf_init(&device
->isl_dev
, isl_surf
,
154 .dim
= ISL_SURF_DIM_2D
,
162 .min_pitch
= row_pitch
,
163 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
164 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
165 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
166 assert(isl_surf
->row_pitch
== row_pitch
);
170 get_blorp_surf_for_anv_image(const struct anv_image
*image
,
171 VkImageAspectFlags aspect
,
172 enum isl_aux_usage aux_usage
,
173 struct blorp_surf
*blorp_surf
)
175 if (aspect
== VK_IMAGE_ASPECT_STENCIL_BIT
)
176 aux_usage
= ISL_AUX_USAGE_NONE
;
178 const struct anv_surface
*surface
=
179 anv_image_get_surface_for_aspect_mask(image
, aspect
);
181 *blorp_surf
= (struct blorp_surf
) {
182 .surf
= &surface
->isl
,
185 .offset
= image
->offset
+ surface
->offset
,
189 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
190 blorp_surf
->aux_surf
= &image
->aux_surface
.isl
,
191 blorp_surf
->aux_addr
= (struct blorp_address
) {
193 .offset
= image
->offset
+ image
->aux_surface
.offset
,
195 blorp_surf
->aux_usage
= aux_usage
;
199 void anv_CmdCopyImage(
200 VkCommandBuffer commandBuffer
,
202 VkImageLayout srcImageLayout
,
204 VkImageLayout dstImageLayout
,
205 uint32_t regionCount
,
206 const VkImageCopy
* pRegions
)
208 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
209 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
210 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
212 struct blorp_batch batch
;
213 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
215 for (unsigned r
= 0; r
< regionCount
; r
++) {
216 VkOffset3D srcOffset
=
217 anv_sanitize_image_offset(src_image
->type
, pRegions
[r
].srcOffset
);
218 VkOffset3D dstOffset
=
219 anv_sanitize_image_offset(dst_image
->type
, pRegions
[r
].dstOffset
);
221 anv_sanitize_image_extent(src_image
->type
, pRegions
[r
].extent
);
223 unsigned dst_base_layer
, layer_count
;
224 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
225 dst_base_layer
= pRegions
[r
].dstOffset
.z
;
226 layer_count
= pRegions
[r
].extent
.depth
;
228 dst_base_layer
= pRegions
[r
].dstSubresource
.baseArrayLayer
;
229 layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
232 unsigned src_base_layer
;
233 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
234 src_base_layer
= pRegions
[r
].srcOffset
.z
;
236 src_base_layer
= pRegions
[r
].srcSubresource
.baseArrayLayer
;
237 assert(pRegions
[r
].srcSubresource
.layerCount
== layer_count
);
240 assert(pRegions
[r
].srcSubresource
.aspectMask
==
241 pRegions
[r
].dstSubresource
.aspectMask
);
244 for_each_bit(a
, pRegions
[r
].dstSubresource
.aspectMask
) {
245 VkImageAspectFlagBits aspect
= (1 << a
);
247 struct blorp_surf src_surf
, dst_surf
;
248 get_blorp_surf_for_anv_image(src_image
, aspect
, src_image
->aux_usage
,
250 get_blorp_surf_for_anv_image(dst_image
, aspect
, dst_image
->aux_usage
,
253 for (unsigned i
= 0; i
< layer_count
; i
++) {
254 blorp_copy(&batch
, &src_surf
, pRegions
[r
].srcSubresource
.mipLevel
,
256 &dst_surf
, pRegions
[r
].dstSubresource
.mipLevel
,
258 srcOffset
.x
, srcOffset
.y
,
259 dstOffset
.x
, dstOffset
.y
,
260 extent
.width
, extent
.height
);
265 blorp_batch_finish(&batch
);
269 copy_buffer_to_image(struct anv_cmd_buffer
*cmd_buffer
,
270 struct anv_buffer
*anv_buffer
,
271 struct anv_image
*anv_image
,
272 uint32_t regionCount
,
273 const VkBufferImageCopy
* pRegions
,
274 bool buffer_to_image
)
276 struct blorp_batch batch
;
277 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
280 struct blorp_surf surf
;
283 } image
, buffer
, *src
, *dst
;
286 buffer
.offset
= (VkOffset3D
) { 0, 0, 0 };
288 if (buffer_to_image
) {
296 for (unsigned r
= 0; r
< regionCount
; r
++) {
297 const VkImageAspectFlags aspect
= pRegions
[r
].imageSubresource
.aspectMask
;
299 get_blorp_surf_for_anv_image(anv_image
, aspect
, anv_image
->aux_usage
,
302 anv_sanitize_image_offset(anv_image
->type
, pRegions
[r
].imageOffset
);
303 image
.level
= pRegions
[r
].imageSubresource
.mipLevel
;
306 anv_sanitize_image_extent(anv_image
->type
, pRegions
[r
].imageExtent
);
307 if (anv_image
->type
!= VK_IMAGE_TYPE_3D
) {
308 image
.offset
.z
= pRegions
[r
].imageSubresource
.baseArrayLayer
;
309 extent
.depth
= pRegions
[r
].imageSubresource
.layerCount
;
312 const enum isl_format buffer_format
=
313 anv_get_isl_format(&cmd_buffer
->device
->info
, anv_image
->vk_format
,
314 aspect
, VK_IMAGE_TILING_LINEAR
);
316 const VkExtent3D bufferImageExtent
= {
317 .width
= pRegions
[r
].bufferRowLength
?
318 pRegions
[r
].bufferRowLength
: extent
.width
,
319 .height
= pRegions
[r
].bufferImageHeight
?
320 pRegions
[r
].bufferImageHeight
: extent
.height
,
323 const struct isl_format_layout
*buffer_fmtl
=
324 isl_format_get_layout(buffer_format
);
326 const uint32_t buffer_row_pitch
=
327 DIV_ROUND_UP(bufferImageExtent
.width
, buffer_fmtl
->bw
) *
328 (buffer_fmtl
->bpb
/ 8);
330 const uint32_t buffer_layer_stride
=
331 DIV_ROUND_UP(bufferImageExtent
.height
, buffer_fmtl
->bh
) *
334 struct isl_surf buffer_isl_surf
;
335 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
336 anv_buffer
, pRegions
[r
].bufferOffset
,
337 extent
.width
, extent
.height
,
338 buffer_row_pitch
, buffer_format
,
339 &buffer
.surf
, &buffer_isl_surf
);
341 for (unsigned z
= 0; z
< extent
.depth
; z
++) {
342 blorp_copy(&batch
, &src
->surf
, src
->level
, src
->offset
.z
,
343 &dst
->surf
, dst
->level
, dst
->offset
.z
,
344 src
->offset
.x
, src
->offset
.y
, dst
->offset
.x
, dst
->offset
.y
,
345 extent
.width
, extent
.height
);
348 buffer
.surf
.addr
.offset
+= buffer_layer_stride
;
352 blorp_batch_finish(&batch
);
355 void anv_CmdCopyBufferToImage(
356 VkCommandBuffer commandBuffer
,
359 VkImageLayout dstImageLayout
,
360 uint32_t regionCount
,
361 const VkBufferImageCopy
* pRegions
)
363 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
364 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
365 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
367 copy_buffer_to_image(cmd_buffer
, src_buffer
, dst_image
,
368 regionCount
, pRegions
, true);
371 void anv_CmdCopyImageToBuffer(
372 VkCommandBuffer commandBuffer
,
374 VkImageLayout srcImageLayout
,
376 uint32_t regionCount
,
377 const VkBufferImageCopy
* pRegions
)
379 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
380 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
381 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
383 copy_buffer_to_image(cmd_buffer
, dst_buffer
, src_image
,
384 regionCount
, pRegions
, false);
388 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
392 unsigned tmp
= *src0
;
399 unsigned tmp
= *dst0
;
408 void anv_CmdBlitImage(
409 VkCommandBuffer commandBuffer
,
411 VkImageLayout srcImageLayout
,
413 VkImageLayout dstImageLayout
,
414 uint32_t regionCount
,
415 const VkImageBlit
* pRegions
,
419 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
420 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
421 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
423 struct blorp_surf src
, dst
;
427 case VK_FILTER_NEAREST
:
428 gl_filter
= 0x2600; /* GL_NEAREST */
430 case VK_FILTER_LINEAR
:
431 gl_filter
= 0x2601; /* GL_LINEAR */
434 unreachable("Invalid filter");
437 struct blorp_batch batch
;
438 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
440 for (unsigned r
= 0; r
< regionCount
; r
++) {
441 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
442 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
444 get_blorp_surf_for_anv_image(src_image
, src_res
->aspectMask
,
445 src_image
->aux_usage
, &src
);
446 get_blorp_surf_for_anv_image(dst_image
, dst_res
->aspectMask
,
447 dst_image
->aux_usage
, &dst
);
449 struct anv_format src_format
=
450 anv_get_format(&cmd_buffer
->device
->info
, src_image
->vk_format
,
451 src_res
->aspectMask
, src_image
->tiling
);
452 struct anv_format dst_format
=
453 anv_get_format(&cmd_buffer
->device
->info
, dst_image
->vk_format
,
454 dst_res
->aspectMask
, dst_image
->tiling
);
456 unsigned dst_start
, dst_end
;
457 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
458 assert(dst_res
->baseArrayLayer
== 0);
459 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
460 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
462 dst_start
= dst_res
->baseArrayLayer
;
463 dst_end
= dst_start
+ dst_res
->layerCount
;
466 unsigned src_start
, src_end
;
467 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
468 assert(src_res
->baseArrayLayer
== 0);
469 src_start
= pRegions
[r
].srcOffsets
[0].z
;
470 src_end
= pRegions
[r
].srcOffsets
[1].z
;
472 src_start
= src_res
->baseArrayLayer
;
473 src_end
= src_start
+ src_res
->layerCount
;
476 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
477 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
478 (float)(dst_end
+ 1 - dst_start
);
485 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
486 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
487 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
488 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
489 bool flip_x
= flip_coords(&src_x0
, &src_x1
, &dst_x0
, &dst_x1
);
491 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
492 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
493 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
494 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
495 bool flip_y
= flip_coords(&src_y0
, &src_y1
, &dst_y0
, &dst_y1
);
497 const unsigned num_layers
= dst_end
- dst_start
;
498 for (unsigned i
= 0; i
< num_layers
; i
++) {
499 unsigned dst_z
= dst_start
+ i
;
500 unsigned src_z
= src_start
+ i
* src_z_step
;
502 blorp_blit(&batch
, &src
, src_res
->mipLevel
, src_z
,
503 src_format
.isl_format
, src_format
.swizzle
,
504 &dst
, dst_res
->mipLevel
, dst_z
,
505 dst_format
.isl_format
, dst_format
.swizzle
,
506 src_x0
, src_y0
, src_x1
, src_y1
,
507 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
508 gl_filter
, flip_x
, flip_y
);
513 blorp_batch_finish(&batch
);
516 static enum isl_format
517 isl_format_for_size(unsigned size_B
)
520 case 1: return ISL_FORMAT_R8_UINT
;
521 case 2: return ISL_FORMAT_R8G8_UINT
;
522 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
523 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
524 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
526 unreachable("Not a power-of-two format size");
531 do_buffer_copy(struct blorp_batch
*batch
,
532 struct anv_bo
*src
, uint64_t src_offset
,
533 struct anv_bo
*dst
, uint64_t dst_offset
,
534 int width
, int height
, int block_size
)
536 struct anv_device
*device
= batch
->blorp
->driver_ctx
;
538 /* The actual format we pick doesn't matter as blorp will throw it away.
539 * The only thing that actually matters is the size.
541 enum isl_format format
= isl_format_for_size(block_size
);
543 struct isl_surf surf
;
544 isl_surf_init(&device
->isl_dev
, &surf
,
545 .dim
= ISL_SURF_DIM_2D
,
553 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
554 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
555 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
556 assert(surf
.row_pitch
== width
* block_size
);
558 struct blorp_surf src_blorp_surf
= {
562 .offset
= src_offset
,
566 struct blorp_surf dst_blorp_surf
= {
570 .offset
= dst_offset
,
574 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
575 0, 0, 0, 0, width
, height
);
579 * Returns the greatest common divisor of a and b that is a power of two.
581 static inline uint64_t
582 gcd_pow2_u64(uint64_t a
, uint64_t b
)
584 assert(a
> 0 || b
> 0);
586 unsigned a_log2
= ffsll(a
) - 1;
587 unsigned b_log2
= ffsll(b
) - 1;
589 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
590 * case, the MIN2() will take the other one. If both are 0 then we will
591 * hit the assert above.
593 return 1 << MIN2(a_log2
, b_log2
);
596 /* This is maximum possible width/height our HW can handle */
597 #define MAX_SURFACE_DIM (1ull << 14)
599 void anv_CmdCopyBuffer(
600 VkCommandBuffer commandBuffer
,
603 uint32_t regionCount
,
604 const VkBufferCopy
* pRegions
)
606 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
607 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
608 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
610 struct blorp_batch batch
;
611 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
613 for (unsigned r
= 0; r
< regionCount
; r
++) {
614 uint64_t src_offset
= src_buffer
->offset
+ pRegions
[r
].srcOffset
;
615 uint64_t dst_offset
= dst_buffer
->offset
+ pRegions
[r
].dstOffset
;
616 uint64_t copy_size
= pRegions
[r
].size
;
618 /* First, we compute the biggest format that can be used with the
619 * given offsets and size.
622 bs
= gcd_pow2_u64(bs
, src_offset
);
623 bs
= gcd_pow2_u64(bs
, dst_offset
);
624 bs
= gcd_pow2_u64(bs
, pRegions
[r
].size
);
626 /* First, we make a bunch of max-sized copies */
627 uint64_t max_copy_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
628 while (copy_size
>= max_copy_size
) {
629 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
630 dst_buffer
->bo
, dst_offset
,
631 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
, bs
);
632 copy_size
-= max_copy_size
;
633 src_offset
+= max_copy_size
;
634 dst_offset
+= max_copy_size
;
637 /* Now make a max-width copy */
638 uint64_t height
= copy_size
/ (MAX_SURFACE_DIM
* bs
);
639 assert(height
< MAX_SURFACE_DIM
);
641 uint64_t rect_copy_size
= height
* MAX_SURFACE_DIM
* bs
;
642 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
643 dst_buffer
->bo
, dst_offset
,
644 MAX_SURFACE_DIM
, height
, bs
);
645 copy_size
-= rect_copy_size
;
646 src_offset
+= rect_copy_size
;
647 dst_offset
+= rect_copy_size
;
650 /* Finally, make a small copy to finish it off */
651 if (copy_size
!= 0) {
652 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
653 dst_buffer
->bo
, dst_offset
,
654 copy_size
/ bs
, 1, bs
);
658 blorp_batch_finish(&batch
);
661 void anv_CmdUpdateBuffer(
662 VkCommandBuffer commandBuffer
,
664 VkDeviceSize dstOffset
,
665 VkDeviceSize dataSize
,
668 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
669 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
671 struct blorp_batch batch
;
672 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
674 /* We can't quite grab a full block because the state stream needs a
675 * little data at the top to build its linked list.
677 const uint32_t max_update_size
=
678 cmd_buffer
->device
->dynamic_state_block_pool
.block_size
- 64;
680 assert(max_update_size
< MAX_SURFACE_DIM
* 4);
683 const uint32_t copy_size
= MIN2(dataSize
, max_update_size
);
685 struct anv_state tmp_data
=
686 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, copy_size
, 64);
688 memcpy(tmp_data
.map
, pData
, copy_size
);
691 bs
= gcd_pow2_u64(bs
, dstOffset
);
692 bs
= gcd_pow2_u64(bs
, copy_size
);
694 do_buffer_copy(&batch
,
695 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
697 dst_buffer
->bo
, dst_buffer
->offset
+ dstOffset
,
698 copy_size
/ bs
, 1, bs
);
700 dataSize
-= copy_size
;
701 dstOffset
+= copy_size
;
702 pData
= (void *)pData
+ copy_size
;
705 blorp_batch_finish(&batch
);
708 void anv_CmdFillBuffer(
709 VkCommandBuffer commandBuffer
,
711 VkDeviceSize dstOffset
,
712 VkDeviceSize fillSize
,
715 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
716 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
717 struct blorp_surf surf
;
718 struct isl_surf isl_surf
;
720 struct blorp_batch batch
;
721 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
723 if (fillSize
== VK_WHOLE_SIZE
) {
724 fillSize
= dst_buffer
->size
- dstOffset
;
725 /* Make sure fillSize is a multiple of 4 */
729 /* First, we compute the biggest format that can be used with the
730 * given offsets and size.
733 bs
= gcd_pow2_u64(bs
, dstOffset
);
734 bs
= gcd_pow2_u64(bs
, fillSize
);
735 enum isl_format isl_format
= isl_format_for_size(bs
);
737 union isl_color_value color
= {
738 .u32
= { data
, data
, data
, data
},
741 const uint64_t max_fill_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
742 while (fillSize
>= max_fill_size
) {
743 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
744 dst_buffer
, dstOffset
,
745 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
746 MAX_SURFACE_DIM
* bs
, isl_format
,
749 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
750 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
752 fillSize
-= max_fill_size
;
753 dstOffset
+= max_fill_size
;
756 uint64_t height
= fillSize
/ (MAX_SURFACE_DIM
* bs
);
757 assert(height
< MAX_SURFACE_DIM
);
759 const uint64_t rect_fill_size
= height
* MAX_SURFACE_DIM
* bs
;
760 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
761 dst_buffer
, dstOffset
,
762 MAX_SURFACE_DIM
, height
,
763 MAX_SURFACE_DIM
* bs
, isl_format
,
766 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
767 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, height
,
769 fillSize
-= rect_fill_size
;
770 dstOffset
+= rect_fill_size
;
774 const uint32_t width
= fillSize
/ bs
;
775 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
776 dst_buffer
, dstOffset
,
778 width
* bs
, isl_format
,
781 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
782 0, 0, 1, 0, 0, width
, 1,
786 blorp_batch_finish(&batch
);
789 void anv_CmdClearColorImage(
790 VkCommandBuffer commandBuffer
,
792 VkImageLayout imageLayout
,
793 const VkClearColorValue
* pColor
,
795 const VkImageSubresourceRange
* pRanges
)
797 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
798 ANV_FROM_HANDLE(anv_image
, image
, _image
);
800 static const bool color_write_disable
[4] = { false, false, false, false };
802 struct blorp_batch batch
;
803 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
805 struct blorp_surf surf
;
806 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
807 image
->aux_usage
, &surf
);
809 for (unsigned r
= 0; r
< rangeCount
; r
++) {
810 if (pRanges
[r
].aspectMask
== 0)
813 assert(pRanges
[r
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
815 struct anv_format src_format
=
816 anv_get_format(&cmd_buffer
->device
->info
, image
->vk_format
,
817 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
819 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
820 unsigned layer_count
= pRanges
[r
].layerCount
;
822 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
823 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
824 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
825 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
827 if (image
->type
== VK_IMAGE_TYPE_3D
) {
829 layer_count
= anv_minify(image
->extent
.depth
, level
);
832 blorp_clear(&batch
, &surf
,
833 src_format
.isl_format
, src_format
.swizzle
,
834 level
, base_layer
, layer_count
,
835 0, 0, level_width
, level_height
,
836 vk_to_isl_color(*pColor
), color_write_disable
);
840 blorp_batch_finish(&batch
);
843 void anv_CmdClearDepthStencilImage(
844 VkCommandBuffer commandBuffer
,
846 VkImageLayout imageLayout
,
847 const VkClearDepthStencilValue
* pDepthStencil
,
849 const VkImageSubresourceRange
* pRanges
)
851 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
852 ANV_FROM_HANDLE(anv_image
, image
, image_h
);
854 struct blorp_batch batch
;
855 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
857 struct blorp_surf depth
, stencil
;
858 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
859 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
860 image
->aux_usage
, &depth
);
862 memset(&depth
, 0, sizeof(depth
));
865 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
866 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
867 ISL_AUX_USAGE_NONE
, &stencil
);
869 memset(&stencil
, 0, sizeof(stencil
));
872 for (unsigned r
= 0; r
< rangeCount
; r
++) {
873 if (pRanges
[r
].aspectMask
== 0)
876 bool clear_depth
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
877 bool clear_stencil
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
879 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
880 unsigned layer_count
= pRanges
[r
].layerCount
;
882 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
883 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
884 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
885 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
887 if (image
->type
== VK_IMAGE_TYPE_3D
)
888 layer_count
= anv_minify(image
->extent
.depth
, level
);
890 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
891 level
, base_layer
, layer_count
,
892 0, 0, level_width
, level_height
,
893 clear_depth
, pDepthStencil
->depth
,
894 clear_stencil
? 0xff : 0,
895 pDepthStencil
->stencil
);
899 blorp_batch_finish(&batch
);
903 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
904 uint32_t num_entries
,
905 uint32_t *state_offset
)
907 struct anv_state bt_state
=
908 anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
910 if (bt_state
.map
== NULL
) {
911 /* We ran out of space. Grab a new binding table block. */
912 VkResult result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
913 assert(result
== VK_SUCCESS
);
915 /* Re-emit state base addresses so we get the new surface state base
916 * address before we start emitting binding tables etc.
918 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
920 bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
922 assert(bt_state
.map
!= NULL
);
929 binding_table_for_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
930 struct anv_state surface_state
)
932 uint32_t state_offset
;
933 struct anv_state bt_state
=
934 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, 1, &state_offset
);
936 uint32_t *bt_map
= bt_state
.map
;
937 bt_map
[0] = surface_state
.offset
+ state_offset
;
939 return bt_state
.offset
;
943 clear_color_attachment(struct anv_cmd_buffer
*cmd_buffer
,
944 struct blorp_batch
*batch
,
945 const VkClearAttachment
*attachment
,
946 uint32_t rectCount
, const VkClearRect
*pRects
)
948 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
949 const uint32_t color_att
= attachment
->colorAttachment
;
950 const uint32_t att_idx
= subpass
->color_attachments
[color_att
];
952 if (att_idx
== VK_ATTACHMENT_UNUSED
)
955 struct anv_render_pass_attachment
*pass_att
=
956 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
957 struct anv_attachment_state
*att_state
=
958 &cmd_buffer
->state
.attachments
[att_idx
];
960 uint32_t binding_table
=
961 binding_table_for_surface_state(cmd_buffer
, att_state
->color_rt_state
);
963 union isl_color_value clear_color
=
964 vk_to_isl_color(attachment
->clearValue
.color
);
966 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
967 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
968 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
969 blorp_clear_attachments(batch
, binding_table
,
970 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
971 pRects
[r
].baseArrayLayer
,
972 pRects
[r
].layerCount
,
974 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
975 true, clear_color
, false, 0.0f
, 0, 0);
980 clear_depth_stencil_attachment(struct anv_cmd_buffer
*cmd_buffer
,
981 struct blorp_batch
*batch
,
982 const VkClearAttachment
*attachment
,
983 uint32_t rectCount
, const VkClearRect
*pRects
)
985 static const union isl_color_value color_value
= { .u32
= { 0, } };
986 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
987 const uint32_t att_idx
= subpass
->depth_stencil_attachment
;
989 if (att_idx
== VK_ATTACHMENT_UNUSED
)
992 struct anv_render_pass_attachment
*pass_att
=
993 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
995 bool clear_depth
= attachment
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
996 bool clear_stencil
= attachment
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
998 enum isl_format depth_format
= ISL_FORMAT_UNSUPPORTED
;
1000 depth_format
= anv_get_isl_format(&cmd_buffer
->device
->info
,
1002 VK_IMAGE_ASPECT_DEPTH_BIT
,
1003 VK_IMAGE_TILING_OPTIMAL
);
1006 uint32_t binding_table
=
1007 binding_table_for_surface_state(cmd_buffer
,
1008 cmd_buffer
->state
.null_surface_state
);
1010 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1011 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1012 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1013 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1014 blorp_clear_attachments(batch
, binding_table
,
1015 depth_format
, pass_att
->samples
,
1016 pRects
[r
].baseArrayLayer
,
1017 pRects
[r
].layerCount
,
1019 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1021 clear_depth
, value
.depth
,
1022 clear_stencil
? 0xff : 0, value
.stencil
);
1026 void anv_CmdClearAttachments(
1027 VkCommandBuffer commandBuffer
,
1028 uint32_t attachmentCount
,
1029 const VkClearAttachment
* pAttachments
,
1031 const VkClearRect
* pRects
)
1033 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1035 /* Because this gets called within a render pass, we tell blorp not to
1036 * trash our depth and stencil buffers.
1038 struct blorp_batch batch
;
1039 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1040 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1042 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1043 if (pAttachments
[a
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1044 clear_color_attachment(cmd_buffer
, &batch
,
1048 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1054 blorp_batch_finish(&batch
);
1057 enum subpass_stage
{
1060 SUBPASS_STAGE_RESOLVE
,
1064 attachment_needs_flush(struct anv_cmd_buffer
*cmd_buffer
,
1065 struct anv_render_pass_attachment
*att
,
1066 enum subpass_stage stage
)
1068 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1069 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1070 unsigned subpass_idx
= subpass
- pass
->subpasses
;
1071 assert(subpass_idx
< pass
->subpass_count
);
1073 /* We handle this subpass specially based on the current stage */
1074 enum anv_subpass_usage usage
= att
->subpass_usage
[subpass_idx
];
1076 case SUBPASS_STAGE_LOAD
:
1077 if (usage
& (ANV_SUBPASS_USAGE_INPUT
| ANV_SUBPASS_USAGE_RESOLVE_SRC
))
1081 case SUBPASS_STAGE_DRAW
:
1082 if (usage
& ANV_SUBPASS_USAGE_RESOLVE_SRC
)
1090 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1091 usage
= att
->subpass_usage
[s
];
1093 /* If this attachment is going to be used as an input in this or any
1094 * future subpass, then we need to flush its cache and invalidate the
1097 if (att
->subpass_usage
[s
] & ANV_SUBPASS_USAGE_INPUT
)
1100 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1101 /* We found another subpass that draws to this attachment. We'll
1102 * wait to resolve until then.
1112 anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1113 enum subpass_stage stage
)
1115 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1116 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1118 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1119 uint32_t att
= subpass
->color_attachments
[i
];
1120 assert(att
< pass
->attachment_count
);
1121 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1122 cmd_buffer
->state
.pending_pipe_bits
|=
1123 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1124 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1128 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1129 uint32_t att
= subpass
->depth_stencil_attachment
;
1130 assert(att
< pass
->attachment_count
);
1131 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1132 cmd_buffer
->state
.pending_pipe_bits
|=
1133 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1134 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1140 subpass_needs_clear(const struct anv_cmd_buffer
*cmd_buffer
)
1142 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1143 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
1145 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1146 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
];
1147 if (cmd_state
->attachments
[a
].pending_clear_aspects
) {
1152 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1153 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1161 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1163 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1165 if (!subpass_needs_clear(cmd_buffer
))
1168 /* Because this gets called within a render pass, we tell blorp not to
1169 * trash our depth and stencil buffers.
1171 struct blorp_batch batch
;
1172 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1173 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1175 VkClearRect clear_rect
= {
1176 .rect
= cmd_buffer
->state
.render_area
,
1177 .baseArrayLayer
= 0,
1178 .layerCount
= cmd_buffer
->state
.framebuffer
->layers
,
1181 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1182 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1183 const uint32_t a
= cmd_state
->subpass
->color_attachments
[i
];
1184 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
1186 if (!att_state
->pending_clear_aspects
)
1189 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1191 struct anv_image_view
*iview
= fb
->attachments
[a
];
1192 const struct anv_image
*image
= iview
->image
;
1193 struct blorp_surf surf
;
1194 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1195 att_state
->aux_usage
, &surf
);
1196 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1198 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1200 if (att_state
->fast_clear
) {
1201 blorp_fast_clear(&batch
, &surf
, iview
->isl
.format
,
1202 iview
->isl
.base_level
,
1203 iview
->isl
.base_array_layer
, fb
->layers
,
1204 render_area
.offset
.x
, render_area
.offset
.y
,
1205 render_area
.offset
.x
+ render_area
.extent
.width
,
1206 render_area
.offset
.y
+ render_area
.extent
.height
);
1208 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1210 * "After Render target fast clear, pipe-control with color cache
1211 * write-flush must be issued before sending any DRAW commands on
1212 * that render target."
1214 cmd_buffer
->state
.pending_pipe_bits
|=
1215 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1217 blorp_clear(&batch
, &surf
, iview
->isl
.format
, iview
->isl
.swizzle
,
1218 iview
->isl
.base_level
,
1219 iview
->isl
.base_array_layer
, fb
->layers
,
1220 render_area
.offset
.x
, render_area
.offset
.y
,
1221 render_area
.offset
.x
+ render_area
.extent
.width
,
1222 render_area
.offset
.y
+ render_area
.extent
.height
,
1223 surf
.clear_color
, NULL
);
1226 att_state
->pending_clear_aspects
= 0;
1229 const uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
1231 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1232 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1234 VkClearAttachment clear_att
= {
1235 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1236 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1239 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1240 &clear_att
, 1, &clear_rect
);
1242 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
1245 blorp_batch_finish(&batch
);
1247 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_LOAD
);
1251 resolve_image(struct blorp_batch
*batch
,
1252 const struct anv_image
*src_image
,
1253 uint32_t src_level
, uint32_t src_layer
,
1254 const struct anv_image
*dst_image
,
1255 uint32_t dst_level
, uint32_t dst_layer
,
1256 VkImageAspectFlags aspect_mask
,
1257 uint32_t src_x
, uint32_t src_y
, uint32_t dst_x
, uint32_t dst_y
,
1258 uint32_t width
, uint32_t height
)
1260 assert(src_image
->type
== VK_IMAGE_TYPE_2D
);
1261 assert(src_image
->samples
> 1);
1262 assert(dst_image
->type
== VK_IMAGE_TYPE_2D
);
1263 assert(dst_image
->samples
== 1);
1266 for_each_bit(a
, aspect_mask
) {
1267 VkImageAspectFlagBits aspect
= 1 << a
;
1269 struct blorp_surf src_surf
, dst_surf
;
1270 get_blorp_surf_for_anv_image(src_image
, aspect
,
1271 src_image
->aux_usage
, &src_surf
);
1272 get_blorp_surf_for_anv_image(dst_image
, aspect
,
1273 dst_image
->aux_usage
, &dst_surf
);
1276 &src_surf
, src_level
, src_layer
,
1277 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1278 &dst_surf
, dst_level
, dst_layer
,
1279 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1280 src_x
, src_y
, src_x
+ width
, src_y
+ height
,
1281 dst_x
, dst_y
, dst_x
+ width
, dst_y
+ height
,
1282 0x2600 /* GL_NEAREST */, false, false);
1286 void anv_CmdResolveImage(
1287 VkCommandBuffer commandBuffer
,
1289 VkImageLayout srcImageLayout
,
1291 VkImageLayout dstImageLayout
,
1292 uint32_t regionCount
,
1293 const VkImageResolve
* pRegions
)
1295 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1296 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
1297 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
1299 struct blorp_batch batch
;
1300 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1302 for (uint32_t r
= 0; r
< regionCount
; r
++) {
1303 assert(pRegions
[r
].srcSubresource
.aspectMask
==
1304 pRegions
[r
].dstSubresource
.aspectMask
);
1305 assert(pRegions
[r
].srcSubresource
.layerCount
==
1306 pRegions
[r
].dstSubresource
.layerCount
);
1308 const uint32_t layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
1310 for (uint32_t layer
= 0; layer
< layer_count
; layer
++) {
1311 resolve_image(&batch
,
1312 src_image
, pRegions
[r
].srcSubresource
.mipLevel
,
1313 pRegions
[r
].srcSubresource
.baseArrayLayer
+ layer
,
1314 dst_image
, pRegions
[r
].dstSubresource
.mipLevel
,
1315 pRegions
[r
].dstSubresource
.baseArrayLayer
+ layer
,
1316 pRegions
[r
].dstSubresource
.aspectMask
,
1317 pRegions
[r
].srcOffset
.x
, pRegions
[r
].srcOffset
.y
,
1318 pRegions
[r
].dstOffset
.x
, pRegions
[r
].dstOffset
.y
,
1319 pRegions
[r
].extent
.width
, pRegions
[r
].extent
.height
);
1323 blorp_batch_finish(&batch
);
1327 ccs_resolve_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1328 struct blorp_batch
*batch
,
1331 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1332 struct anv_attachment_state
*att_state
=
1333 &cmd_buffer
->state
.attachments
[att
];
1335 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
1336 return; /* Nothing to resolve */
1338 assert(att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1339 att_state
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1341 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1342 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1343 unsigned subpass_idx
= subpass
- pass
->subpasses
;
1344 assert(subpass_idx
< pass
->subpass_count
);
1346 /* Scan forward to see what all ways this attachment will be used.
1347 * Ideally, we would like to resolve in the same subpass as the last write
1348 * of a particular attachment. That way we only resolve once but it's
1349 * still hot in the cache.
1351 bool found_draw
= false;
1352 enum anv_subpass_usage usage
= 0;
1353 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1354 usage
|= pass
->attachments
[att
].subpass_usage
[s
];
1356 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1357 /* We found another subpass that draws to this attachment. We'll
1358 * wait to resolve until then.
1365 struct anv_image_view
*iview
= fb
->attachments
[att
];
1366 const struct anv_image
*image
= iview
->image
;
1367 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1369 enum blorp_fast_clear_op resolve_op
= BLORP_FAST_CLEAR_OP_NONE
;
1371 /* This is the last subpass that writes to this attachment so we need to
1372 * resolve here. Ideally, we would like to only resolve if the storeOp
1373 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1374 * that the CCS bits are set to "resolved" because there may be copy or
1375 * blit operations (which may ignore CCS) between now and the next time
1376 * we render and we need to ensure that anything they write will be
1377 * respected in the next render. Unfortunately, the hardware does not
1378 * provide us with any sort of "invalidate" pass that sets the CCS to
1379 * "resolved" without writing to the render target.
1381 if (iview
->image
->aux_usage
!= ISL_AUX_USAGE_CCS_E
) {
1382 /* The image destination surface doesn't support compression outside
1383 * the render pass. We need a full resolve.
1385 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1386 } else if (att_state
->fast_clear
) {
1387 /* We don't know what to do with clear colors outside the render
1388 * pass. We need a partial resolve.
1390 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1392 /* The image "natively" supports all the compression we care about
1393 * and we don't need to resolve at all. If this is the case, we also
1394 * don't need to resolve for any of the input attachment cases below.
1397 } else if (usage
& ANV_SUBPASS_USAGE_INPUT
) {
1398 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1399 * can frequently sample from them with no resolves at all.
1401 if (att_state
->aux_usage
!= att_state
->input_aux_usage
) {
1402 assert(att_state
->input_aux_usage
== ISL_AUX_USAGE_NONE
);
1403 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1404 } else if (!att_state
->clear_color_is_zero_one
) {
1405 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1407 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1408 * is fast cleared with non-0/1 clear value, this RT must be
1409 * partially resolved (refer to Partial Resolve operation) before
1410 * binding this surface to Sampler."
1412 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1416 if (resolve_op
== BLORP_FAST_CLEAR_OP_NONE
)
1419 struct blorp_surf surf
;
1420 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1421 att_state
->aux_usage
, &surf
);
1422 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1424 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1426 * "When performing a render target resolve, PIPE_CONTROL with end of
1427 * pipe sync must be delivered."
1429 * This comment is a bit cryptic and doesn't really tell you what's going
1430 * or what's really needed. It appears that fast clear ops are not
1431 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1432 * to ensure that the contents of the previous draw hit the render target
1433 * before we resolve and then use a second PIPE_CONTROL after the resolve
1434 * to ensure that it is completed before any additional drawing occurs.
1436 cmd_buffer
->state
.pending_pipe_bits
|=
1437 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1439 for (uint32_t layer
= 0; layer
< fb
->layers
; layer
++) {
1440 blorp_ccs_resolve(batch
, &surf
,
1441 iview
->isl
.base_level
,
1442 iview
->isl
.base_array_layer
+ layer
,
1443 iview
->isl
.format
, resolve_op
);
1446 cmd_buffer
->state
.pending_pipe_bits
|=
1447 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1449 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1450 att_state
->fast_clear
= false;
1454 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1456 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1457 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1460 struct blorp_batch batch
;
1461 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1463 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1464 ccs_resolve_attachment(cmd_buffer
, &batch
,
1465 subpass
->color_attachments
[i
]);
1468 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_DRAW
);
1470 if (subpass
->has_resolve
) {
1471 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1472 uint32_t src_att
= subpass
->color_attachments
[i
];
1473 uint32_t dst_att
= subpass
->resolve_attachments
[i
];
1475 if (dst_att
== VK_ATTACHMENT_UNUSED
)
1478 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
1479 /* From the Vulkan 1.0 spec:
1481 * If the first use of an attachment in a render pass is as a
1482 * resolve attachment, then the loadOp is effectively ignored
1483 * as the resolve is guaranteed to overwrite all pixels in the
1486 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
1489 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
1490 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
1492 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1494 assert(src_iview
->aspect_mask
== dst_iview
->aspect_mask
);
1495 resolve_image(&batch
, src_iview
->image
,
1496 src_iview
->isl
.base_level
,
1497 src_iview
->isl
.base_array_layer
,
1499 dst_iview
->isl
.base_level
,
1500 dst_iview
->isl
.base_array_layer
,
1501 src_iview
->aspect_mask
,
1502 render_area
.offset
.x
, render_area
.offset
.y
,
1503 render_area
.offset
.x
, render_area
.offset
.y
,
1504 render_area
.extent
.width
, render_area
.extent
.height
);
1506 ccs_resolve_attachment(cmd_buffer
, &batch
, dst_att
);
1509 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_RESOLVE
);
1512 blorp_batch_finish(&batch
);