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[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_context *blorp,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct anv_device *device = blorp->driver_ctx;
32
33 /* The blorp cache must be a real cache */
34 assert(device->blorp_shader_cache.cache);
35
36 struct anv_shader_bin *bin =
37 anv_pipeline_cache_search(&device->blorp_shader_cache, key, key_size);
38 if (!bin)
39 return false;
40
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
43 */
44 anv_shader_bin_unref(device, bin);
45
46 *kernel_out = bin->kernel.offset;
47 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
48
49 return true;
50 }
51
52 static void
53 upload_blorp_shader(struct blorp_context *blorp,
54 const void *key, uint32_t key_size,
55 const void *kernel, uint32_t kernel_size,
56 const struct brw_stage_prog_data *prog_data,
57 uint32_t prog_data_size,
58 uint32_t *kernel_out, void *prog_data_out)
59 {
60 struct anv_device *device = blorp->driver_ctx;
61
62 /* The blorp cache must be a real cache */
63 assert(device->blorp_shader_cache.cache);
64
65 struct anv_pipeline_bind_map bind_map = {
66 .surface_count = 0,
67 .sampler_count = 0,
68 };
69
70 struct anv_shader_bin *bin =
71 anv_pipeline_cache_upload_kernel(&device->blorp_shader_cache,
72 key, key_size, kernel, kernel_size,
73 prog_data, prog_data_size, &bind_map);
74
75 /* The cache already has a reference and it's not going anywhere so there
76 * is no need to hold a second reference.
77 */
78 anv_shader_bin_unref(device, bin);
79
80 *kernel_out = bin->kernel.offset;
81 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
82 }
83
84 void
85 anv_device_init_blorp(struct anv_device *device)
86 {
87 anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
88 blorp_init(&device->blorp, device, &device->isl_dev);
89 device->blorp.compiler = device->instance->physicalDevice.compiler;
90 device->blorp.mocs.tex = device->default_mocs;
91 device->blorp.mocs.rb = device->default_mocs;
92 device->blorp.mocs.vb = device->default_mocs;
93 device->blorp.lookup_shader = lookup_blorp_shader;
94 device->blorp.upload_shader = upload_blorp_shader;
95 switch (device->info.gen) {
96 case 7:
97 if (device->info.is_haswell) {
98 device->blorp.exec = gen75_blorp_exec;
99 } else {
100 device->blorp.exec = gen7_blorp_exec;
101 }
102 break;
103 case 8:
104 device->blorp.exec = gen8_blorp_exec;
105 break;
106 case 9:
107 device->blorp.exec = gen9_blorp_exec;
108 break;
109 default:
110 unreachable("Unknown hardware generation");
111 }
112 }
113
114 void
115 anv_device_finish_blorp(struct anv_device *device)
116 {
117 blorp_finish(&device->blorp);
118 anv_pipeline_cache_finish(&device->blorp_shader_cache);
119 }
120
121 static void
122 get_blorp_surf_for_anv_buffer(struct anv_device *device,
123 struct anv_buffer *buffer, uint64_t offset,
124 uint32_t width, uint32_t height,
125 uint32_t row_pitch, enum isl_format format,
126 struct blorp_surf *blorp_surf,
127 struct isl_surf *isl_surf)
128 {
129 const struct isl_format_layout *fmtl =
130 isl_format_get_layout(format);
131
132 /* ASTC is the only format which doesn't support linear layouts.
133 * Create an equivalently sized surface with ISL to get around this.
134 */
135 if (fmtl->txc == ISL_TXC_ASTC) {
136 /* Use an equivalently sized format */
137 format = ISL_FORMAT_R32G32B32A32_UINT;
138 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
139
140 /* Shrink the dimensions for the new format */
141 width = DIV_ROUND_UP(width, fmtl->bw);
142 height = DIV_ROUND_UP(height, fmtl->bh);
143 }
144
145 *blorp_surf = (struct blorp_surf) {
146 .surf = isl_surf,
147 .addr = {
148 .buffer = buffer->bo,
149 .offset = buffer->offset + offset,
150 },
151 };
152
153 isl_surf_init(&device->isl_dev, isl_surf,
154 .dim = ISL_SURF_DIM_2D,
155 .format = format,
156 .width = width,
157 .height = height,
158 .depth = 1,
159 .levels = 1,
160 .array_len = 1,
161 .samples = 1,
162 .min_pitch = row_pitch,
163 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
164 ISL_SURF_USAGE_RENDER_TARGET_BIT,
165 .tiling_flags = ISL_TILING_LINEAR_BIT);
166 assert(isl_surf->row_pitch == row_pitch);
167 }
168
169 static void
170 get_blorp_surf_for_anv_image(const struct anv_image *image,
171 VkImageAspectFlags aspect,
172 enum isl_aux_usage aux_usage,
173 struct blorp_surf *blorp_surf)
174 {
175 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
176 aux_usage == ISL_AUX_USAGE_HIZ)
177 aux_usage = ISL_AUX_USAGE_NONE;
178
179 const struct anv_surface *surface =
180 anv_image_get_surface_for_aspect_mask(image, aspect);
181
182 *blorp_surf = (struct blorp_surf) {
183 .surf = &surface->isl,
184 .addr = {
185 .buffer = image->bo,
186 .offset = image->offset + surface->offset,
187 },
188 };
189
190 if (aux_usage != ISL_AUX_USAGE_NONE) {
191 blorp_surf->aux_surf = &image->aux_surface.isl,
192 blorp_surf->aux_addr = (struct blorp_address) {
193 .buffer = image->bo,
194 .offset = image->offset + image->aux_surface.offset,
195 };
196 blorp_surf->aux_usage = aux_usage;
197 }
198 }
199
200 void anv_CmdCopyImage(
201 VkCommandBuffer commandBuffer,
202 VkImage srcImage,
203 VkImageLayout srcImageLayout,
204 VkImage dstImage,
205 VkImageLayout dstImageLayout,
206 uint32_t regionCount,
207 const VkImageCopy* pRegions)
208 {
209 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
210 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
211 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
212
213 struct blorp_batch batch;
214 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
215
216 for (unsigned r = 0; r < regionCount; r++) {
217 VkOffset3D srcOffset =
218 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
219 VkOffset3D dstOffset =
220 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
221 VkExtent3D extent =
222 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
223
224 unsigned dst_base_layer, layer_count;
225 if (dst_image->type == VK_IMAGE_TYPE_3D) {
226 dst_base_layer = pRegions[r].dstOffset.z;
227 layer_count = pRegions[r].extent.depth;
228 } else {
229 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
230 layer_count = pRegions[r].dstSubresource.layerCount;
231 }
232
233 unsigned src_base_layer;
234 if (src_image->type == VK_IMAGE_TYPE_3D) {
235 src_base_layer = pRegions[r].srcOffset.z;
236 } else {
237 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
238 assert(pRegions[r].srcSubresource.layerCount == layer_count);
239 }
240
241 assert(pRegions[r].srcSubresource.aspectMask ==
242 pRegions[r].dstSubresource.aspectMask);
243
244 uint32_t a;
245 for_each_bit(a, pRegions[r].dstSubresource.aspectMask) {
246 VkImageAspectFlagBits aspect = (1 << a);
247
248 struct blorp_surf src_surf, dst_surf;
249 get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
250 &src_surf);
251 get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
252 &dst_surf);
253
254 for (unsigned i = 0; i < layer_count; i++) {
255 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
256 src_base_layer + i,
257 &dst_surf, pRegions[r].dstSubresource.mipLevel,
258 dst_base_layer + i,
259 srcOffset.x, srcOffset.y,
260 dstOffset.x, dstOffset.y,
261 extent.width, extent.height);
262 }
263 }
264 }
265
266 blorp_batch_finish(&batch);
267 }
268
269 static void
270 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
271 struct anv_buffer *anv_buffer,
272 struct anv_image *anv_image,
273 uint32_t regionCount,
274 const VkBufferImageCopy* pRegions,
275 bool buffer_to_image)
276 {
277 struct blorp_batch batch;
278 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
279
280 struct {
281 struct blorp_surf surf;
282 uint32_t level;
283 VkOffset3D offset;
284 } image, buffer, *src, *dst;
285
286 buffer.level = 0;
287 buffer.offset = (VkOffset3D) { 0, 0, 0 };
288
289 if (buffer_to_image) {
290 src = &buffer;
291 dst = &image;
292 } else {
293 src = &image;
294 dst = &buffer;
295 }
296
297 for (unsigned r = 0; r < regionCount; r++) {
298 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
299
300 get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
301 &image.surf);
302 image.offset =
303 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
304 image.level = pRegions[r].imageSubresource.mipLevel;
305
306 VkExtent3D extent =
307 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
308 if (anv_image->type != VK_IMAGE_TYPE_3D) {
309 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
310 extent.depth = pRegions[r].imageSubresource.layerCount;
311 }
312
313 const enum isl_format buffer_format =
314 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
315 aspect, VK_IMAGE_TILING_LINEAR);
316
317 const VkExtent3D bufferImageExtent = {
318 .width = pRegions[r].bufferRowLength ?
319 pRegions[r].bufferRowLength : extent.width,
320 .height = pRegions[r].bufferImageHeight ?
321 pRegions[r].bufferImageHeight : extent.height,
322 };
323
324 const struct isl_format_layout *buffer_fmtl =
325 isl_format_get_layout(buffer_format);
326
327 const uint32_t buffer_row_pitch =
328 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
329 (buffer_fmtl->bpb / 8);
330
331 const uint32_t buffer_layer_stride =
332 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
333 buffer_row_pitch;
334
335 struct isl_surf buffer_isl_surf;
336 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
337 anv_buffer, pRegions[r].bufferOffset,
338 extent.width, extent.height,
339 buffer_row_pitch, buffer_format,
340 &buffer.surf, &buffer_isl_surf);
341
342 for (unsigned z = 0; z < extent.depth; z++) {
343 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
344 &dst->surf, dst->level, dst->offset.z,
345 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
346 extent.width, extent.height);
347
348 image.offset.z++;
349 buffer.surf.addr.offset += buffer_layer_stride;
350 }
351 }
352
353 blorp_batch_finish(&batch);
354 }
355
356 void anv_CmdCopyBufferToImage(
357 VkCommandBuffer commandBuffer,
358 VkBuffer srcBuffer,
359 VkImage dstImage,
360 VkImageLayout dstImageLayout,
361 uint32_t regionCount,
362 const VkBufferImageCopy* pRegions)
363 {
364 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
365 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
366 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
367
368 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image,
369 regionCount, pRegions, true);
370 }
371
372 void anv_CmdCopyImageToBuffer(
373 VkCommandBuffer commandBuffer,
374 VkImage srcImage,
375 VkImageLayout srcImageLayout,
376 VkBuffer dstBuffer,
377 uint32_t regionCount,
378 const VkBufferImageCopy* pRegions)
379 {
380 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
381 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
382 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
383
384 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image,
385 regionCount, pRegions, false);
386 }
387
388 static bool
389 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
390 {
391 bool flip = false;
392 if (*src0 > *src1) {
393 unsigned tmp = *src0;
394 *src0 = *src1;
395 *src1 = tmp;
396 flip = !flip;
397 }
398
399 if (*dst0 > *dst1) {
400 unsigned tmp = *dst0;
401 *dst0 = *dst1;
402 *dst1 = tmp;
403 flip = !flip;
404 }
405
406 return flip;
407 }
408
409 void anv_CmdBlitImage(
410 VkCommandBuffer commandBuffer,
411 VkImage srcImage,
412 VkImageLayout srcImageLayout,
413 VkImage dstImage,
414 VkImageLayout dstImageLayout,
415 uint32_t regionCount,
416 const VkImageBlit* pRegions,
417 VkFilter filter)
418
419 {
420 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
421 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
422 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
423
424 struct blorp_surf src, dst;
425
426 uint32_t gl_filter;
427 switch (filter) {
428 case VK_FILTER_NEAREST:
429 gl_filter = 0x2600; /* GL_NEAREST */
430 break;
431 case VK_FILTER_LINEAR:
432 gl_filter = 0x2601; /* GL_LINEAR */
433 break;
434 default:
435 unreachable("Invalid filter");
436 }
437
438 struct blorp_batch batch;
439 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
440
441 for (unsigned r = 0; r < regionCount; r++) {
442 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
443 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
444
445 get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
446 src_image->aux_usage, &src);
447 get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
448 dst_image->aux_usage, &dst);
449
450 struct anv_format src_format =
451 anv_get_format(&cmd_buffer->device->info, src_image->vk_format,
452 src_res->aspectMask, src_image->tiling);
453 struct anv_format dst_format =
454 anv_get_format(&cmd_buffer->device->info, dst_image->vk_format,
455 dst_res->aspectMask, dst_image->tiling);
456
457 unsigned dst_start, dst_end;
458 if (dst_image->type == VK_IMAGE_TYPE_3D) {
459 assert(dst_res->baseArrayLayer == 0);
460 dst_start = pRegions[r].dstOffsets[0].z;
461 dst_end = pRegions[r].dstOffsets[1].z;
462 } else {
463 dst_start = dst_res->baseArrayLayer;
464 dst_end = dst_start + dst_res->layerCount;
465 }
466
467 unsigned src_start, src_end;
468 if (src_image->type == VK_IMAGE_TYPE_3D) {
469 assert(src_res->baseArrayLayer == 0);
470 src_start = pRegions[r].srcOffsets[0].z;
471 src_end = pRegions[r].srcOffsets[1].z;
472 } else {
473 src_start = src_res->baseArrayLayer;
474 src_end = src_start + src_res->layerCount;
475 }
476
477 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
478 float src_z_step = (float)(src_end + 1 - src_start) /
479 (float)(dst_end + 1 - dst_start);
480
481 if (flip_z) {
482 src_start = src_end;
483 src_z_step *= -1;
484 }
485
486 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
487 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
488 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
489 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
490 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
491
492 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
493 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
494 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
495 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
496 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
497
498 const unsigned num_layers = dst_end - dst_start;
499 for (unsigned i = 0; i < num_layers; i++) {
500 unsigned dst_z = dst_start + i;
501 unsigned src_z = src_start + i * src_z_step;
502
503 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
504 src_format.isl_format, src_format.swizzle,
505 &dst, dst_res->mipLevel, dst_z,
506 dst_format.isl_format, dst_format.swizzle,
507 src_x0, src_y0, src_x1, src_y1,
508 dst_x0, dst_y0, dst_x1, dst_y1,
509 gl_filter, flip_x, flip_y);
510 }
511
512 }
513
514 blorp_batch_finish(&batch);
515 }
516
517 static enum isl_format
518 isl_format_for_size(unsigned size_B)
519 {
520 switch (size_B) {
521 case 1: return ISL_FORMAT_R8_UINT;
522 case 2: return ISL_FORMAT_R8G8_UINT;
523 case 4: return ISL_FORMAT_R8G8B8A8_UINT;
524 case 8: return ISL_FORMAT_R16G16B16A16_UINT;
525 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
526 default:
527 unreachable("Not a power-of-two format size");
528 }
529 }
530
531 static void
532 do_buffer_copy(struct blorp_batch *batch,
533 struct anv_bo *src, uint64_t src_offset,
534 struct anv_bo *dst, uint64_t dst_offset,
535 int width, int height, int block_size)
536 {
537 struct anv_device *device = batch->blorp->driver_ctx;
538
539 /* The actual format we pick doesn't matter as blorp will throw it away.
540 * The only thing that actually matters is the size.
541 */
542 enum isl_format format = isl_format_for_size(block_size);
543
544 struct isl_surf surf;
545 isl_surf_init(&device->isl_dev, &surf,
546 .dim = ISL_SURF_DIM_2D,
547 .format = format,
548 .width = width,
549 .height = height,
550 .depth = 1,
551 .levels = 1,
552 .array_len = 1,
553 .samples = 1,
554 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
555 ISL_SURF_USAGE_RENDER_TARGET_BIT,
556 .tiling_flags = ISL_TILING_LINEAR_BIT);
557 assert(surf.row_pitch == width * block_size);
558
559 struct blorp_surf src_blorp_surf = {
560 .surf = &surf,
561 .addr = {
562 .buffer = src,
563 .offset = src_offset,
564 },
565 };
566
567 struct blorp_surf dst_blorp_surf = {
568 .surf = &surf,
569 .addr = {
570 .buffer = dst,
571 .offset = dst_offset,
572 },
573 };
574
575 blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
576 0, 0, 0, 0, width, height);
577 }
578
579 /**
580 * Returns the greatest common divisor of a and b that is a power of two.
581 */
582 static inline uint64_t
583 gcd_pow2_u64(uint64_t a, uint64_t b)
584 {
585 assert(a > 0 || b > 0);
586
587 unsigned a_log2 = ffsll(a) - 1;
588 unsigned b_log2 = ffsll(b) - 1;
589
590 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
591 * case, the MIN2() will take the other one. If both are 0 then we will
592 * hit the assert above.
593 */
594 return 1 << MIN2(a_log2, b_log2);
595 }
596
597 /* This is maximum possible width/height our HW can handle */
598 #define MAX_SURFACE_DIM (1ull << 14)
599
600 void anv_CmdCopyBuffer(
601 VkCommandBuffer commandBuffer,
602 VkBuffer srcBuffer,
603 VkBuffer dstBuffer,
604 uint32_t regionCount,
605 const VkBufferCopy* pRegions)
606 {
607 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
608 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
609 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
610
611 struct blorp_batch batch;
612 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
613
614 for (unsigned r = 0; r < regionCount; r++) {
615 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
616 uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
617 uint64_t copy_size = pRegions[r].size;
618
619 /* First, we compute the biggest format that can be used with the
620 * given offsets and size.
621 */
622 int bs = 16;
623 bs = gcd_pow2_u64(bs, src_offset);
624 bs = gcd_pow2_u64(bs, dst_offset);
625 bs = gcd_pow2_u64(bs, pRegions[r].size);
626
627 /* First, we make a bunch of max-sized copies */
628 uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
629 while (copy_size >= max_copy_size) {
630 do_buffer_copy(&batch, src_buffer->bo, src_offset,
631 dst_buffer->bo, dst_offset,
632 MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
633 copy_size -= max_copy_size;
634 src_offset += max_copy_size;
635 dst_offset += max_copy_size;
636 }
637
638 /* Now make a max-width copy */
639 uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
640 assert(height < MAX_SURFACE_DIM);
641 if (height != 0) {
642 uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
643 do_buffer_copy(&batch, src_buffer->bo, src_offset,
644 dst_buffer->bo, dst_offset,
645 MAX_SURFACE_DIM, height, bs);
646 copy_size -= rect_copy_size;
647 src_offset += rect_copy_size;
648 dst_offset += rect_copy_size;
649 }
650
651 /* Finally, make a small copy to finish it off */
652 if (copy_size != 0) {
653 do_buffer_copy(&batch, src_buffer->bo, src_offset,
654 dst_buffer->bo, dst_offset,
655 copy_size / bs, 1, bs);
656 }
657 }
658
659 blorp_batch_finish(&batch);
660 }
661
662 void anv_CmdUpdateBuffer(
663 VkCommandBuffer commandBuffer,
664 VkBuffer dstBuffer,
665 VkDeviceSize dstOffset,
666 VkDeviceSize dataSize,
667 const void* pData)
668 {
669 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
670 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
671
672 struct blorp_batch batch;
673 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
674
675 /* We can't quite grab a full block because the state stream needs a
676 * little data at the top to build its linked list.
677 */
678 const uint32_t max_update_size =
679 cmd_buffer->device->dynamic_state_block_pool.block_size - 64;
680
681 assert(max_update_size < MAX_SURFACE_DIM * 4);
682
683 while (dataSize) {
684 const uint32_t copy_size = MIN2(dataSize, max_update_size);
685
686 struct anv_state tmp_data =
687 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
688
689 memcpy(tmp_data.map, pData, copy_size);
690
691 int bs = 16;
692 bs = gcd_pow2_u64(bs, dstOffset);
693 bs = gcd_pow2_u64(bs, copy_size);
694
695 do_buffer_copy(&batch,
696 &cmd_buffer->device->dynamic_state_block_pool.bo,
697 tmp_data.offset,
698 dst_buffer->bo, dst_buffer->offset + dstOffset,
699 copy_size / bs, 1, bs);
700
701 dataSize -= copy_size;
702 dstOffset += copy_size;
703 pData = (void *)pData + copy_size;
704 }
705
706 blorp_batch_finish(&batch);
707 }
708
709 void anv_CmdFillBuffer(
710 VkCommandBuffer commandBuffer,
711 VkBuffer dstBuffer,
712 VkDeviceSize dstOffset,
713 VkDeviceSize fillSize,
714 uint32_t data)
715 {
716 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
717 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
718 struct blorp_surf surf;
719 struct isl_surf isl_surf;
720
721 struct blorp_batch batch;
722 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
723
724 if (fillSize == VK_WHOLE_SIZE) {
725 fillSize = dst_buffer->size - dstOffset;
726 /* Make sure fillSize is a multiple of 4 */
727 fillSize &= ~3ull;
728 }
729
730 /* First, we compute the biggest format that can be used with the
731 * given offsets and size.
732 */
733 int bs = 16;
734 bs = gcd_pow2_u64(bs, dstOffset);
735 bs = gcd_pow2_u64(bs, fillSize);
736 enum isl_format isl_format = isl_format_for_size(bs);
737
738 union isl_color_value color = {
739 .u32 = { data, data, data, data },
740 };
741
742 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
743 while (fillSize >= max_fill_size) {
744 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
745 dst_buffer, dstOffset,
746 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
747 MAX_SURFACE_DIM * bs, isl_format,
748 &surf, &isl_surf);
749
750 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
751 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
752 color, NULL);
753 fillSize -= max_fill_size;
754 dstOffset += max_fill_size;
755 }
756
757 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
758 assert(height < MAX_SURFACE_DIM);
759 if (height != 0) {
760 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
761 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
762 dst_buffer, dstOffset,
763 MAX_SURFACE_DIM, height,
764 MAX_SURFACE_DIM * bs, isl_format,
765 &surf, &isl_surf);
766
767 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
768 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
769 color, NULL);
770 fillSize -= rect_fill_size;
771 dstOffset += rect_fill_size;
772 }
773
774 if (fillSize != 0) {
775 const uint32_t width = fillSize / bs;
776 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
777 dst_buffer, dstOffset,
778 width, 1,
779 width * bs, isl_format,
780 &surf, &isl_surf);
781
782 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
783 0, 0, 1, 0, 0, width, 1,
784 color, NULL);
785 }
786
787 blorp_batch_finish(&batch);
788 }
789
790 void anv_CmdClearColorImage(
791 VkCommandBuffer commandBuffer,
792 VkImage _image,
793 VkImageLayout imageLayout,
794 const VkClearColorValue* pColor,
795 uint32_t rangeCount,
796 const VkImageSubresourceRange* pRanges)
797 {
798 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
799 ANV_FROM_HANDLE(anv_image, image, _image);
800
801 static const bool color_write_disable[4] = { false, false, false, false };
802
803 struct blorp_batch batch;
804 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
805
806 struct blorp_surf surf;
807 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
808 image->aux_usage, &surf);
809
810 for (unsigned r = 0; r < rangeCount; r++) {
811 if (pRanges[r].aspectMask == 0)
812 continue;
813
814 assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
815
816 struct anv_format src_format =
817 anv_get_format(&cmd_buffer->device->info, image->vk_format,
818 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
819
820 unsigned base_layer = pRanges[r].baseArrayLayer;
821 unsigned layer_count = pRanges[r].layerCount;
822
823 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
824 const unsigned level = pRanges[r].baseMipLevel + i;
825 const unsigned level_width = anv_minify(image->extent.width, level);
826 const unsigned level_height = anv_minify(image->extent.height, level);
827
828 if (image->type == VK_IMAGE_TYPE_3D) {
829 base_layer = 0;
830 layer_count = anv_minify(image->extent.depth, level);
831 }
832
833 blorp_clear(&batch, &surf,
834 src_format.isl_format, src_format.swizzle,
835 level, base_layer, layer_count,
836 0, 0, level_width, level_height,
837 vk_to_isl_color(*pColor), color_write_disable);
838 }
839 }
840
841 blorp_batch_finish(&batch);
842 }
843
844 void anv_CmdClearDepthStencilImage(
845 VkCommandBuffer commandBuffer,
846 VkImage image_h,
847 VkImageLayout imageLayout,
848 const VkClearDepthStencilValue* pDepthStencil,
849 uint32_t rangeCount,
850 const VkImageSubresourceRange* pRanges)
851 {
852 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
853 ANV_FROM_HANDLE(anv_image, image, image_h);
854
855 struct blorp_batch batch;
856 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
857
858 struct blorp_surf depth, stencil;
859 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
860 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
861 image->aux_usage, &depth);
862 } else {
863 memset(&depth, 0, sizeof(depth));
864 }
865
866 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
867 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
868 ISL_AUX_USAGE_NONE, &stencil);
869 } else {
870 memset(&stencil, 0, sizeof(stencil));
871 }
872
873 for (unsigned r = 0; r < rangeCount; r++) {
874 if (pRanges[r].aspectMask == 0)
875 continue;
876
877 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
878 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
879
880 unsigned base_layer = pRanges[r].baseArrayLayer;
881 unsigned layer_count = pRanges[r].layerCount;
882
883 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
884 const unsigned level = pRanges[r].baseMipLevel + i;
885 const unsigned level_width = anv_minify(image->extent.width, level);
886 const unsigned level_height = anv_minify(image->extent.height, level);
887
888 if (image->type == VK_IMAGE_TYPE_3D)
889 layer_count = anv_minify(image->extent.depth, level);
890
891 blorp_clear_depth_stencil(&batch, &depth, &stencil,
892 level, base_layer, layer_count,
893 0, 0, level_width, level_height,
894 clear_depth, pDepthStencil->depth,
895 clear_stencil ? 0xff : 0,
896 pDepthStencil->stencil);
897 }
898 }
899
900 blorp_batch_finish(&batch);
901 }
902
903 struct anv_state
904 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
905 uint32_t num_entries,
906 uint32_t *state_offset)
907 {
908 struct anv_state bt_state =
909 anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
910 state_offset);
911 if (bt_state.map == NULL) {
912 /* We ran out of space. Grab a new binding table block. */
913 MAYBE_UNUSED VkResult result =
914 anv_cmd_buffer_new_binding_table_block(cmd_buffer);
915 assert(result == VK_SUCCESS);
916
917 /* Re-emit state base addresses so we get the new surface state base
918 * address before we start emitting binding tables etc.
919 */
920 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
921
922 bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
923 state_offset);
924 assert(bt_state.map != NULL);
925 }
926
927 return bt_state;
928 }
929
930 static uint32_t
931 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
932 struct anv_state surface_state)
933 {
934 uint32_t state_offset;
935 struct anv_state bt_state =
936 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset);
937
938 uint32_t *bt_map = bt_state.map;
939 bt_map[0] = surface_state.offset + state_offset;
940
941 return bt_state.offset;
942 }
943
944 static void
945 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
946 struct blorp_batch *batch,
947 const VkClearAttachment *attachment,
948 uint32_t rectCount, const VkClearRect *pRects)
949 {
950 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
951 const uint32_t color_att = attachment->colorAttachment;
952 const uint32_t att_idx = subpass->color_attachments[color_att];
953
954 if (att_idx == VK_ATTACHMENT_UNUSED)
955 return;
956
957 struct anv_render_pass_attachment *pass_att =
958 &cmd_buffer->state.pass->attachments[att_idx];
959 struct anv_attachment_state *att_state =
960 &cmd_buffer->state.attachments[att_idx];
961
962 uint32_t binding_table =
963 binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state);
964
965 union isl_color_value clear_color =
966 vk_to_isl_color(attachment->clearValue.color);
967
968 for (uint32_t r = 0; r < rectCount; ++r) {
969 const VkOffset2D offset = pRects[r].rect.offset;
970 const VkExtent2D extent = pRects[r].rect.extent;
971 blorp_clear_attachments(batch, binding_table,
972 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
973 pRects[r].baseArrayLayer,
974 pRects[r].layerCount,
975 offset.x, offset.y,
976 offset.x + extent.width, offset.y + extent.height,
977 true, clear_color, false, 0.0f, 0, 0);
978 }
979 }
980
981 static void
982 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
983 struct blorp_batch *batch,
984 const VkClearAttachment *attachment,
985 uint32_t rectCount, const VkClearRect *pRects)
986 {
987 static const union isl_color_value color_value = { .u32 = { 0, } };
988 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
989 const uint32_t att_idx = subpass->depth_stencil_attachment;
990
991 if (att_idx == VK_ATTACHMENT_UNUSED)
992 return;
993
994 struct anv_render_pass_attachment *pass_att =
995 &cmd_buffer->state.pass->attachments[att_idx];
996
997 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
998 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
999
1000 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
1001 if (clear_depth) {
1002 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
1003 pass_att->format,
1004 VK_IMAGE_ASPECT_DEPTH_BIT,
1005 VK_IMAGE_TILING_OPTIMAL);
1006 }
1007
1008 uint32_t binding_table =
1009 binding_table_for_surface_state(cmd_buffer,
1010 cmd_buffer->state.null_surface_state);
1011
1012 for (uint32_t r = 0; r < rectCount; ++r) {
1013 const VkOffset2D offset = pRects[r].rect.offset;
1014 const VkExtent2D extent = pRects[r].rect.extent;
1015 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1016 blorp_clear_attachments(batch, binding_table,
1017 depth_format, pass_att->samples,
1018 pRects[r].baseArrayLayer,
1019 pRects[r].layerCount,
1020 offset.x, offset.y,
1021 offset.x + extent.width, offset.y + extent.height,
1022 false, color_value,
1023 clear_depth, value.depth,
1024 clear_stencil ? 0xff : 0, value.stencil);
1025 }
1026 }
1027
1028 void anv_CmdClearAttachments(
1029 VkCommandBuffer commandBuffer,
1030 uint32_t attachmentCount,
1031 const VkClearAttachment* pAttachments,
1032 uint32_t rectCount,
1033 const VkClearRect* pRects)
1034 {
1035 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1036
1037 /* Because this gets called within a render pass, we tell blorp not to
1038 * trash our depth and stencil buffers.
1039 */
1040 struct blorp_batch batch;
1041 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1042 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1043
1044 for (uint32_t a = 0; a < attachmentCount; ++a) {
1045 if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
1046 clear_color_attachment(cmd_buffer, &batch,
1047 &pAttachments[a],
1048 rectCount, pRects);
1049 } else {
1050 clear_depth_stencil_attachment(cmd_buffer, &batch,
1051 &pAttachments[a],
1052 rectCount, pRects);
1053 }
1054 }
1055
1056 blorp_batch_finish(&batch);
1057 }
1058
1059 enum subpass_stage {
1060 SUBPASS_STAGE_LOAD,
1061 SUBPASS_STAGE_DRAW,
1062 SUBPASS_STAGE_RESOLVE,
1063 };
1064
1065 static bool
1066 attachment_needs_flush(struct anv_cmd_buffer *cmd_buffer,
1067 struct anv_render_pass_attachment *att,
1068 enum subpass_stage stage)
1069 {
1070 struct anv_render_pass *pass = cmd_buffer->state.pass;
1071 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1072 unsigned subpass_idx = subpass - pass->subpasses;
1073 assert(subpass_idx < pass->subpass_count);
1074
1075 /* We handle this subpass specially based on the current stage */
1076 enum anv_subpass_usage usage = att->subpass_usage[subpass_idx];
1077 switch (stage) {
1078 case SUBPASS_STAGE_LOAD:
1079 if (usage & (ANV_SUBPASS_USAGE_INPUT | ANV_SUBPASS_USAGE_RESOLVE_SRC))
1080 return true;
1081 break;
1082
1083 case SUBPASS_STAGE_DRAW:
1084 if (usage & ANV_SUBPASS_USAGE_RESOLVE_SRC)
1085 return true;
1086 break;
1087
1088 default:
1089 break;
1090 }
1091
1092 for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
1093 usage = att->subpass_usage[s];
1094
1095 /* If this attachment is going to be used as an input in this or any
1096 * future subpass, then we need to flush its cache and invalidate the
1097 * texture cache.
1098 */
1099 if (att->subpass_usage[s] & ANV_SUBPASS_USAGE_INPUT)
1100 return true;
1101
1102 if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
1103 /* We found another subpass that draws to this attachment. We'll
1104 * wait to resolve until then.
1105 */
1106 return false;
1107 }
1108 }
1109
1110 return false;
1111 }
1112
1113 static void
1114 anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer *cmd_buffer,
1115 enum subpass_stage stage)
1116 {
1117 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1118 struct anv_render_pass *pass = cmd_buffer->state.pass;
1119
1120 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1121 uint32_t att = subpass->color_attachments[i];
1122 assert(att < pass->attachment_count);
1123 if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
1124 cmd_buffer->state.pending_pipe_bits |=
1125 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1126 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1127 }
1128 }
1129
1130 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1131 uint32_t att = subpass->depth_stencil_attachment;
1132 assert(att < pass->attachment_count);
1133 if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
1134 cmd_buffer->state.pending_pipe_bits |=
1135 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1136 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1137 }
1138 }
1139 }
1140
1141 static bool
1142 subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
1143 {
1144 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1145 uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
1146
1147 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1148 uint32_t a = cmd_state->subpass->color_attachments[i];
1149 if (cmd_state->attachments[a].pending_clear_aspects) {
1150 return true;
1151 }
1152 }
1153
1154 if (ds != VK_ATTACHMENT_UNUSED &&
1155 cmd_state->attachments[ds].pending_clear_aspects) {
1156 return true;
1157 }
1158
1159 return false;
1160 }
1161
1162 void
1163 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
1164 {
1165 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1166
1167 if (!subpass_needs_clear(cmd_buffer))
1168 return;
1169
1170 /* Because this gets called within a render pass, we tell blorp not to
1171 * trash our depth and stencil buffers.
1172 */
1173 struct blorp_batch batch;
1174 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1175 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1176
1177 VkClearRect clear_rect = {
1178 .rect = cmd_buffer->state.render_area,
1179 .baseArrayLayer = 0,
1180 .layerCount = cmd_buffer->state.framebuffer->layers,
1181 };
1182
1183 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1184 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1185 const uint32_t a = cmd_state->subpass->color_attachments[i];
1186 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
1187
1188 if (!att_state->pending_clear_aspects)
1189 continue;
1190
1191 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1192
1193 struct anv_image_view *iview = fb->attachments[a];
1194 const struct anv_image *image = iview->image;
1195 struct blorp_surf surf;
1196 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1197 att_state->aux_usage, &surf);
1198 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1199
1200 const VkRect2D render_area = cmd_buffer->state.render_area;
1201
1202 if (att_state->fast_clear) {
1203 blorp_fast_clear(&batch, &surf, iview->isl.format,
1204 iview->isl.base_level,
1205 iview->isl.base_array_layer, fb->layers,
1206 render_area.offset.x, render_area.offset.y,
1207 render_area.offset.x + render_area.extent.width,
1208 render_area.offset.y + render_area.extent.height);
1209
1210 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1211 *
1212 * "After Render target fast clear, pipe-control with color cache
1213 * write-flush must be issued before sending any DRAW commands on
1214 * that render target."
1215 */
1216 cmd_buffer->state.pending_pipe_bits |=
1217 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1218 } else {
1219 blorp_clear(&batch, &surf, iview->isl.format, iview->isl.swizzle,
1220 iview->isl.base_level,
1221 iview->isl.base_array_layer, fb->layers,
1222 render_area.offset.x, render_area.offset.y,
1223 render_area.offset.x + render_area.extent.width,
1224 render_area.offset.y + render_area.extent.height,
1225 surf.clear_color, NULL);
1226 }
1227
1228 att_state->pending_clear_aspects = 0;
1229 }
1230
1231 const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
1232
1233 if (ds != VK_ATTACHMENT_UNUSED &&
1234 cmd_state->attachments[ds].pending_clear_aspects) {
1235
1236 VkClearAttachment clear_att = {
1237 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1238 .clearValue = cmd_state->attachments[ds].clear_value,
1239 };
1240
1241 clear_depth_stencil_attachment(cmd_buffer, &batch,
1242 &clear_att, 1, &clear_rect);
1243
1244 cmd_state->attachments[ds].pending_clear_aspects = 0;
1245 }
1246
1247 blorp_batch_finish(&batch);
1248
1249 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_LOAD);
1250 }
1251
1252 static void
1253 resolve_image(struct blorp_batch *batch,
1254 const struct anv_image *src_image,
1255 uint32_t src_level, uint32_t src_layer,
1256 const struct anv_image *dst_image,
1257 uint32_t dst_level, uint32_t dst_layer,
1258 VkImageAspectFlags aspect_mask,
1259 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1260 uint32_t width, uint32_t height)
1261 {
1262 assert(src_image->type == VK_IMAGE_TYPE_2D);
1263 assert(src_image->samples > 1);
1264 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1265 assert(dst_image->samples == 1);
1266
1267 uint32_t a;
1268 for_each_bit(a, aspect_mask) {
1269 VkImageAspectFlagBits aspect = 1 << a;
1270
1271 struct blorp_surf src_surf, dst_surf;
1272 get_blorp_surf_for_anv_image(src_image, aspect,
1273 src_image->aux_usage, &src_surf);
1274 get_blorp_surf_for_anv_image(dst_image, aspect,
1275 dst_image->aux_usage, &dst_surf);
1276
1277 blorp_blit(batch,
1278 &src_surf, src_level, src_layer,
1279 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1280 &dst_surf, dst_level, dst_layer,
1281 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1282 src_x, src_y, src_x + width, src_y + height,
1283 dst_x, dst_y, dst_x + width, dst_y + height,
1284 0x2600 /* GL_NEAREST */, false, false);
1285 }
1286 }
1287
1288 void anv_CmdResolveImage(
1289 VkCommandBuffer commandBuffer,
1290 VkImage srcImage,
1291 VkImageLayout srcImageLayout,
1292 VkImage dstImage,
1293 VkImageLayout dstImageLayout,
1294 uint32_t regionCount,
1295 const VkImageResolve* pRegions)
1296 {
1297 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1298 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1299 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1300
1301 struct blorp_batch batch;
1302 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1303
1304 for (uint32_t r = 0; r < regionCount; r++) {
1305 assert(pRegions[r].srcSubresource.aspectMask ==
1306 pRegions[r].dstSubresource.aspectMask);
1307 assert(pRegions[r].srcSubresource.layerCount ==
1308 pRegions[r].dstSubresource.layerCount);
1309
1310 const uint32_t layer_count = pRegions[r].dstSubresource.layerCount;
1311
1312 for (uint32_t layer = 0; layer < layer_count; layer++) {
1313 resolve_image(&batch,
1314 src_image, pRegions[r].srcSubresource.mipLevel,
1315 pRegions[r].srcSubresource.baseArrayLayer + layer,
1316 dst_image, pRegions[r].dstSubresource.mipLevel,
1317 pRegions[r].dstSubresource.baseArrayLayer + layer,
1318 pRegions[r].dstSubresource.aspectMask,
1319 pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
1320 pRegions[r].dstOffset.x, pRegions[r].dstOffset.y,
1321 pRegions[r].extent.width, pRegions[r].extent.height);
1322 }
1323 }
1324
1325 blorp_batch_finish(&batch);
1326 }
1327
1328 static void
1329 ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
1330 struct blorp_batch *batch,
1331 uint32_t att)
1332 {
1333 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1334 struct anv_attachment_state *att_state =
1335 &cmd_buffer->state.attachments[att];
1336
1337 if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
1338 return; /* Nothing to resolve */
1339
1340 assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
1341 att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
1342
1343 struct anv_render_pass *pass = cmd_buffer->state.pass;
1344 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1345 unsigned subpass_idx = subpass - pass->subpasses;
1346 assert(subpass_idx < pass->subpass_count);
1347
1348 /* Scan forward to see what all ways this attachment will be used.
1349 * Ideally, we would like to resolve in the same subpass as the last write
1350 * of a particular attachment. That way we only resolve once but it's
1351 * still hot in the cache.
1352 */
1353 bool found_draw = false;
1354 enum anv_subpass_usage usage = 0;
1355 for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
1356 usage |= pass->attachments[att].subpass_usage[s];
1357
1358 if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
1359 /* We found another subpass that draws to this attachment. We'll
1360 * wait to resolve until then.
1361 */
1362 found_draw = true;
1363 break;
1364 }
1365 }
1366
1367 struct anv_image_view *iview = fb->attachments[att];
1368 const struct anv_image *image = iview->image;
1369 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1370
1371 enum blorp_fast_clear_op resolve_op = BLORP_FAST_CLEAR_OP_NONE;
1372 if (!found_draw) {
1373 /* This is the last subpass that writes to this attachment so we need to
1374 * resolve here. Ideally, we would like to only resolve if the storeOp
1375 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1376 * that the CCS bits are set to "resolved" because there may be copy or
1377 * blit operations (which may ignore CCS) between now and the next time
1378 * we render and we need to ensure that anything they write will be
1379 * respected in the next render. Unfortunately, the hardware does not
1380 * provide us with any sort of "invalidate" pass that sets the CCS to
1381 * "resolved" without writing to the render target.
1382 */
1383 if (iview->image->aux_usage != ISL_AUX_USAGE_CCS_E) {
1384 /* The image destination surface doesn't support compression outside
1385 * the render pass. We need a full resolve.
1386 */
1387 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1388 } else if (att_state->fast_clear) {
1389 /* We don't know what to do with clear colors outside the render
1390 * pass. We need a partial resolve.
1391 */
1392 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1393 } else {
1394 /* The image "natively" supports all the compression we care about
1395 * and we don't need to resolve at all. If this is the case, we also
1396 * don't need to resolve for any of the input attachment cases below.
1397 */
1398 }
1399 } else if (usage & ANV_SUBPASS_USAGE_INPUT) {
1400 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1401 * can frequently sample from them with no resolves at all.
1402 */
1403 if (att_state->aux_usage != att_state->input_aux_usage) {
1404 assert(att_state->input_aux_usage == ISL_AUX_USAGE_NONE);
1405 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1406 } else if (!att_state->clear_color_is_zero_one) {
1407 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1408 *
1409 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1410 * is fast cleared with non-0/1 clear value, this RT must be
1411 * partially resolved (refer to Partial Resolve operation) before
1412 * binding this surface to Sampler."
1413 */
1414 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1415 }
1416 }
1417
1418 if (resolve_op == BLORP_FAST_CLEAR_OP_NONE)
1419 return;
1420
1421 struct blorp_surf surf;
1422 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1423 att_state->aux_usage, &surf);
1424 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1425
1426 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1427 *
1428 * "When performing a render target resolve, PIPE_CONTROL with end of
1429 * pipe sync must be delivered."
1430 *
1431 * This comment is a bit cryptic and doesn't really tell you what's going
1432 * or what's really needed. It appears that fast clear ops are not
1433 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1434 * to ensure that the contents of the previous draw hit the render target
1435 * before we resolve and then use a second PIPE_CONTROL after the resolve
1436 * to ensure that it is completed before any additional drawing occurs.
1437 */
1438 cmd_buffer->state.pending_pipe_bits |=
1439 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1440
1441 for (uint32_t layer = 0; layer < fb->layers; layer++) {
1442 blorp_ccs_resolve(batch, &surf,
1443 iview->isl.base_level,
1444 iview->isl.base_array_layer + layer,
1445 iview->isl.format, resolve_op);
1446 }
1447
1448 cmd_buffer->state.pending_pipe_bits |=
1449 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1450
1451 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1452 att_state->fast_clear = false;
1453 }
1454
1455 void
1456 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
1457 {
1458 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1459 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1460
1461
1462 struct blorp_batch batch;
1463 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1464
1465 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1466 ccs_resolve_attachment(cmd_buffer, &batch,
1467 subpass->color_attachments[i]);
1468 }
1469
1470 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_DRAW);
1471
1472 if (subpass->has_resolve) {
1473 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1474 uint32_t src_att = subpass->color_attachments[i];
1475 uint32_t dst_att = subpass->resolve_attachments[i];
1476
1477 if (dst_att == VK_ATTACHMENT_UNUSED)
1478 continue;
1479
1480 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
1481 /* From the Vulkan 1.0 spec:
1482 *
1483 * If the first use of an attachment in a render pass is as a
1484 * resolve attachment, then the loadOp is effectively ignored
1485 * as the resolve is guaranteed to overwrite all pixels in the
1486 * render area.
1487 */
1488 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
1489 }
1490
1491 struct anv_image_view *src_iview = fb->attachments[src_att];
1492 struct anv_image_view *dst_iview = fb->attachments[dst_att];
1493
1494 const VkRect2D render_area = cmd_buffer->state.render_area;
1495
1496 assert(src_iview->aspect_mask == dst_iview->aspect_mask);
1497 resolve_image(&batch, src_iview->image,
1498 src_iview->isl.base_level,
1499 src_iview->isl.base_array_layer,
1500 dst_iview->image,
1501 dst_iview->isl.base_level,
1502 dst_iview->isl.base_array_layer,
1503 src_iview->aspect_mask,
1504 render_area.offset.x, render_area.offset.y,
1505 render_area.offset.x, render_area.offset.y,
1506 render_area.extent.width, render_area.extent.height);
1507
1508 ccs_resolve_attachment(cmd_buffer, &batch, dst_att);
1509 }
1510
1511 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_RESOLVE);
1512 }
1513
1514 blorp_batch_finish(&batch);
1515 }