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anv: Remove state flush.
[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_batch *batch,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct blorp_context *blorp = batch->blorp;
32 struct anv_device *device = blorp->driver_ctx;
33
34 /* The default cache must be a real cache */
35 assert(device->default_pipeline_cache.cache);
36
37 struct anv_shader_bin *bin =
38 anv_pipeline_cache_search(&device->default_pipeline_cache, key, key_size);
39 if (!bin)
40 return false;
41
42 /* The cache already has a reference and it's not going anywhere so there
43 * is no need to hold a second reference.
44 */
45 anv_shader_bin_unref(device, bin);
46
47 *kernel_out = bin->kernel.offset;
48 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
49
50 return true;
51 }
52
53 static bool
54 upload_blorp_shader(struct blorp_batch *batch,
55 const void *key, uint32_t key_size,
56 const void *kernel, uint32_t kernel_size,
57 const struct brw_stage_prog_data *prog_data,
58 uint32_t prog_data_size,
59 uint32_t *kernel_out, void *prog_data_out)
60 {
61 struct blorp_context *blorp = batch->blorp;
62 struct anv_device *device = blorp->driver_ctx;
63
64 /* The blorp cache must be a real cache */
65 assert(device->default_pipeline_cache.cache);
66
67 struct anv_pipeline_bind_map bind_map = {
68 .surface_count = 0,
69 .sampler_count = 0,
70 };
71
72 struct anv_shader_bin *bin =
73 anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache,
74 key, key_size, kernel, kernel_size,
75 NULL, 0,
76 prog_data, prog_data_size, &bind_map);
77
78 if (!bin)
79 return false;
80
81 /* The cache already has a reference and it's not going anywhere so there
82 * is no need to hold a second reference.
83 */
84 anv_shader_bin_unref(device, bin);
85
86 *kernel_out = bin->kernel.offset;
87 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
88
89 return true;
90 }
91
92 void
93 anv_device_init_blorp(struct anv_device *device)
94 {
95 blorp_init(&device->blorp, device, &device->isl_dev);
96 device->blorp.compiler = device->instance->physicalDevice.compiler;
97 device->blorp.lookup_shader = lookup_blorp_shader;
98 device->blorp.upload_shader = upload_blorp_shader;
99 switch (device->info.gen) {
100 case 7:
101 if (device->info.is_haswell) {
102 device->blorp.exec = gen75_blorp_exec;
103 } else {
104 device->blorp.exec = gen7_blorp_exec;
105 }
106 break;
107 case 8:
108 device->blorp.exec = gen8_blorp_exec;
109 break;
110 case 9:
111 device->blorp.exec = gen9_blorp_exec;
112 break;
113 case 10:
114 device->blorp.exec = gen10_blorp_exec;
115 break;
116 case 11:
117 device->blorp.exec = gen11_blorp_exec;
118 break;
119 default:
120 unreachable("Unknown hardware generation");
121 }
122 }
123
124 void
125 anv_device_finish_blorp(struct anv_device *device)
126 {
127 blorp_finish(&device->blorp);
128 }
129
130 static void
131 get_blorp_surf_for_anv_buffer(struct anv_device *device,
132 struct anv_buffer *buffer, uint64_t offset,
133 uint32_t width, uint32_t height,
134 uint32_t row_pitch, enum isl_format format,
135 struct blorp_surf *blorp_surf,
136 struct isl_surf *isl_surf)
137 {
138 const struct isl_format_layout *fmtl =
139 isl_format_get_layout(format);
140 bool ok UNUSED;
141
142 /* ASTC is the only format which doesn't support linear layouts.
143 * Create an equivalently sized surface with ISL to get around this.
144 */
145 if (fmtl->txc == ISL_TXC_ASTC) {
146 /* Use an equivalently sized format */
147 format = ISL_FORMAT_R32G32B32A32_UINT;
148 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
149
150 /* Shrink the dimensions for the new format */
151 width = DIV_ROUND_UP(width, fmtl->bw);
152 height = DIV_ROUND_UP(height, fmtl->bh);
153 }
154
155 *blorp_surf = (struct blorp_surf) {
156 .surf = isl_surf,
157 .addr = {
158 .buffer = buffer->address.bo,
159 .offset = buffer->address.offset + offset,
160 .mocs = anv_mocs_for_bo(device, buffer->address.bo),
161 },
162 };
163
164 ok = isl_surf_init(&device->isl_dev, isl_surf,
165 .dim = ISL_SURF_DIM_2D,
166 .format = format,
167 .width = width,
168 .height = height,
169 .depth = 1,
170 .levels = 1,
171 .array_len = 1,
172 .samples = 1,
173 .row_pitch_B = row_pitch,
174 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
175 ISL_SURF_USAGE_RENDER_TARGET_BIT,
176 .tiling_flags = ISL_TILING_LINEAR_BIT);
177 assert(ok);
178 }
179
180 /* Pick something high enough that it won't be used in core and low enough it
181 * will never map to an extension.
182 */
183 #define ANV_IMAGE_LAYOUT_EXPLICIT_AUX (VkImageLayout)10000000
184
185 static struct blorp_address
186 anv_to_blorp_address(struct anv_address addr)
187 {
188 return (struct blorp_address) {
189 .buffer = addr.bo,
190 .offset = addr.offset,
191 };
192 }
193
194 static void
195 get_blorp_surf_for_anv_image(const struct anv_device *device,
196 const struct anv_image *image,
197 VkImageAspectFlags aspect,
198 VkImageLayout layout,
199 enum isl_aux_usage aux_usage,
200 struct blorp_surf *blorp_surf)
201 {
202 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
203
204 if (layout != ANV_IMAGE_LAYOUT_EXPLICIT_AUX)
205 aux_usage = anv_layout_to_aux_usage(&device->info, image, aspect, layout);
206
207 const struct anv_surface *surface = &image->planes[plane].surface;
208 *blorp_surf = (struct blorp_surf) {
209 .surf = &surface->isl,
210 .addr = {
211 .buffer = image->planes[plane].address.bo,
212 .offset = image->planes[plane].address.offset + surface->offset,
213 .mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo),
214 },
215 };
216
217 if (aux_usage != ISL_AUX_USAGE_NONE) {
218 const struct anv_surface *aux_surface = &image->planes[plane].aux_surface;
219 blorp_surf->aux_surf = &aux_surface->isl,
220 blorp_surf->aux_addr = (struct blorp_address) {
221 .buffer = image->planes[plane].address.bo,
222 .offset = image->planes[plane].address.offset + aux_surface->offset,
223 .mocs = anv_mocs_for_bo(device, image->planes[plane].address.bo),
224 };
225 blorp_surf->aux_usage = aux_usage;
226
227 /* If we're doing a partial resolve, then we need the indirect clear
228 * color. If we are doing a fast clear and want to store/update the
229 * clear color, we also pass the address to blorp, otherwise it will only
230 * stomp the CCS to a particular value and won't care about format or
231 * clear value
232 */
233 if (aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
234 const struct anv_address clear_color_addr =
235 anv_image_get_clear_color_addr(device, image, aspect);
236 blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
237 } else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT
238 && device->info.gen >= 10) {
239 /* Vulkan always clears to 1.0. On gen < 10, we set that directly in
240 * the state packet. For gen >= 10, must provide the clear value in a
241 * buffer. We have a single global buffer that stores the 1.0 value.
242 */
243 const struct anv_address clear_color_addr = (struct anv_address) {
244 .bo = (struct anv_bo *)&device->hiz_clear_bo
245 };
246 blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
247 }
248 }
249 }
250
251 void anv_CmdCopyImage(
252 VkCommandBuffer commandBuffer,
253 VkImage srcImage,
254 VkImageLayout srcImageLayout,
255 VkImage dstImage,
256 VkImageLayout dstImageLayout,
257 uint32_t regionCount,
258 const VkImageCopy* pRegions)
259 {
260 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
261 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
262 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
263
264 struct blorp_batch batch;
265 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
266
267 for (unsigned r = 0; r < regionCount; r++) {
268 VkOffset3D srcOffset =
269 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
270 VkOffset3D dstOffset =
271 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
272 VkExtent3D extent =
273 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
274
275 const uint32_t dst_level = pRegions[r].dstSubresource.mipLevel;
276 unsigned dst_base_layer, layer_count;
277 if (dst_image->type == VK_IMAGE_TYPE_3D) {
278 dst_base_layer = pRegions[r].dstOffset.z;
279 layer_count = pRegions[r].extent.depth;
280 } else {
281 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
282 layer_count =
283 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
284 }
285
286 const uint32_t src_level = pRegions[r].srcSubresource.mipLevel;
287 unsigned src_base_layer;
288 if (src_image->type == VK_IMAGE_TYPE_3D) {
289 src_base_layer = pRegions[r].srcOffset.z;
290 } else {
291 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
292 assert(layer_count ==
293 anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
294 }
295
296 VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask,
297 dst_mask = pRegions[r].dstSubresource.aspectMask;
298
299 assert(anv_image_aspects_compatible(src_mask, dst_mask));
300
301 if (util_bitcount(src_mask) > 1) {
302 uint32_t aspect_bit;
303 anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
304 struct blorp_surf src_surf, dst_surf;
305 get_blorp_surf_for_anv_image(cmd_buffer->device,
306 src_image, 1UL << aspect_bit,
307 srcImageLayout, ISL_AUX_USAGE_NONE,
308 &src_surf);
309 get_blorp_surf_for_anv_image(cmd_buffer->device,
310 dst_image, 1UL << aspect_bit,
311 dstImageLayout, ISL_AUX_USAGE_NONE,
312 &dst_surf);
313 anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
314 1UL << aspect_bit,
315 dst_surf.aux_usage, dst_level,
316 dst_base_layer, layer_count);
317
318 for (unsigned i = 0; i < layer_count; i++) {
319 blorp_copy(&batch, &src_surf, src_level, src_base_layer + i,
320 &dst_surf, dst_level, dst_base_layer + i,
321 srcOffset.x, srcOffset.y,
322 dstOffset.x, dstOffset.y,
323 extent.width, extent.height);
324 }
325 }
326 } else {
327 struct blorp_surf src_surf, dst_surf;
328 get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
329 srcImageLayout, ISL_AUX_USAGE_NONE,
330 &src_surf);
331 get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask,
332 dstImageLayout, ISL_AUX_USAGE_NONE,
333 &dst_surf);
334 anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image, dst_mask,
335 dst_surf.aux_usage, dst_level,
336 dst_base_layer, layer_count);
337
338 for (unsigned i = 0; i < layer_count; i++) {
339 blorp_copy(&batch, &src_surf, src_level, src_base_layer + i,
340 &dst_surf, dst_level, dst_base_layer + i,
341 srcOffset.x, srcOffset.y,
342 dstOffset.x, dstOffset.y,
343 extent.width, extent.height);
344 }
345 }
346 }
347
348 blorp_batch_finish(&batch);
349 }
350
351 static void
352 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
353 struct anv_buffer *anv_buffer,
354 struct anv_image *anv_image,
355 VkImageLayout image_layout,
356 uint32_t regionCount,
357 const VkBufferImageCopy* pRegions,
358 bool buffer_to_image)
359 {
360 struct blorp_batch batch;
361 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
362
363 struct {
364 struct blorp_surf surf;
365 uint32_t level;
366 VkOffset3D offset;
367 } image, buffer, *src, *dst;
368
369 buffer.level = 0;
370 buffer.offset = (VkOffset3D) { 0, 0, 0 };
371
372 if (buffer_to_image) {
373 src = &buffer;
374 dst = &image;
375 } else {
376 src = &image;
377 dst = &buffer;
378 }
379
380 for (unsigned r = 0; r < regionCount; r++) {
381 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
382
383 get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
384 image_layout, ISL_AUX_USAGE_NONE,
385 &image.surf);
386 image.offset =
387 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
388 image.level = pRegions[r].imageSubresource.mipLevel;
389
390 VkExtent3D extent =
391 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
392 if (anv_image->type != VK_IMAGE_TYPE_3D) {
393 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
394 extent.depth =
395 anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
396 }
397
398 const enum isl_format buffer_format =
399 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
400 aspect, VK_IMAGE_TILING_LINEAR);
401
402 const VkExtent3D bufferImageExtent = {
403 .width = pRegions[r].bufferRowLength ?
404 pRegions[r].bufferRowLength : extent.width,
405 .height = pRegions[r].bufferImageHeight ?
406 pRegions[r].bufferImageHeight : extent.height,
407 };
408
409 const struct isl_format_layout *buffer_fmtl =
410 isl_format_get_layout(buffer_format);
411
412 const uint32_t buffer_row_pitch =
413 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
414 (buffer_fmtl->bpb / 8);
415
416 const uint32_t buffer_layer_stride =
417 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
418 buffer_row_pitch;
419
420 struct isl_surf buffer_isl_surf;
421 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
422 anv_buffer, pRegions[r].bufferOffset,
423 extent.width, extent.height,
424 buffer_row_pitch, buffer_format,
425 &buffer.surf, &buffer_isl_surf);
426
427 if (&image == dst) {
428 anv_cmd_buffer_mark_image_written(cmd_buffer, anv_image,
429 aspect, dst->surf.aux_usage,
430 dst->level,
431 dst->offset.z, extent.depth);
432 }
433
434 for (unsigned z = 0; z < extent.depth; z++) {
435 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
436 &dst->surf, dst->level, dst->offset.z,
437 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
438 extent.width, extent.height);
439
440 image.offset.z++;
441 buffer.surf.addr.offset += buffer_layer_stride;
442 }
443 }
444
445 blorp_batch_finish(&batch);
446 }
447
448 void anv_CmdCopyBufferToImage(
449 VkCommandBuffer commandBuffer,
450 VkBuffer srcBuffer,
451 VkImage dstImage,
452 VkImageLayout dstImageLayout,
453 uint32_t regionCount,
454 const VkBufferImageCopy* pRegions)
455 {
456 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
457 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
458 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
459
460 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image, dstImageLayout,
461 regionCount, pRegions, true);
462 }
463
464 void anv_CmdCopyImageToBuffer(
465 VkCommandBuffer commandBuffer,
466 VkImage srcImage,
467 VkImageLayout srcImageLayout,
468 VkBuffer dstBuffer,
469 uint32_t regionCount,
470 const VkBufferImageCopy* pRegions)
471 {
472 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
473 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
474 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
475
476 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image, srcImageLayout,
477 regionCount, pRegions, false);
478 }
479
480 static bool
481 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
482 {
483 bool flip = false;
484 if (*src0 > *src1) {
485 unsigned tmp = *src0;
486 *src0 = *src1;
487 *src1 = tmp;
488 flip = !flip;
489 }
490
491 if (*dst0 > *dst1) {
492 unsigned tmp = *dst0;
493 *dst0 = *dst1;
494 *dst1 = tmp;
495 flip = !flip;
496 }
497
498 return flip;
499 }
500
501 void anv_CmdBlitImage(
502 VkCommandBuffer commandBuffer,
503 VkImage srcImage,
504 VkImageLayout srcImageLayout,
505 VkImage dstImage,
506 VkImageLayout dstImageLayout,
507 uint32_t regionCount,
508 const VkImageBlit* pRegions,
509 VkFilter filter)
510
511 {
512 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
513 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
514 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
515
516 struct blorp_surf src, dst;
517
518 enum blorp_filter blorp_filter;
519 switch (filter) {
520 case VK_FILTER_NEAREST:
521 blorp_filter = BLORP_FILTER_NEAREST;
522 break;
523 case VK_FILTER_LINEAR:
524 blorp_filter = BLORP_FILTER_BILINEAR;
525 break;
526 default:
527 unreachable("Invalid filter");
528 }
529
530 struct blorp_batch batch;
531 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
532
533 for (unsigned r = 0; r < regionCount; r++) {
534 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
535 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
536
537 assert(anv_image_aspects_compatible(src_res->aspectMask,
538 dst_res->aspectMask));
539
540 uint32_t aspect_bit;
541 anv_foreach_image_aspect_bit(aspect_bit, src_image, src_res->aspectMask) {
542 get_blorp_surf_for_anv_image(cmd_buffer->device,
543 src_image, 1U << aspect_bit,
544 srcImageLayout, ISL_AUX_USAGE_NONE, &src);
545 get_blorp_surf_for_anv_image(cmd_buffer->device,
546 dst_image, 1U << aspect_bit,
547 dstImageLayout, ISL_AUX_USAGE_NONE, &dst);
548
549 struct anv_format_plane src_format =
550 anv_get_format_plane(&cmd_buffer->device->info, src_image->vk_format,
551 1U << aspect_bit, src_image->tiling);
552 struct anv_format_plane dst_format =
553 anv_get_format_plane(&cmd_buffer->device->info, dst_image->vk_format,
554 1U << aspect_bit, dst_image->tiling);
555
556 unsigned dst_start, dst_end;
557 if (dst_image->type == VK_IMAGE_TYPE_3D) {
558 assert(dst_res->baseArrayLayer == 0);
559 dst_start = pRegions[r].dstOffsets[0].z;
560 dst_end = pRegions[r].dstOffsets[1].z;
561 } else {
562 dst_start = dst_res->baseArrayLayer;
563 dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
564 }
565
566 unsigned src_start, src_end;
567 if (src_image->type == VK_IMAGE_TYPE_3D) {
568 assert(src_res->baseArrayLayer == 0);
569 src_start = pRegions[r].srcOffsets[0].z;
570 src_end = pRegions[r].srcOffsets[1].z;
571 } else {
572 src_start = src_res->baseArrayLayer;
573 src_end = src_start + anv_get_layerCount(src_image, src_res);
574 }
575
576 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
577 float src_z_step = (float)(src_end + 1 - src_start) /
578 (float)(dst_end + 1 - dst_start);
579
580 if (flip_z) {
581 src_start = src_end;
582 src_z_step *= -1;
583 }
584
585 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
586 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
587 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
588 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
589 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
590
591 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
592 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
593 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
594 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
595 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
596
597 const unsigned num_layers = dst_end - dst_start;
598 anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
599 1U << aspect_bit,
600 dst.aux_usage,
601 dst_res->mipLevel,
602 dst_start, num_layers);
603
604 for (unsigned i = 0; i < num_layers; i++) {
605 unsigned dst_z = dst_start + i;
606 unsigned src_z = src_start + i * src_z_step;
607
608 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
609 src_format.isl_format, src_format.swizzle,
610 &dst, dst_res->mipLevel, dst_z,
611 dst_format.isl_format, dst_format.swizzle,
612 src_x0, src_y0, src_x1, src_y1,
613 dst_x0, dst_y0, dst_x1, dst_y1,
614 blorp_filter, flip_x, flip_y);
615 }
616 }
617 }
618
619 blorp_batch_finish(&batch);
620 }
621
622 static enum isl_format
623 isl_format_for_size(unsigned size_B)
624 {
625 switch (size_B) {
626 case 4: return ISL_FORMAT_R32_UINT;
627 case 8: return ISL_FORMAT_R32G32_UINT;
628 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
629 default:
630 unreachable("Not a power-of-two format size");
631 }
632 }
633
634 /**
635 * Returns the greatest common divisor of a and b that is a power of two.
636 */
637 static uint64_t
638 gcd_pow2_u64(uint64_t a, uint64_t b)
639 {
640 assert(a > 0 || b > 0);
641
642 unsigned a_log2 = ffsll(a) - 1;
643 unsigned b_log2 = ffsll(b) - 1;
644
645 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
646 * case, the MIN2() will take the other one. If both are 0 then we will
647 * hit the assert above.
648 */
649 return 1 << MIN2(a_log2, b_log2);
650 }
651
652 /* This is maximum possible width/height our HW can handle */
653 #define MAX_SURFACE_DIM (1ull << 14)
654
655 void anv_CmdCopyBuffer(
656 VkCommandBuffer commandBuffer,
657 VkBuffer srcBuffer,
658 VkBuffer dstBuffer,
659 uint32_t regionCount,
660 const VkBufferCopy* pRegions)
661 {
662 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
663 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
664 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
665
666 struct blorp_batch batch;
667 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
668
669 for (unsigned r = 0; r < regionCount; r++) {
670 struct blorp_address src = {
671 .buffer = src_buffer->address.bo,
672 .offset = src_buffer->address.offset + pRegions[r].srcOffset,
673 .mocs = anv_mocs_for_bo(cmd_buffer->device, src_buffer->address.bo),
674 };
675 struct blorp_address dst = {
676 .buffer = dst_buffer->address.bo,
677 .offset = dst_buffer->address.offset + pRegions[r].dstOffset,
678 .mocs = anv_mocs_for_bo(cmd_buffer->device, dst_buffer->address.bo),
679 };
680
681 blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
682 }
683
684 blorp_batch_finish(&batch);
685 }
686
687 void anv_CmdUpdateBuffer(
688 VkCommandBuffer commandBuffer,
689 VkBuffer dstBuffer,
690 VkDeviceSize dstOffset,
691 VkDeviceSize dataSize,
692 const void* pData)
693 {
694 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
695 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
696
697 struct blorp_batch batch;
698 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
699
700 /* We can't quite grab a full block because the state stream needs a
701 * little data at the top to build its linked list.
702 */
703 const uint32_t max_update_size =
704 cmd_buffer->device->dynamic_state_pool.block_size - 64;
705
706 assert(max_update_size < MAX_SURFACE_DIM * 4);
707
708 /* We're about to read data that was written from the CPU. Flush the
709 * texture cache so we don't get anything stale.
710 */
711 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
712
713 while (dataSize) {
714 const uint32_t copy_size = MIN2(dataSize, max_update_size);
715
716 struct anv_state tmp_data =
717 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
718
719 memcpy(tmp_data.map, pData, copy_size);
720
721 struct blorp_address src = {
722 .buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
723 .offset = tmp_data.offset,
724 .mocs = cmd_buffer->device->default_mocs,
725 };
726 struct blorp_address dst = {
727 .buffer = dst_buffer->address.bo,
728 .offset = dst_buffer->address.offset + dstOffset,
729 .mocs = anv_mocs_for_bo(cmd_buffer->device, dst_buffer->address.bo),
730 };
731
732 blorp_buffer_copy(&batch, src, dst, copy_size);
733
734 dataSize -= copy_size;
735 dstOffset += copy_size;
736 pData = (void *)pData + copy_size;
737 }
738
739 blorp_batch_finish(&batch);
740 }
741
742 void anv_CmdFillBuffer(
743 VkCommandBuffer commandBuffer,
744 VkBuffer dstBuffer,
745 VkDeviceSize dstOffset,
746 VkDeviceSize fillSize,
747 uint32_t data)
748 {
749 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
750 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
751 struct blorp_surf surf;
752 struct isl_surf isl_surf;
753
754 struct blorp_batch batch;
755 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
756
757 fillSize = anv_buffer_get_range(dst_buffer, dstOffset, fillSize);
758
759 /* From the Vulkan spec:
760 *
761 * "size is the number of bytes to fill, and must be either a multiple
762 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
763 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
764 * buffer is not a multiple of 4, then the nearest smaller multiple is
765 * used."
766 */
767 fillSize &= ~3ull;
768
769 /* First, we compute the biggest format that can be used with the
770 * given offsets and size.
771 */
772 int bs = 16;
773 bs = gcd_pow2_u64(bs, dstOffset);
774 bs = gcd_pow2_u64(bs, fillSize);
775 enum isl_format isl_format = isl_format_for_size(bs);
776
777 union isl_color_value color = {
778 .u32 = { data, data, data, data },
779 };
780
781 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
782 while (fillSize >= max_fill_size) {
783 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
784 dst_buffer, dstOffset,
785 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
786 MAX_SURFACE_DIM * bs, isl_format,
787 &surf, &isl_surf);
788
789 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
790 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
791 color, NULL);
792 fillSize -= max_fill_size;
793 dstOffset += max_fill_size;
794 }
795
796 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
797 assert(height < MAX_SURFACE_DIM);
798 if (height != 0) {
799 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
800 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
801 dst_buffer, dstOffset,
802 MAX_SURFACE_DIM, height,
803 MAX_SURFACE_DIM * bs, isl_format,
804 &surf, &isl_surf);
805
806 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
807 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
808 color, NULL);
809 fillSize -= rect_fill_size;
810 dstOffset += rect_fill_size;
811 }
812
813 if (fillSize != 0) {
814 const uint32_t width = fillSize / bs;
815 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
816 dst_buffer, dstOffset,
817 width, 1,
818 width * bs, isl_format,
819 &surf, &isl_surf);
820
821 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
822 0, 0, 1, 0, 0, width, 1,
823 color, NULL);
824 }
825
826 blorp_batch_finish(&batch);
827 }
828
829 void anv_CmdClearColorImage(
830 VkCommandBuffer commandBuffer,
831 VkImage _image,
832 VkImageLayout imageLayout,
833 const VkClearColorValue* pColor,
834 uint32_t rangeCount,
835 const VkImageSubresourceRange* pRanges)
836 {
837 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
838 ANV_FROM_HANDLE(anv_image, image, _image);
839
840 static const bool color_write_disable[4] = { false, false, false, false };
841
842 struct blorp_batch batch;
843 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
844
845
846 for (unsigned r = 0; r < rangeCount; r++) {
847 if (pRanges[r].aspectMask == 0)
848 continue;
849
850 assert(pRanges[r].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
851
852 struct blorp_surf surf;
853 get_blorp_surf_for_anv_image(cmd_buffer->device,
854 image, pRanges[r].aspectMask,
855 imageLayout, ISL_AUX_USAGE_NONE, &surf);
856
857 struct anv_format_plane src_format =
858 anv_get_format_plane(&cmd_buffer->device->info, image->vk_format,
859 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
860
861 unsigned base_layer = pRanges[r].baseArrayLayer;
862 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
863
864 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
865 const unsigned level = pRanges[r].baseMipLevel + i;
866 const unsigned level_width = anv_minify(image->extent.width, level);
867 const unsigned level_height = anv_minify(image->extent.height, level);
868
869 if (image->type == VK_IMAGE_TYPE_3D) {
870 base_layer = 0;
871 layer_count = anv_minify(image->extent.depth, level);
872 }
873
874 anv_cmd_buffer_mark_image_written(cmd_buffer, image,
875 pRanges[r].aspectMask,
876 surf.aux_usage, level,
877 base_layer, layer_count);
878
879 blorp_clear(&batch, &surf,
880 src_format.isl_format, src_format.swizzle,
881 level, base_layer, layer_count,
882 0, 0, level_width, level_height,
883 vk_to_isl_color(*pColor), color_write_disable);
884 }
885 }
886
887 blorp_batch_finish(&batch);
888 }
889
890 void anv_CmdClearDepthStencilImage(
891 VkCommandBuffer commandBuffer,
892 VkImage image_h,
893 VkImageLayout imageLayout,
894 const VkClearDepthStencilValue* pDepthStencil,
895 uint32_t rangeCount,
896 const VkImageSubresourceRange* pRanges)
897 {
898 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
899 ANV_FROM_HANDLE(anv_image, image, image_h);
900
901 struct blorp_batch batch;
902 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
903
904 struct blorp_surf depth, stencil;
905 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
906 get_blorp_surf_for_anv_image(cmd_buffer->device,
907 image, VK_IMAGE_ASPECT_DEPTH_BIT,
908 imageLayout, ISL_AUX_USAGE_NONE, &depth);
909 } else {
910 memset(&depth, 0, sizeof(depth));
911 }
912
913 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
914 get_blorp_surf_for_anv_image(cmd_buffer->device,
915 image, VK_IMAGE_ASPECT_STENCIL_BIT,
916 imageLayout, ISL_AUX_USAGE_NONE, &stencil);
917 } else {
918 memset(&stencil, 0, sizeof(stencil));
919 }
920
921 for (unsigned r = 0; r < rangeCount; r++) {
922 if (pRanges[r].aspectMask == 0)
923 continue;
924
925 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
926 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
927
928 unsigned base_layer = pRanges[r].baseArrayLayer;
929 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
930
931 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
932 const unsigned level = pRanges[r].baseMipLevel + i;
933 const unsigned level_width = anv_minify(image->extent.width, level);
934 const unsigned level_height = anv_minify(image->extent.height, level);
935
936 if (image->type == VK_IMAGE_TYPE_3D)
937 layer_count = anv_minify(image->extent.depth, level);
938
939 blorp_clear_depth_stencil(&batch, &depth, &stencil,
940 level, base_layer, layer_count,
941 0, 0, level_width, level_height,
942 clear_depth, pDepthStencil->depth,
943 clear_stencil ? 0xff : 0,
944 pDepthStencil->stencil);
945 }
946 }
947
948 blorp_batch_finish(&batch);
949 }
950
951 VkResult
952 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
953 uint32_t num_entries,
954 uint32_t *state_offset,
955 struct anv_state *bt_state)
956 {
957 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
958 state_offset);
959 if (bt_state->map == NULL) {
960 /* We ran out of space. Grab a new binding table block. */
961 VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
962 if (result != VK_SUCCESS)
963 return result;
964
965 /* Re-emit state base addresses so we get the new surface state base
966 * address before we start emitting binding tables etc.
967 */
968 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
969
970 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
971 state_offset);
972 assert(bt_state->map != NULL);
973 }
974
975 return VK_SUCCESS;
976 }
977
978 static VkResult
979 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
980 struct anv_state surface_state,
981 uint32_t *bt_offset)
982 {
983 uint32_t state_offset;
984 struct anv_state bt_state;
985
986 VkResult result =
987 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
988 &bt_state);
989 if (result != VK_SUCCESS)
990 return result;
991
992 uint32_t *bt_map = bt_state.map;
993 bt_map[0] = surface_state.offset + state_offset;
994
995 *bt_offset = bt_state.offset;
996 return VK_SUCCESS;
997 }
998
999 static void
1000 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
1001 struct blorp_batch *batch,
1002 const VkClearAttachment *attachment,
1003 uint32_t rectCount, const VkClearRect *pRects)
1004 {
1005 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1006 const uint32_t color_att = attachment->colorAttachment;
1007 const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
1008
1009 if (att_idx == VK_ATTACHMENT_UNUSED)
1010 return;
1011
1012 struct anv_render_pass_attachment *pass_att =
1013 &cmd_buffer->state.pass->attachments[att_idx];
1014 struct anv_attachment_state *att_state =
1015 &cmd_buffer->state.attachments[att_idx];
1016
1017 uint32_t binding_table;
1018 VkResult result =
1019 binding_table_for_surface_state(cmd_buffer, att_state->color.state,
1020 &binding_table);
1021 if (result != VK_SUCCESS)
1022 return;
1023
1024 union isl_color_value clear_color =
1025 vk_to_isl_color(attachment->clearValue.color);
1026
1027 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1028 if (subpass->view_mask) {
1029 uint32_t view_idx;
1030 for_each_bit(view_idx, subpass->view_mask) {
1031 for (uint32_t r = 0; r < rectCount; ++r) {
1032 const VkOffset2D offset = pRects[r].rect.offset;
1033 const VkExtent2D extent = pRects[r].rect.extent;
1034 blorp_clear_attachments(batch, binding_table,
1035 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
1036 view_idx, 1,
1037 offset.x, offset.y,
1038 offset.x + extent.width,
1039 offset.y + extent.height,
1040 true, clear_color, false, 0.0f, 0, 0);
1041 }
1042 }
1043 return;
1044 }
1045
1046 for (uint32_t r = 0; r < rectCount; ++r) {
1047 const VkOffset2D offset = pRects[r].rect.offset;
1048 const VkExtent2D extent = pRects[r].rect.extent;
1049 assert(pRects[r].layerCount != VK_REMAINING_ARRAY_LAYERS);
1050 blorp_clear_attachments(batch, binding_table,
1051 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
1052 pRects[r].baseArrayLayer,
1053 pRects[r].layerCount,
1054 offset.x, offset.y,
1055 offset.x + extent.width, offset.y + extent.height,
1056 true, clear_color, false, 0.0f, 0, 0);
1057 }
1058 }
1059
1060 static void
1061 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
1062 struct blorp_batch *batch,
1063 const VkClearAttachment *attachment,
1064 uint32_t rectCount, const VkClearRect *pRects)
1065 {
1066 static const union isl_color_value color_value = { .u32 = { 0, } };
1067 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1068 const uint32_t att_idx = subpass->depth_stencil_attachment->attachment;
1069
1070 if (att_idx == VK_ATTACHMENT_UNUSED)
1071 return;
1072
1073 struct anv_render_pass_attachment *pass_att =
1074 &cmd_buffer->state.pass->attachments[att_idx];
1075
1076 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
1077 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
1078
1079 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
1080 if (clear_depth) {
1081 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
1082 pass_att->format,
1083 VK_IMAGE_ASPECT_DEPTH_BIT,
1084 VK_IMAGE_TILING_OPTIMAL);
1085 }
1086
1087 uint32_t binding_table;
1088 VkResult result =
1089 binding_table_for_surface_state(cmd_buffer,
1090 cmd_buffer->state.null_surface_state,
1091 &binding_table);
1092 if (result != VK_SUCCESS)
1093 return;
1094
1095 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1096 if (subpass->view_mask) {
1097 uint32_t view_idx;
1098 for_each_bit(view_idx, subpass->view_mask) {
1099 for (uint32_t r = 0; r < rectCount; ++r) {
1100 const VkOffset2D offset = pRects[r].rect.offset;
1101 const VkExtent2D extent = pRects[r].rect.extent;
1102 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1103 blorp_clear_attachments(batch, binding_table,
1104 depth_format, pass_att->samples,
1105 view_idx, 1,
1106 offset.x, offset.y,
1107 offset.x + extent.width,
1108 offset.y + extent.height,
1109 false, color_value,
1110 clear_depth, value.depth,
1111 clear_stencil ? 0xff : 0, value.stencil);
1112 }
1113 }
1114 return;
1115 }
1116
1117 for (uint32_t r = 0; r < rectCount; ++r) {
1118 const VkOffset2D offset = pRects[r].rect.offset;
1119 const VkExtent2D extent = pRects[r].rect.extent;
1120 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1121 assert(pRects[r].layerCount != VK_REMAINING_ARRAY_LAYERS);
1122 blorp_clear_attachments(batch, binding_table,
1123 depth_format, pass_att->samples,
1124 pRects[r].baseArrayLayer,
1125 pRects[r].layerCount,
1126 offset.x, offset.y,
1127 offset.x + extent.width, offset.y + extent.height,
1128 false, color_value,
1129 clear_depth, value.depth,
1130 clear_stencil ? 0xff : 0, value.stencil);
1131 }
1132 }
1133
1134 void anv_CmdClearAttachments(
1135 VkCommandBuffer commandBuffer,
1136 uint32_t attachmentCount,
1137 const VkClearAttachment* pAttachments,
1138 uint32_t rectCount,
1139 const VkClearRect* pRects)
1140 {
1141 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1142
1143 /* Because this gets called within a render pass, we tell blorp not to
1144 * trash our depth and stencil buffers.
1145 */
1146 struct blorp_batch batch;
1147 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1148 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1149
1150 for (uint32_t a = 0; a < attachmentCount; ++a) {
1151 if (pAttachments[a].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1152 assert(pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
1153 clear_color_attachment(cmd_buffer, &batch,
1154 &pAttachments[a],
1155 rectCount, pRects);
1156 } else {
1157 clear_depth_stencil_attachment(cmd_buffer, &batch,
1158 &pAttachments[a],
1159 rectCount, pRects);
1160 }
1161 }
1162
1163 blorp_batch_finish(&batch);
1164 }
1165
1166 enum subpass_stage {
1167 SUBPASS_STAGE_LOAD,
1168 SUBPASS_STAGE_DRAW,
1169 SUBPASS_STAGE_RESOLVE,
1170 };
1171
1172 void
1173 anv_image_msaa_resolve(struct anv_cmd_buffer *cmd_buffer,
1174 const struct anv_image *src_image,
1175 enum isl_aux_usage src_aux_usage,
1176 uint32_t src_level, uint32_t src_base_layer,
1177 const struct anv_image *dst_image,
1178 enum isl_aux_usage dst_aux_usage,
1179 uint32_t dst_level, uint32_t dst_base_layer,
1180 VkImageAspectFlagBits aspect,
1181 uint32_t src_x, uint32_t src_y,
1182 uint32_t dst_x, uint32_t dst_y,
1183 uint32_t width, uint32_t height,
1184 uint32_t layer_count,
1185 enum blorp_filter filter)
1186 {
1187 struct blorp_batch batch;
1188 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1189
1190 assert(src_image->type == VK_IMAGE_TYPE_2D);
1191 assert(src_image->samples > 1);
1192 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1193 assert(dst_image->samples == 1);
1194 assert(src_image->n_planes == dst_image->n_planes);
1195 assert(!src_image->format->can_ycbcr);
1196 assert(!dst_image->format->can_ycbcr);
1197
1198 struct blorp_surf src_surf, dst_surf;
1199 get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, aspect,
1200 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1201 src_aux_usage, &src_surf);
1202 if (src_aux_usage == ISL_AUX_USAGE_MCS) {
1203 src_surf.clear_color_addr = anv_to_blorp_address(
1204 anv_image_get_clear_color_addr(cmd_buffer->device, src_image,
1205 VK_IMAGE_ASPECT_COLOR_BIT));
1206 }
1207 get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, aspect,
1208 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1209 dst_aux_usage, &dst_surf);
1210 anv_cmd_buffer_mark_image_written(cmd_buffer, dst_image,
1211 aspect, dst_aux_usage,
1212 dst_level, dst_base_layer, layer_count);
1213
1214 if (filter == BLORP_FILTER_NONE) {
1215 /* If no explicit filter is provided, then it's implied by the type of
1216 * the source image.
1217 */
1218 if ((src_surf.surf->usage & ISL_SURF_USAGE_DEPTH_BIT) ||
1219 (src_surf.surf->usage & ISL_SURF_USAGE_STENCIL_BIT) ||
1220 isl_format_has_int_channel(src_surf.surf->format)) {
1221 filter = BLORP_FILTER_SAMPLE_0;
1222 } else {
1223 filter = BLORP_FILTER_AVERAGE;
1224 }
1225 }
1226
1227 for (uint32_t l = 0; l < layer_count; l++) {
1228 blorp_blit(&batch,
1229 &src_surf, src_level, src_base_layer + l,
1230 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1231 &dst_surf, dst_level, dst_base_layer + l,
1232 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1233 src_x, src_y, src_x + width, src_y + height,
1234 dst_x, dst_y, dst_x + width, dst_y + height,
1235 filter, false, false);
1236 }
1237
1238 blorp_batch_finish(&batch);
1239 }
1240
1241 void anv_CmdResolveImage(
1242 VkCommandBuffer commandBuffer,
1243 VkImage srcImage,
1244 VkImageLayout srcImageLayout,
1245 VkImage dstImage,
1246 VkImageLayout dstImageLayout,
1247 uint32_t regionCount,
1248 const VkImageResolve* pRegions)
1249 {
1250 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1251 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1252 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1253
1254 assert(!src_image->format->can_ycbcr);
1255
1256 for (uint32_t r = 0; r < regionCount; r++) {
1257 assert(pRegions[r].srcSubresource.aspectMask ==
1258 pRegions[r].dstSubresource.aspectMask);
1259 assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
1260 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
1261
1262 const uint32_t layer_count =
1263 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
1264
1265 VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask;
1266 VkImageAspectFlags dst_mask = pRegions[r].dstSubresource.aspectMask;
1267
1268 assert(anv_image_aspects_compatible(src_mask, dst_mask));
1269
1270 uint32_t aspect_bit;
1271 anv_foreach_image_aspect_bit(aspect_bit, src_image,
1272 pRegions[r].srcSubresource.aspectMask) {
1273 enum isl_aux_usage src_aux_usage =
1274 anv_layout_to_aux_usage(&cmd_buffer->device->info, src_image,
1275 (1 << aspect_bit), srcImageLayout);
1276 enum isl_aux_usage dst_aux_usage =
1277 anv_layout_to_aux_usage(&cmd_buffer->device->info, dst_image,
1278 (1 << aspect_bit), dstImageLayout);
1279
1280 anv_image_msaa_resolve(cmd_buffer,
1281 src_image, src_aux_usage,
1282 pRegions[r].srcSubresource.mipLevel,
1283 pRegions[r].srcSubresource.baseArrayLayer,
1284 dst_image, dst_aux_usage,
1285 pRegions[r].dstSubresource.mipLevel,
1286 pRegions[r].dstSubresource.baseArrayLayer,
1287 (1 << aspect_bit),
1288 pRegions[r].srcOffset.x,
1289 pRegions[r].srcOffset.y,
1290 pRegions[r].dstOffset.x,
1291 pRegions[r].dstOffset.y,
1292 pRegions[r].extent.width,
1293 pRegions[r].extent.height,
1294 layer_count, BLORP_FILTER_NONE);
1295 }
1296 }
1297 }
1298
1299 static enum isl_aux_usage
1300 fast_clear_aux_usage(const struct anv_image *image,
1301 VkImageAspectFlagBits aspect)
1302 {
1303 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1304 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
1305 return ISL_AUX_USAGE_CCS_D;
1306 else
1307 return image->planes[plane].aux_usage;
1308 }
1309
1310 void
1311 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
1312 const struct anv_image *image,
1313 uint32_t base_level, uint32_t level_count,
1314 uint32_t base_layer, uint32_t layer_count)
1315 {
1316 struct blorp_batch batch;
1317 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1318
1319 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT && image->n_planes == 1);
1320
1321 struct blorp_surf surf;
1322 get_blorp_surf_for_anv_image(cmd_buffer->device,
1323 image, VK_IMAGE_ASPECT_COLOR_BIT,
1324 VK_IMAGE_LAYOUT_GENERAL,
1325 ISL_AUX_USAGE_NONE, &surf);
1326 assert(surf.aux_usage == ISL_AUX_USAGE_NONE);
1327
1328 struct blorp_surf shadow_surf = {
1329 .surf = &image->planes[0].shadow_surface.isl,
1330 .addr = {
1331 .buffer = image->planes[0].address.bo,
1332 .offset = image->planes[0].address.offset +
1333 image->planes[0].shadow_surface.offset,
1334 .mocs = anv_mocs_for_bo(cmd_buffer->device,
1335 image->planes[0].address.bo),
1336 },
1337 };
1338
1339 for (uint32_t l = 0; l < level_count; l++) {
1340 const uint32_t level = base_level + l;
1341
1342 const VkExtent3D extent = {
1343 .width = anv_minify(image->extent.width, level),
1344 .height = anv_minify(image->extent.height, level),
1345 .depth = anv_minify(image->extent.depth, level),
1346 };
1347
1348 if (image->type == VK_IMAGE_TYPE_3D)
1349 layer_count = extent.depth;
1350
1351 for (uint32_t a = 0; a < layer_count; a++) {
1352 const uint32_t layer = base_layer + a;
1353
1354 blorp_copy(&batch, &surf, level, layer,
1355 &shadow_surf, level, layer,
1356 0, 0, 0, 0, extent.width, extent.height);
1357 }
1358 }
1359
1360 blorp_batch_finish(&batch);
1361 }
1362
1363 void
1364 anv_image_clear_color(struct anv_cmd_buffer *cmd_buffer,
1365 const struct anv_image *image,
1366 VkImageAspectFlagBits aspect,
1367 enum isl_aux_usage aux_usage,
1368 enum isl_format format, struct isl_swizzle swizzle,
1369 uint32_t level, uint32_t base_layer, uint32_t layer_count,
1370 VkRect2D area, union isl_color_value clear_color)
1371 {
1372 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1373
1374 /* We don't support planar images with multisampling yet */
1375 assert(image->n_planes == 1);
1376
1377 struct blorp_batch batch;
1378 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1379
1380 struct blorp_surf surf;
1381 get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
1382 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1383 aux_usage, &surf);
1384 anv_cmd_buffer_mark_image_written(cmd_buffer, image, aspect, aux_usage,
1385 level, base_layer, layer_count);
1386
1387 blorp_clear(&batch, &surf, format, anv_swizzle_for_render(swizzle),
1388 level, base_layer, layer_count,
1389 area.offset.x, area.offset.y,
1390 area.offset.x + area.extent.width,
1391 area.offset.y + area.extent.height,
1392 clear_color, NULL);
1393
1394 blorp_batch_finish(&batch);
1395 }
1396
1397 void
1398 anv_image_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
1399 const struct anv_image *image,
1400 VkImageAspectFlags aspects,
1401 enum isl_aux_usage depth_aux_usage,
1402 uint32_t level,
1403 uint32_t base_layer, uint32_t layer_count,
1404 VkRect2D area,
1405 float depth_value, uint8_t stencil_value)
1406 {
1407 assert(image->aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1408 VK_IMAGE_ASPECT_STENCIL_BIT));
1409
1410 struct blorp_batch batch;
1411 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1412
1413 struct blorp_surf depth = {};
1414 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1415 get_blorp_surf_for_anv_image(cmd_buffer->device,
1416 image, VK_IMAGE_ASPECT_DEPTH_BIT,
1417 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1418 depth_aux_usage, &depth);
1419 depth.clear_color.f32[0] = ANV_HZ_FC_VAL;
1420 }
1421
1422 struct blorp_surf stencil = {};
1423 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1424 get_blorp_surf_for_anv_image(cmd_buffer->device,
1425 image, VK_IMAGE_ASPECT_STENCIL_BIT,
1426 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1427 ISL_AUX_USAGE_NONE, &stencil);
1428 }
1429
1430 blorp_clear_depth_stencil(&batch, &depth, &stencil,
1431 level, base_layer, layer_count,
1432 area.offset.x, area.offset.y,
1433 area.offset.x + area.extent.width,
1434 area.offset.y + area.extent.height,
1435 aspects & VK_IMAGE_ASPECT_DEPTH_BIT,
1436 depth_value,
1437 (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) ? 0xff : 0,
1438 stencil_value);
1439
1440 blorp_batch_finish(&batch);
1441 }
1442
1443 void
1444 anv_image_hiz_op(struct anv_cmd_buffer *cmd_buffer,
1445 const struct anv_image *image,
1446 VkImageAspectFlagBits aspect, uint32_t level,
1447 uint32_t base_layer, uint32_t layer_count,
1448 enum isl_aux_op hiz_op)
1449 {
1450 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
1451 assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level));
1452 assert(anv_image_aspect_to_plane(image->aspects,
1453 VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
1454
1455 struct blorp_batch batch;
1456 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1457
1458 struct blorp_surf surf;
1459 get_blorp_surf_for_anv_image(cmd_buffer->device,
1460 image, VK_IMAGE_ASPECT_DEPTH_BIT,
1461 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1462 ISL_AUX_USAGE_HIZ, &surf);
1463 surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
1464
1465 blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);
1466
1467 blorp_batch_finish(&batch);
1468 }
1469
1470 void
1471 anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
1472 const struct anv_image *image,
1473 VkImageAspectFlags aspects,
1474 uint32_t level,
1475 uint32_t base_layer, uint32_t layer_count,
1476 VkRect2D area, uint8_t stencil_value)
1477 {
1478 assert(image->aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
1479 VK_IMAGE_ASPECT_STENCIL_BIT));
1480
1481 struct blorp_batch batch;
1482 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1483
1484 struct blorp_surf depth = {};
1485 if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
1486 assert(base_layer + layer_count <=
1487 anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level));
1488 get_blorp_surf_for_anv_image(cmd_buffer->device,
1489 image, VK_IMAGE_ASPECT_DEPTH_BIT,
1490 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1491 ISL_AUX_USAGE_HIZ, &depth);
1492 depth.clear_color.f32[0] = ANV_HZ_FC_VAL;
1493 }
1494
1495 struct blorp_surf stencil = {};
1496 if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
1497 get_blorp_surf_for_anv_image(cmd_buffer->device,
1498 image, VK_IMAGE_ASPECT_STENCIL_BIT,
1499 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1500 ISL_AUX_USAGE_NONE, &stencil);
1501 }
1502
1503 /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
1504 *
1505 * "The following is required when performing a depth buffer clear with
1506 * using the WM_STATE or 3DSTATE_WM:
1507 *
1508 * * If other rendering operations have preceded this clear, a
1509 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1510 * enabled must be issued before the rectangle primitive used for
1511 * the depth buffer clear operation.
1512 * * [...]"
1513 *
1514 * Even though the PRM only says that this is required if using 3DSTATE_WM
1515 * and a 3DPRIMITIVE, the GPU appears to also need this to avoid occasional
1516 * hangs when doing a clear with WM_HZ_OP.
1517 */
1518 cmd_buffer->state.pending_pipe_bits |=
1519 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
1520
1521 blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil,
1522 level, base_layer, layer_count,
1523 area.offset.x, area.offset.y,
1524 area.offset.x + area.extent.width,
1525 area.offset.y + area.extent.height,
1526 aspects & VK_IMAGE_ASPECT_DEPTH_BIT,
1527 ANV_HZ_FC_VAL,
1528 aspects & VK_IMAGE_ASPECT_STENCIL_BIT,
1529 stencil_value);
1530
1531 blorp_batch_finish(&batch);
1532
1533 /* From the SKL PRM, Depth Buffer Clear:
1534 *
1535 * "Depth Buffer Clear Workaround
1536 *
1537 * Depth buffer clear pass using any of the methods (WM_STATE,
1538 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
1539 * command with DEPTH_STALL bit and Depth FLUSH bits “set” before
1540 * starting to render. DepthStall and DepthFlush are not needed between
1541 * consecutive depth clear passes nor is it required if the depth-clear
1542 * pass was done with “full_surf_clear” bit set in the
1543 * 3DSTATE_WM_HZ_OP."
1544 *
1545 * Even though the PRM provides a bunch of conditions under which this is
1546 * supposedly unnecessary, we choose to perform the flush unconditionally
1547 * just to be safe.
1548 */
1549 cmd_buffer->state.pending_pipe_bits |=
1550 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
1551 }
1552
1553 void
1554 anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
1555 const struct anv_image *image,
1556 enum isl_format format,
1557 VkImageAspectFlagBits aspect,
1558 uint32_t base_layer, uint32_t layer_count,
1559 enum isl_aux_op mcs_op, union isl_color_value *clear_value,
1560 bool predicate)
1561 {
1562 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1563 assert(image->samples > 1);
1564 assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, 0));
1565
1566 /* Multisampling with multi-planar formats is not supported */
1567 assert(image->n_planes == 1);
1568
1569 struct blorp_batch batch;
1570 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1571 predicate ? BLORP_BATCH_PREDICATE_ENABLE : 0);
1572
1573 struct blorp_surf surf;
1574 get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
1575 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1576 ISL_AUX_USAGE_MCS, &surf);
1577
1578 /* Blorp will store the clear color for us if we provide the clear color
1579 * address and we are doing a fast clear. So we save the clear value into
1580 * the blorp surface. However, in some situations we want to do a fast clear
1581 * without changing the clear value stored in the state buffer. For those
1582 * cases, we set the clear color address pointer to NULL, so blorp will not
1583 * try to store a garbage color.
1584 */
1585 if (mcs_op == ISL_AUX_OP_FAST_CLEAR) {
1586 if (clear_value)
1587 surf.clear_color = *clear_value;
1588 else
1589 surf.clear_color_addr.buffer = NULL;
1590 }
1591
1592 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1593 *
1594 * "After Render target fast clear, pipe-control with color cache
1595 * write-flush must be issued before sending any DRAW commands on
1596 * that render target."
1597 *
1598 * This comment is a bit cryptic and doesn't really tell you what's going
1599 * or what's really needed. It appears that fast clear ops are not
1600 * properly synchronized with other drawing. This means that we cannot
1601 * have a fast clear operation in the pipe at the same time as other
1602 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1603 * that the contents of the previous draw hit the render target before we
1604 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1605 * that it is completed before any additional drawing occurs.
1606 */
1607 cmd_buffer->state.pending_pipe_bits |=
1608 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1609
1610 switch (mcs_op) {
1611 case ISL_AUX_OP_FAST_CLEAR:
1612 blorp_fast_clear(&batch, &surf, format,
1613 0, base_layer, layer_count,
1614 0, 0, image->extent.width, image->extent.height);
1615 break;
1616 case ISL_AUX_OP_PARTIAL_RESOLVE:
1617 blorp_mcs_partial_resolve(&batch, &surf, format,
1618 base_layer, layer_count);
1619 break;
1620 case ISL_AUX_OP_FULL_RESOLVE:
1621 case ISL_AUX_OP_AMBIGUATE:
1622 default:
1623 unreachable("Unsupported MCS operation");
1624 }
1625
1626 cmd_buffer->state.pending_pipe_bits |=
1627 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1628
1629 blorp_batch_finish(&batch);
1630 }
1631
1632 void
1633 anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
1634 const struct anv_image *image,
1635 enum isl_format format,
1636 VkImageAspectFlagBits aspect, uint32_t level,
1637 uint32_t base_layer, uint32_t layer_count,
1638 enum isl_aux_op ccs_op, union isl_color_value *clear_value,
1639 bool predicate)
1640 {
1641 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1642 assert(image->samples == 1);
1643 assert(level < anv_image_aux_levels(image, aspect));
1644 /* Multi-LOD YcBcR is not allowed */
1645 assert(image->n_planes == 1 || level == 0);
1646 assert(base_layer + layer_count <=
1647 anv_image_aux_layers(image, aspect, level));
1648
1649 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1650 uint32_t width_div = image->format->planes[plane].denominator_scales[0];
1651 uint32_t height_div = image->format->planes[plane].denominator_scales[1];
1652 uint32_t level_width = anv_minify(image->extent.width, level) / width_div;
1653 uint32_t level_height = anv_minify(image->extent.height, level) / height_div;
1654
1655 struct blorp_batch batch;
1656 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1657 predicate ? BLORP_BATCH_PREDICATE_ENABLE : 0);
1658
1659 struct blorp_surf surf;
1660 get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
1661 ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
1662 fast_clear_aux_usage(image, aspect),
1663 &surf);
1664
1665 /* Blorp will store the clear color for us if we provide the clear color
1666 * address and we are doing a fast clear. So we save the clear value into
1667 * the blorp surface. However, in some situations we want to do a fast clear
1668 * without changing the clear value stored in the state buffer. For those
1669 * cases, we set the clear color address pointer to NULL, so blorp will not
1670 * try to store a garbage color.
1671 */
1672 if (ccs_op == ISL_AUX_OP_FAST_CLEAR) {
1673 if (clear_value)
1674 surf.clear_color = *clear_value;
1675 else
1676 surf.clear_color_addr.buffer = NULL;
1677 }
1678
1679 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1680 *
1681 * "After Render target fast clear, pipe-control with color cache
1682 * write-flush must be issued before sending any DRAW commands on
1683 * that render target."
1684 *
1685 * This comment is a bit cryptic and doesn't really tell you what's going
1686 * or what's really needed. It appears that fast clear ops are not
1687 * properly synchronized with other drawing. This means that we cannot
1688 * have a fast clear operation in the pipe at the same time as other
1689 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1690 * that the contents of the previous draw hit the render target before we
1691 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1692 * that it is completed before any additional drawing occurs.
1693 */
1694 cmd_buffer->state.pending_pipe_bits |=
1695 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1696
1697 switch (ccs_op) {
1698 case ISL_AUX_OP_FAST_CLEAR:
1699 blorp_fast_clear(&batch, &surf, format,
1700 level, base_layer, layer_count,
1701 0, 0, level_width, level_height);
1702 break;
1703 case ISL_AUX_OP_FULL_RESOLVE:
1704 case ISL_AUX_OP_PARTIAL_RESOLVE:
1705 blorp_ccs_resolve(&batch, &surf, level, base_layer, layer_count,
1706 format, ccs_op);
1707 break;
1708 case ISL_AUX_OP_AMBIGUATE:
1709 for (uint32_t a = 0; a < layer_count; a++) {
1710 const uint32_t layer = base_layer + a;
1711 blorp_ccs_ambiguate(&batch, &surf, level, layer);
1712 }
1713 break;
1714 default:
1715 unreachable("Unsupported CCS operation");
1716 }
1717
1718 cmd_buffer->state.pending_pipe_bits |=
1719 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1720
1721 blorp_batch_finish(&batch);
1722 }