2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
27 lookup_blorp_shader(struct blorp_context
*blorp
,
28 const void *key
, uint32_t key_size
,
29 uint32_t *kernel_out
, void *prog_data_out
)
31 struct anv_device
*device
= blorp
->driver_ctx
;
33 /* The blorp cache must be a real cache */
34 assert(device
->blorp_shader_cache
.cache
);
36 struct anv_shader_bin
*bin
=
37 anv_pipeline_cache_search(&device
->blorp_shader_cache
, key
, key_size
);
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
44 anv_shader_bin_unref(device
, bin
);
46 *kernel_out
= bin
->kernel
.offset
;
47 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
53 upload_blorp_shader(struct blorp_context
*blorp
,
54 const void *key
, uint32_t key_size
,
55 const void *kernel
, uint32_t kernel_size
,
56 const struct brw_stage_prog_data
*prog_data
,
57 uint32_t prog_data_size
,
58 uint32_t *kernel_out
, void *prog_data_out
)
60 struct anv_device
*device
= blorp
->driver_ctx
;
62 /* The blorp cache must be a real cache */
63 assert(device
->blorp_shader_cache
.cache
);
65 struct anv_pipeline_bind_map bind_map
= {
70 struct anv_shader_bin
*bin
=
71 anv_pipeline_cache_upload_kernel(&device
->blorp_shader_cache
,
72 key
, key_size
, kernel
, kernel_size
,
73 prog_data
, prog_data_size
, &bind_map
);
75 /* The cache already has a reference and it's not going anywhere so there
76 * is no need to hold a second reference.
78 anv_shader_bin_unref(device
, bin
);
80 *kernel_out
= bin
->kernel
.offset
;
81 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
85 anv_device_init_blorp(struct anv_device
*device
)
87 anv_pipeline_cache_init(&device
->blorp_shader_cache
, device
, true);
88 blorp_init(&device
->blorp
, device
, &device
->isl_dev
);
89 device
->blorp
.compiler
= device
->instance
->physicalDevice
.compiler
;
90 device
->blorp
.mocs
.tex
= device
->default_mocs
;
91 device
->blorp
.mocs
.rb
= device
->default_mocs
;
92 device
->blorp
.mocs
.vb
= device
->default_mocs
;
93 device
->blorp
.lookup_shader
= lookup_blorp_shader
;
94 device
->blorp
.upload_shader
= upload_blorp_shader
;
95 switch (device
->info
.gen
) {
97 if (device
->info
.is_haswell
) {
98 device
->blorp
.exec
= gen75_blorp_exec
;
100 device
->blorp
.exec
= gen7_blorp_exec
;
104 device
->blorp
.exec
= gen8_blorp_exec
;
107 device
->blorp
.exec
= gen9_blorp_exec
;
110 unreachable("Unknown hardware generation");
115 anv_device_finish_blorp(struct anv_device
*device
)
117 blorp_finish(&device
->blorp
);
118 anv_pipeline_cache_finish(&device
->blorp_shader_cache
);
122 get_blorp_surf_for_anv_buffer(struct anv_device
*device
,
123 struct anv_buffer
*buffer
, uint64_t offset
,
124 uint32_t width
, uint32_t height
,
125 uint32_t row_pitch
, enum isl_format format
,
126 struct blorp_surf
*blorp_surf
,
127 struct isl_surf
*isl_surf
)
129 const struct isl_format_layout
*fmtl
=
130 isl_format_get_layout(format
);
132 /* ASTC is the only format which doesn't support linear layouts.
133 * Create an equivalently sized surface with ISL to get around this.
135 if (fmtl
->txc
== ISL_TXC_ASTC
) {
136 /* Use an equivalently sized format */
137 format
= ISL_FORMAT_R32G32B32A32_UINT
;
138 assert(fmtl
->bpb
== isl_format_get_layout(format
)->bpb
);
140 /* Shrink the dimensions for the new format */
141 width
= DIV_ROUND_UP(width
, fmtl
->bw
);
142 height
= DIV_ROUND_UP(height
, fmtl
->bh
);
145 *blorp_surf
= (struct blorp_surf
) {
148 .buffer
= buffer
->bo
,
149 .offset
= buffer
->offset
+ offset
,
153 isl_surf_init(&device
->isl_dev
, isl_surf
,
154 .dim
= ISL_SURF_DIM_2D
,
162 .min_pitch
= row_pitch
,
163 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
164 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
165 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
166 assert(isl_surf
->row_pitch
== row_pitch
);
170 get_blorp_surf_for_anv_image(const struct anv_image
*image
,
171 VkImageAspectFlags aspect
,
172 enum isl_aux_usage aux_usage
,
173 struct blorp_surf
*blorp_surf
)
175 if (aspect
== VK_IMAGE_ASPECT_STENCIL_BIT
||
176 aux_usage
== ISL_AUX_USAGE_HIZ
)
177 aux_usage
= ISL_AUX_USAGE_NONE
;
179 const struct anv_surface
*surface
=
180 anv_image_get_surface_for_aspect_mask(image
, aspect
);
182 *blorp_surf
= (struct blorp_surf
) {
183 .surf
= &surface
->isl
,
186 .offset
= image
->offset
+ surface
->offset
,
190 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
191 blorp_surf
->aux_surf
= &image
->aux_surface
.isl
,
192 blorp_surf
->aux_addr
= (struct blorp_address
) {
194 .offset
= image
->offset
+ image
->aux_surface
.offset
,
196 blorp_surf
->aux_usage
= aux_usage
;
200 void anv_CmdCopyImage(
201 VkCommandBuffer commandBuffer
,
203 VkImageLayout srcImageLayout
,
205 VkImageLayout dstImageLayout
,
206 uint32_t regionCount
,
207 const VkImageCopy
* pRegions
)
209 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
210 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
211 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
213 struct blorp_batch batch
;
214 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
216 for (unsigned r
= 0; r
< regionCount
; r
++) {
217 VkOffset3D srcOffset
=
218 anv_sanitize_image_offset(src_image
->type
, pRegions
[r
].srcOffset
);
219 VkOffset3D dstOffset
=
220 anv_sanitize_image_offset(dst_image
->type
, pRegions
[r
].dstOffset
);
222 anv_sanitize_image_extent(src_image
->type
, pRegions
[r
].extent
);
224 unsigned dst_base_layer
, layer_count
;
225 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
226 dst_base_layer
= pRegions
[r
].dstOffset
.z
;
227 layer_count
= pRegions
[r
].extent
.depth
;
229 dst_base_layer
= pRegions
[r
].dstSubresource
.baseArrayLayer
;
230 layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
233 unsigned src_base_layer
;
234 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
235 src_base_layer
= pRegions
[r
].srcOffset
.z
;
237 src_base_layer
= pRegions
[r
].srcSubresource
.baseArrayLayer
;
238 assert(pRegions
[r
].srcSubresource
.layerCount
== layer_count
);
241 assert(pRegions
[r
].srcSubresource
.aspectMask
==
242 pRegions
[r
].dstSubresource
.aspectMask
);
245 for_each_bit(a
, pRegions
[r
].dstSubresource
.aspectMask
) {
246 VkImageAspectFlagBits aspect
= (1 << a
);
248 struct blorp_surf src_surf
, dst_surf
;
249 get_blorp_surf_for_anv_image(src_image
, aspect
, src_image
->aux_usage
,
251 get_blorp_surf_for_anv_image(dst_image
, aspect
, dst_image
->aux_usage
,
254 for (unsigned i
= 0; i
< layer_count
; i
++) {
255 blorp_copy(&batch
, &src_surf
, pRegions
[r
].srcSubresource
.mipLevel
,
257 &dst_surf
, pRegions
[r
].dstSubresource
.mipLevel
,
259 srcOffset
.x
, srcOffset
.y
,
260 dstOffset
.x
, dstOffset
.y
,
261 extent
.width
, extent
.height
);
266 blorp_batch_finish(&batch
);
270 copy_buffer_to_image(struct anv_cmd_buffer
*cmd_buffer
,
271 struct anv_buffer
*anv_buffer
,
272 struct anv_image
*anv_image
,
273 uint32_t regionCount
,
274 const VkBufferImageCopy
* pRegions
,
275 bool buffer_to_image
)
277 struct blorp_batch batch
;
278 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
281 struct blorp_surf surf
;
284 } image
, buffer
, *src
, *dst
;
287 buffer
.offset
= (VkOffset3D
) { 0, 0, 0 };
289 if (buffer_to_image
) {
297 for (unsigned r
= 0; r
< regionCount
; r
++) {
298 const VkImageAspectFlags aspect
= pRegions
[r
].imageSubresource
.aspectMask
;
300 get_blorp_surf_for_anv_image(anv_image
, aspect
, anv_image
->aux_usage
,
303 anv_sanitize_image_offset(anv_image
->type
, pRegions
[r
].imageOffset
);
304 image
.level
= pRegions
[r
].imageSubresource
.mipLevel
;
307 anv_sanitize_image_extent(anv_image
->type
, pRegions
[r
].imageExtent
);
308 if (anv_image
->type
!= VK_IMAGE_TYPE_3D
) {
309 image
.offset
.z
= pRegions
[r
].imageSubresource
.baseArrayLayer
;
310 extent
.depth
= pRegions
[r
].imageSubresource
.layerCount
;
313 const enum isl_format buffer_format
=
314 anv_get_isl_format(&cmd_buffer
->device
->info
, anv_image
->vk_format
,
315 aspect
, VK_IMAGE_TILING_LINEAR
);
317 const VkExtent3D bufferImageExtent
= {
318 .width
= pRegions
[r
].bufferRowLength
?
319 pRegions
[r
].bufferRowLength
: extent
.width
,
320 .height
= pRegions
[r
].bufferImageHeight
?
321 pRegions
[r
].bufferImageHeight
: extent
.height
,
324 const struct isl_format_layout
*buffer_fmtl
=
325 isl_format_get_layout(buffer_format
);
327 const uint32_t buffer_row_pitch
=
328 DIV_ROUND_UP(bufferImageExtent
.width
, buffer_fmtl
->bw
) *
329 (buffer_fmtl
->bpb
/ 8);
331 const uint32_t buffer_layer_stride
=
332 DIV_ROUND_UP(bufferImageExtent
.height
, buffer_fmtl
->bh
) *
335 struct isl_surf buffer_isl_surf
;
336 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
337 anv_buffer
, pRegions
[r
].bufferOffset
,
338 extent
.width
, extent
.height
,
339 buffer_row_pitch
, buffer_format
,
340 &buffer
.surf
, &buffer_isl_surf
);
342 for (unsigned z
= 0; z
< extent
.depth
; z
++) {
343 blorp_copy(&batch
, &src
->surf
, src
->level
, src
->offset
.z
,
344 &dst
->surf
, dst
->level
, dst
->offset
.z
,
345 src
->offset
.x
, src
->offset
.y
, dst
->offset
.x
, dst
->offset
.y
,
346 extent
.width
, extent
.height
);
349 buffer
.surf
.addr
.offset
+= buffer_layer_stride
;
353 blorp_batch_finish(&batch
);
356 void anv_CmdCopyBufferToImage(
357 VkCommandBuffer commandBuffer
,
360 VkImageLayout dstImageLayout
,
361 uint32_t regionCount
,
362 const VkBufferImageCopy
* pRegions
)
364 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
365 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
366 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
368 copy_buffer_to_image(cmd_buffer
, src_buffer
, dst_image
,
369 regionCount
, pRegions
, true);
372 void anv_CmdCopyImageToBuffer(
373 VkCommandBuffer commandBuffer
,
375 VkImageLayout srcImageLayout
,
377 uint32_t regionCount
,
378 const VkBufferImageCopy
* pRegions
)
380 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
381 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
382 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
384 copy_buffer_to_image(cmd_buffer
, dst_buffer
, src_image
,
385 regionCount
, pRegions
, false);
389 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
393 unsigned tmp
= *src0
;
400 unsigned tmp
= *dst0
;
409 void anv_CmdBlitImage(
410 VkCommandBuffer commandBuffer
,
412 VkImageLayout srcImageLayout
,
414 VkImageLayout dstImageLayout
,
415 uint32_t regionCount
,
416 const VkImageBlit
* pRegions
,
420 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
421 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
422 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
424 struct blorp_surf src
, dst
;
428 case VK_FILTER_NEAREST
:
429 gl_filter
= 0x2600; /* GL_NEAREST */
431 case VK_FILTER_LINEAR
:
432 gl_filter
= 0x2601; /* GL_LINEAR */
435 unreachable("Invalid filter");
438 struct blorp_batch batch
;
439 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
441 for (unsigned r
= 0; r
< regionCount
; r
++) {
442 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
443 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
445 get_blorp_surf_for_anv_image(src_image
, src_res
->aspectMask
,
446 src_image
->aux_usage
, &src
);
447 get_blorp_surf_for_anv_image(dst_image
, dst_res
->aspectMask
,
448 dst_image
->aux_usage
, &dst
);
450 struct anv_format src_format
=
451 anv_get_format(&cmd_buffer
->device
->info
, src_image
->vk_format
,
452 src_res
->aspectMask
, src_image
->tiling
);
453 struct anv_format dst_format
=
454 anv_get_format(&cmd_buffer
->device
->info
, dst_image
->vk_format
,
455 dst_res
->aspectMask
, dst_image
->tiling
);
457 unsigned dst_start
, dst_end
;
458 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
459 assert(dst_res
->baseArrayLayer
== 0);
460 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
461 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
463 dst_start
= dst_res
->baseArrayLayer
;
464 dst_end
= dst_start
+ dst_res
->layerCount
;
467 unsigned src_start
, src_end
;
468 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
469 assert(src_res
->baseArrayLayer
== 0);
470 src_start
= pRegions
[r
].srcOffsets
[0].z
;
471 src_end
= pRegions
[r
].srcOffsets
[1].z
;
473 src_start
= src_res
->baseArrayLayer
;
474 src_end
= src_start
+ src_res
->layerCount
;
477 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
478 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
479 (float)(dst_end
+ 1 - dst_start
);
486 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
487 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
488 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
489 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
490 bool flip_x
= flip_coords(&src_x0
, &src_x1
, &dst_x0
, &dst_x1
);
492 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
493 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
494 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
495 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
496 bool flip_y
= flip_coords(&src_y0
, &src_y1
, &dst_y0
, &dst_y1
);
498 const unsigned num_layers
= dst_end
- dst_start
;
499 for (unsigned i
= 0; i
< num_layers
; i
++) {
500 unsigned dst_z
= dst_start
+ i
;
501 unsigned src_z
= src_start
+ i
* src_z_step
;
503 blorp_blit(&batch
, &src
, src_res
->mipLevel
, src_z
,
504 src_format
.isl_format
, src_format
.swizzle
,
505 &dst
, dst_res
->mipLevel
, dst_z
,
506 dst_format
.isl_format
,
507 anv_swizzle_for_render(dst_format
.swizzle
),
508 src_x0
, src_y0
, src_x1
, src_y1
,
509 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
510 gl_filter
, flip_x
, flip_y
);
515 blorp_batch_finish(&batch
);
518 static enum isl_format
519 isl_format_for_size(unsigned size_B
)
522 case 1: return ISL_FORMAT_R8_UINT
;
523 case 2: return ISL_FORMAT_R8G8_UINT
;
524 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
525 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
526 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
528 unreachable("Not a power-of-two format size");
533 do_buffer_copy(struct blorp_batch
*batch
,
534 struct anv_bo
*src
, uint64_t src_offset
,
535 struct anv_bo
*dst
, uint64_t dst_offset
,
536 int width
, int height
, int block_size
)
538 struct anv_device
*device
= batch
->blorp
->driver_ctx
;
540 /* The actual format we pick doesn't matter as blorp will throw it away.
541 * The only thing that actually matters is the size.
543 enum isl_format format
= isl_format_for_size(block_size
);
545 struct isl_surf surf
;
546 isl_surf_init(&device
->isl_dev
, &surf
,
547 .dim
= ISL_SURF_DIM_2D
,
555 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
556 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
557 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
558 assert(surf
.row_pitch
== width
* block_size
);
560 struct blorp_surf src_blorp_surf
= {
564 .offset
= src_offset
,
568 struct blorp_surf dst_blorp_surf
= {
572 .offset
= dst_offset
,
576 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
577 0, 0, 0, 0, width
, height
);
581 * Returns the greatest common divisor of a and b that is a power of two.
583 static inline uint64_t
584 gcd_pow2_u64(uint64_t a
, uint64_t b
)
586 assert(a
> 0 || b
> 0);
588 unsigned a_log2
= ffsll(a
) - 1;
589 unsigned b_log2
= ffsll(b
) - 1;
591 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
592 * case, the MIN2() will take the other one. If both are 0 then we will
593 * hit the assert above.
595 return 1 << MIN2(a_log2
, b_log2
);
598 /* This is maximum possible width/height our HW can handle */
599 #define MAX_SURFACE_DIM (1ull << 14)
601 void anv_CmdCopyBuffer(
602 VkCommandBuffer commandBuffer
,
605 uint32_t regionCount
,
606 const VkBufferCopy
* pRegions
)
608 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
609 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
610 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
612 struct blorp_batch batch
;
613 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
615 for (unsigned r
= 0; r
< regionCount
; r
++) {
616 uint64_t src_offset
= src_buffer
->offset
+ pRegions
[r
].srcOffset
;
617 uint64_t dst_offset
= dst_buffer
->offset
+ pRegions
[r
].dstOffset
;
618 uint64_t copy_size
= pRegions
[r
].size
;
620 /* First, we compute the biggest format that can be used with the
621 * given offsets and size.
624 bs
= gcd_pow2_u64(bs
, src_offset
);
625 bs
= gcd_pow2_u64(bs
, dst_offset
);
626 bs
= gcd_pow2_u64(bs
, pRegions
[r
].size
);
628 /* First, we make a bunch of max-sized copies */
629 uint64_t max_copy_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
630 while (copy_size
>= max_copy_size
) {
631 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
632 dst_buffer
->bo
, dst_offset
,
633 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
, bs
);
634 copy_size
-= max_copy_size
;
635 src_offset
+= max_copy_size
;
636 dst_offset
+= max_copy_size
;
639 /* Now make a max-width copy */
640 uint64_t height
= copy_size
/ (MAX_SURFACE_DIM
* bs
);
641 assert(height
< MAX_SURFACE_DIM
);
643 uint64_t rect_copy_size
= height
* MAX_SURFACE_DIM
* bs
;
644 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
645 dst_buffer
->bo
, dst_offset
,
646 MAX_SURFACE_DIM
, height
, bs
);
647 copy_size
-= rect_copy_size
;
648 src_offset
+= rect_copy_size
;
649 dst_offset
+= rect_copy_size
;
652 /* Finally, make a small copy to finish it off */
653 if (copy_size
!= 0) {
654 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
655 dst_buffer
->bo
, dst_offset
,
656 copy_size
/ bs
, 1, bs
);
660 blorp_batch_finish(&batch
);
663 void anv_CmdUpdateBuffer(
664 VkCommandBuffer commandBuffer
,
666 VkDeviceSize dstOffset
,
667 VkDeviceSize dataSize
,
670 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
671 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
673 struct blorp_batch batch
;
674 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
676 /* We can't quite grab a full block because the state stream needs a
677 * little data at the top to build its linked list.
679 const uint32_t max_update_size
=
680 cmd_buffer
->device
->dynamic_state_block_pool
.block_size
- 64;
682 assert(max_update_size
< MAX_SURFACE_DIM
* 4);
685 const uint32_t copy_size
= MIN2(dataSize
, max_update_size
);
687 struct anv_state tmp_data
=
688 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, copy_size
, 64);
690 memcpy(tmp_data
.map
, pData
, copy_size
);
693 bs
= gcd_pow2_u64(bs
, dstOffset
);
694 bs
= gcd_pow2_u64(bs
, copy_size
);
696 do_buffer_copy(&batch
,
697 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
699 dst_buffer
->bo
, dst_buffer
->offset
+ dstOffset
,
700 copy_size
/ bs
, 1, bs
);
702 dataSize
-= copy_size
;
703 dstOffset
+= copy_size
;
704 pData
= (void *)pData
+ copy_size
;
707 blorp_batch_finish(&batch
);
710 void anv_CmdFillBuffer(
711 VkCommandBuffer commandBuffer
,
713 VkDeviceSize dstOffset
,
714 VkDeviceSize fillSize
,
717 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
718 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
719 struct blorp_surf surf
;
720 struct isl_surf isl_surf
;
722 struct blorp_batch batch
;
723 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
725 fillSize
= anv_buffer_get_range(dst_buffer
, dstOffset
, fillSize
);
727 /* From the Vulkan spec:
729 * "size is the number of bytes to fill, and must be either a multiple
730 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
731 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
732 * buffer is not a multiple of 4, then the nearest smaller multiple is
737 /* First, we compute the biggest format that can be used with the
738 * given offsets and size.
741 bs
= gcd_pow2_u64(bs
, dstOffset
);
742 bs
= gcd_pow2_u64(bs
, fillSize
);
743 enum isl_format isl_format
= isl_format_for_size(bs
);
745 union isl_color_value color
= {
746 .u32
= { data
, data
, data
, data
},
749 const uint64_t max_fill_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
750 while (fillSize
>= max_fill_size
) {
751 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
752 dst_buffer
, dstOffset
,
753 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
754 MAX_SURFACE_DIM
* bs
, isl_format
,
757 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
758 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
760 fillSize
-= max_fill_size
;
761 dstOffset
+= max_fill_size
;
764 uint64_t height
= fillSize
/ (MAX_SURFACE_DIM
* bs
);
765 assert(height
< MAX_SURFACE_DIM
);
767 const uint64_t rect_fill_size
= height
* MAX_SURFACE_DIM
* bs
;
768 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
769 dst_buffer
, dstOffset
,
770 MAX_SURFACE_DIM
, height
,
771 MAX_SURFACE_DIM
* bs
, isl_format
,
774 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
775 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, height
,
777 fillSize
-= rect_fill_size
;
778 dstOffset
+= rect_fill_size
;
782 const uint32_t width
= fillSize
/ bs
;
783 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
784 dst_buffer
, dstOffset
,
786 width
* bs
, isl_format
,
789 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
790 0, 0, 1, 0, 0, width
, 1,
794 blorp_batch_finish(&batch
);
797 void anv_CmdClearColorImage(
798 VkCommandBuffer commandBuffer
,
800 VkImageLayout imageLayout
,
801 const VkClearColorValue
* pColor
,
803 const VkImageSubresourceRange
* pRanges
)
805 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
806 ANV_FROM_HANDLE(anv_image
, image
, _image
);
808 static const bool color_write_disable
[4] = { false, false, false, false };
810 struct blorp_batch batch
;
811 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
813 struct blorp_surf surf
;
814 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
815 image
->aux_usage
, &surf
);
817 for (unsigned r
= 0; r
< rangeCount
; r
++) {
818 if (pRanges
[r
].aspectMask
== 0)
821 assert(pRanges
[r
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
823 struct anv_format src_format
=
824 anv_get_format(&cmd_buffer
->device
->info
, image
->vk_format
,
825 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
827 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
828 unsigned layer_count
= pRanges
[r
].layerCount
;
830 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
831 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
832 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
833 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
835 if (image
->type
== VK_IMAGE_TYPE_3D
) {
837 layer_count
= anv_minify(image
->extent
.depth
, level
);
840 blorp_clear(&batch
, &surf
,
841 src_format
.isl_format
, src_format
.swizzle
,
842 level
, base_layer
, layer_count
,
843 0, 0, level_width
, level_height
,
844 vk_to_isl_color(*pColor
), color_write_disable
);
848 blorp_batch_finish(&batch
);
851 void anv_CmdClearDepthStencilImage(
852 VkCommandBuffer commandBuffer
,
854 VkImageLayout imageLayout
,
855 const VkClearDepthStencilValue
* pDepthStencil
,
857 const VkImageSubresourceRange
* pRanges
)
859 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
860 ANV_FROM_HANDLE(anv_image
, image
, image_h
);
862 struct blorp_batch batch
;
863 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
865 struct blorp_surf depth
, stencil
;
866 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
867 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
868 ISL_AUX_USAGE_NONE
, &depth
);
870 memset(&depth
, 0, sizeof(depth
));
873 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
874 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
875 ISL_AUX_USAGE_NONE
, &stencil
);
877 memset(&stencil
, 0, sizeof(stencil
));
880 for (unsigned r
= 0; r
< rangeCount
; r
++) {
881 if (pRanges
[r
].aspectMask
== 0)
884 bool clear_depth
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
885 bool clear_stencil
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
887 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
888 unsigned layer_count
= pRanges
[r
].layerCount
;
890 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
891 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
892 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
893 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
895 if (image
->type
== VK_IMAGE_TYPE_3D
)
896 layer_count
= anv_minify(image
->extent
.depth
, level
);
898 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
899 level
, base_layer
, layer_count
,
900 0, 0, level_width
, level_height
,
901 clear_depth
, pDepthStencil
->depth
,
902 clear_stencil
? 0xff : 0,
903 pDepthStencil
->stencil
);
907 blorp_batch_finish(&batch
);
911 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
912 uint32_t num_entries
,
913 uint32_t *state_offset
)
915 struct anv_state bt_state
=
916 anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
918 if (bt_state
.map
== NULL
) {
919 /* We ran out of space. Grab a new binding table block. */
920 MAYBE_UNUSED VkResult result
=
921 anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
922 assert(result
== VK_SUCCESS
);
924 /* Re-emit state base addresses so we get the new surface state base
925 * address before we start emitting binding tables etc.
927 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
929 bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
931 assert(bt_state
.map
!= NULL
);
938 binding_table_for_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
939 struct anv_state surface_state
)
941 uint32_t state_offset
;
942 struct anv_state bt_state
=
943 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, 1, &state_offset
);
945 uint32_t *bt_map
= bt_state
.map
;
946 bt_map
[0] = surface_state
.offset
+ state_offset
;
948 return bt_state
.offset
;
952 clear_color_attachment(struct anv_cmd_buffer
*cmd_buffer
,
953 struct blorp_batch
*batch
,
954 const VkClearAttachment
*attachment
,
955 uint32_t rectCount
, const VkClearRect
*pRects
)
957 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
958 const uint32_t color_att
= attachment
->colorAttachment
;
959 const uint32_t att_idx
= subpass
->color_attachments
[color_att
].attachment
;
961 if (att_idx
== VK_ATTACHMENT_UNUSED
)
964 struct anv_render_pass_attachment
*pass_att
=
965 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
966 struct anv_attachment_state
*att_state
=
967 &cmd_buffer
->state
.attachments
[att_idx
];
969 uint32_t binding_table
=
970 binding_table_for_surface_state(cmd_buffer
, att_state
->color_rt_state
);
972 union isl_color_value clear_color
=
973 vk_to_isl_color(attachment
->clearValue
.color
);
975 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
976 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
977 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
978 blorp_clear_attachments(batch
, binding_table
,
979 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
980 pRects
[r
].baseArrayLayer
,
981 pRects
[r
].layerCount
,
983 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
984 true, clear_color
, false, 0.0f
, 0, 0);
989 clear_depth_stencil_attachment(struct anv_cmd_buffer
*cmd_buffer
,
990 struct blorp_batch
*batch
,
991 const VkClearAttachment
*attachment
,
992 uint32_t rectCount
, const VkClearRect
*pRects
)
994 static const union isl_color_value color_value
= { .u32
= { 0, } };
995 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
996 const uint32_t att_idx
= subpass
->depth_stencil_attachment
.attachment
;
998 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1001 struct anv_render_pass_attachment
*pass_att
=
1002 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
1004 bool clear_depth
= attachment
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
1005 bool clear_stencil
= attachment
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
1007 enum isl_format depth_format
= ISL_FORMAT_UNSUPPORTED
;
1009 depth_format
= anv_get_isl_format(&cmd_buffer
->device
->info
,
1011 VK_IMAGE_ASPECT_DEPTH_BIT
,
1012 VK_IMAGE_TILING_OPTIMAL
);
1015 uint32_t binding_table
=
1016 binding_table_for_surface_state(cmd_buffer
,
1017 cmd_buffer
->state
.null_surface_state
);
1019 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1020 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1021 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1022 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1023 blorp_clear_attachments(batch
, binding_table
,
1024 depth_format
, pass_att
->samples
,
1025 pRects
[r
].baseArrayLayer
,
1026 pRects
[r
].layerCount
,
1028 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1030 clear_depth
, value
.depth
,
1031 clear_stencil
? 0xff : 0, value
.stencil
);
1035 void anv_CmdClearAttachments(
1036 VkCommandBuffer commandBuffer
,
1037 uint32_t attachmentCount
,
1038 const VkClearAttachment
* pAttachments
,
1040 const VkClearRect
* pRects
)
1042 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1044 /* Because this gets called within a render pass, we tell blorp not to
1045 * trash our depth and stencil buffers.
1047 struct blorp_batch batch
;
1048 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1049 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1051 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1052 if (pAttachments
[a
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1053 clear_color_attachment(cmd_buffer
, &batch
,
1057 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1063 blorp_batch_finish(&batch
);
1066 enum subpass_stage
{
1069 SUBPASS_STAGE_RESOLVE
,
1073 attachment_needs_flush(struct anv_cmd_buffer
*cmd_buffer
,
1074 struct anv_render_pass_attachment
*att
,
1075 enum subpass_stage stage
)
1077 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1078 const uint32_t subpass_idx
= anv_get_subpass_id(&cmd_buffer
->state
);
1080 /* We handle this subpass specially based on the current stage */
1081 enum anv_subpass_usage usage
= att
->subpass_usage
[subpass_idx
];
1083 case SUBPASS_STAGE_LOAD
:
1084 if (usage
& (ANV_SUBPASS_USAGE_INPUT
| ANV_SUBPASS_USAGE_RESOLVE_SRC
))
1088 case SUBPASS_STAGE_DRAW
:
1089 if (usage
& ANV_SUBPASS_USAGE_RESOLVE_SRC
)
1097 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1098 usage
= att
->subpass_usage
[s
];
1100 /* If this attachment is going to be used as an input in this or any
1101 * future subpass, then we need to flush its cache and invalidate the
1104 if (att
->subpass_usage
[s
] & ANV_SUBPASS_USAGE_INPUT
)
1107 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1108 /* We found another subpass that draws to this attachment. We'll
1109 * wait to resolve until then.
1119 anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1120 enum subpass_stage stage
)
1122 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1123 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1125 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1126 uint32_t att
= subpass
->color_attachments
[i
].attachment
;
1127 assert(att
< pass
->attachment_count
);
1128 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1129 cmd_buffer
->state
.pending_pipe_bits
|=
1130 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1131 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1135 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1136 uint32_t att
= subpass
->depth_stencil_attachment
.attachment
;
1137 assert(att
< pass
->attachment_count
);
1138 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1139 cmd_buffer
->state
.pending_pipe_bits
|=
1140 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1141 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1147 subpass_needs_clear(const struct anv_cmd_buffer
*cmd_buffer
)
1149 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1150 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1152 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1153 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1154 if (cmd_state
->attachments
[a
].pending_clear_aspects
) {
1159 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1160 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1168 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1170 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1171 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1174 if (!subpass_needs_clear(cmd_buffer
))
1177 /* Because this gets called within a render pass, we tell blorp not to
1178 * trash our depth and stencil buffers.
1180 struct blorp_batch batch
;
1181 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1182 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1184 VkClearRect clear_rect
= {
1185 .rect
= cmd_buffer
->state
.render_area
,
1186 .baseArrayLayer
= 0,
1187 .layerCount
= cmd_buffer
->state
.framebuffer
->layers
,
1190 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1191 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1192 const uint32_t a
= cmd_state
->subpass
->color_attachments
[i
].attachment
;
1193 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
1195 if (!att_state
->pending_clear_aspects
)
1198 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1200 struct anv_image_view
*iview
= fb
->attachments
[a
];
1201 const struct anv_image
*image
= iview
->image
;
1202 struct blorp_surf surf
;
1203 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1204 att_state
->aux_usage
, &surf
);
1206 if (att_state
->fast_clear
) {
1207 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1209 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1211 * "After Render target fast clear, pipe-control with color cache
1212 * write-flush must be issued before sending any DRAW commands on
1213 * that render target."
1215 * This comment is a bit cryptic and doesn't really tell you what's
1216 * going or what's really needed. It appears that fast clear ops are
1217 * not properly synchronized with other drawing. This means that we
1218 * cannot have a fast clear operation in the pipe at the same time as
1219 * other regular drawing operations. We need to use a PIPE_CONTROL
1220 * to ensure that the contents of the previous draw hit the render
1221 * target before we resolve and then use a second PIPE_CONTROL after
1222 * the resolve to ensure that it is completed before any additional
1225 cmd_buffer
->state
.pending_pipe_bits
|=
1226 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1228 blorp_fast_clear(&batch
, &surf
, iview
->isl
.format
,
1229 iview
->isl
.base_level
,
1230 iview
->isl
.base_array_layer
, fb
->layers
,
1231 render_area
.offset
.x
, render_area
.offset
.y
,
1232 render_area
.offset
.x
+ render_area
.extent
.width
,
1233 render_area
.offset
.y
+ render_area
.extent
.height
);
1235 cmd_buffer
->state
.pending_pipe_bits
|=
1236 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1238 blorp_clear(&batch
, &surf
, iview
->isl
.format
,
1239 anv_swizzle_for_render(iview
->isl
.swizzle
),
1240 iview
->isl
.base_level
,
1241 iview
->isl
.base_array_layer
, fb
->layers
,
1242 render_area
.offset
.x
, render_area
.offset
.y
,
1243 render_area
.offset
.x
+ render_area
.extent
.width
,
1244 render_area
.offset
.y
+ render_area
.extent
.height
,
1245 vk_to_isl_color(att_state
->clear_value
.color
), NULL
);
1248 att_state
->pending_clear_aspects
= 0;
1251 const uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
.attachment
;
1253 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1254 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1256 VkClearAttachment clear_att
= {
1257 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1258 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1262 const uint8_t gen
= cmd_buffer
->device
->info
.gen
;
1263 bool clear_with_hiz
= gen
>= 8 && cmd_state
->attachments
[ds
].aux_usage
==
1265 const struct anv_image_view
*iview
= fb
->attachments
[ds
];
1267 if (clear_with_hiz
) {
1268 const bool clear_depth
= clear_att
.aspectMask
&
1269 VK_IMAGE_ASPECT_DEPTH_BIT
;
1270 const bool clear_stencil
= clear_att
.aspectMask
&
1271 VK_IMAGE_ASPECT_STENCIL_BIT
;
1273 /* Check against restrictions for depth buffer clearing. A great GPU
1274 * performance benefit isn't expected when using the HZ sequence for
1275 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1276 * a stencil clear in addition to using the BLORP-fallback for depth.
1279 if (!blorp_can_hiz_clear_depth(gen
, iview
->isl
.format
,
1280 iview
->image
->samples
,
1281 render_area
.offset
.x
,
1282 render_area
.offset
.y
,
1283 render_area
.offset
.x
+
1284 render_area
.extent
.width
,
1285 render_area
.offset
.y
+
1286 render_area
.extent
.height
)) {
1287 clear_with_hiz
= false;
1288 } else if (clear_att
.clearValue
.depthStencil
.depth
!=
1290 /* Don't enable fast depth clears for any color not equal to
1293 clear_with_hiz
= false;
1294 } else if (gen
== 8 &&
1295 anv_can_sample_with_hiz(&cmd_buffer
->device
->info
,
1297 iview
->image
->samples
)) {
1298 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
1299 * fast-cleared portion of a HiZ buffer. Testing has revealed
1300 * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
1301 * not support this feature at all.
1303 clear_with_hiz
= false;
1307 if (clear_with_hiz
) {
1308 blorp_gen8_hiz_clear_attachments(&batch
, iview
->image
->samples
,
1309 render_area
.offset
.x
,
1310 render_area
.offset
.y
,
1311 render_area
.offset
.x
+
1312 render_area
.extent
.width
,
1313 render_area
.offset
.y
+
1314 render_area
.extent
.height
,
1315 clear_depth
, clear_stencil
,
1316 clear_att
.clearValue
.
1317 depthStencil
.stencil
);
1321 if (!clear_with_hiz
) {
1322 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1323 &clear_att
, 1, &clear_rect
);
1326 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
1329 blorp_batch_finish(&batch
);
1331 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_LOAD
);
1335 resolve_image(struct blorp_batch
*batch
,
1336 const struct anv_image
*src_image
,
1337 uint32_t src_level
, uint32_t src_layer
,
1338 const struct anv_image
*dst_image
,
1339 uint32_t dst_level
, uint32_t dst_layer
,
1340 VkImageAspectFlags aspect_mask
,
1341 uint32_t src_x
, uint32_t src_y
, uint32_t dst_x
, uint32_t dst_y
,
1342 uint32_t width
, uint32_t height
)
1344 assert(src_image
->type
== VK_IMAGE_TYPE_2D
);
1345 assert(src_image
->samples
> 1);
1346 assert(dst_image
->type
== VK_IMAGE_TYPE_2D
);
1347 assert(dst_image
->samples
== 1);
1350 for_each_bit(a
, aspect_mask
) {
1351 VkImageAspectFlagBits aspect
= 1 << a
;
1353 struct blorp_surf src_surf
, dst_surf
;
1354 get_blorp_surf_for_anv_image(src_image
, aspect
,
1355 src_image
->aux_usage
, &src_surf
);
1356 get_blorp_surf_for_anv_image(dst_image
, aspect
,
1357 dst_image
->aux_usage
, &dst_surf
);
1360 &src_surf
, src_level
, src_layer
,
1361 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1362 &dst_surf
, dst_level
, dst_layer
,
1363 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1364 src_x
, src_y
, src_x
+ width
, src_y
+ height
,
1365 dst_x
, dst_y
, dst_x
+ width
, dst_y
+ height
,
1366 0x2600 /* GL_NEAREST */, false, false);
1370 void anv_CmdResolveImage(
1371 VkCommandBuffer commandBuffer
,
1373 VkImageLayout srcImageLayout
,
1375 VkImageLayout dstImageLayout
,
1376 uint32_t regionCount
,
1377 const VkImageResolve
* pRegions
)
1379 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1380 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
1381 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
1383 struct blorp_batch batch
;
1384 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1386 for (uint32_t r
= 0; r
< regionCount
; r
++) {
1387 assert(pRegions
[r
].srcSubresource
.aspectMask
==
1388 pRegions
[r
].dstSubresource
.aspectMask
);
1389 assert(pRegions
[r
].srcSubresource
.layerCount
==
1390 pRegions
[r
].dstSubresource
.layerCount
);
1392 const uint32_t layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
1394 for (uint32_t layer
= 0; layer
< layer_count
; layer
++) {
1395 resolve_image(&batch
,
1396 src_image
, pRegions
[r
].srcSubresource
.mipLevel
,
1397 pRegions
[r
].srcSubresource
.baseArrayLayer
+ layer
,
1398 dst_image
, pRegions
[r
].dstSubresource
.mipLevel
,
1399 pRegions
[r
].dstSubresource
.baseArrayLayer
+ layer
,
1400 pRegions
[r
].dstSubresource
.aspectMask
,
1401 pRegions
[r
].srcOffset
.x
, pRegions
[r
].srcOffset
.y
,
1402 pRegions
[r
].dstOffset
.x
, pRegions
[r
].dstOffset
.y
,
1403 pRegions
[r
].extent
.width
, pRegions
[r
].extent
.height
);
1407 blorp_batch_finish(&batch
);
1411 ccs_resolve_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1412 struct blorp_batch
*batch
,
1415 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1416 struct anv_attachment_state
*att_state
=
1417 &cmd_buffer
->state
.attachments
[att
];
1419 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
||
1420 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
)
1421 return; /* Nothing to resolve */
1423 assert(att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1424 att_state
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1426 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1427 const uint32_t subpass_idx
= anv_get_subpass_id(&cmd_buffer
->state
);
1429 /* Scan forward to see what all ways this attachment will be used.
1430 * Ideally, we would like to resolve in the same subpass as the last write
1431 * of a particular attachment. That way we only resolve once but it's
1432 * still hot in the cache.
1434 bool found_draw
= false;
1435 enum anv_subpass_usage usage
= 0;
1436 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1437 usage
|= pass
->attachments
[att
].subpass_usage
[s
];
1439 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1440 /* We found another subpass that draws to this attachment. We'll
1441 * wait to resolve until then.
1448 struct anv_image_view
*iview
= fb
->attachments
[att
];
1449 const struct anv_image
*image
= iview
->image
;
1450 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1452 enum blorp_fast_clear_op resolve_op
= BLORP_FAST_CLEAR_OP_NONE
;
1454 /* This is the last subpass that writes to this attachment so we need to
1455 * resolve here. Ideally, we would like to only resolve if the storeOp
1456 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1457 * that the CCS bits are set to "resolved" because there may be copy or
1458 * blit operations (which may ignore CCS) between now and the next time
1459 * we render and we need to ensure that anything they write will be
1460 * respected in the next render. Unfortunately, the hardware does not
1461 * provide us with any sort of "invalidate" pass that sets the CCS to
1462 * "resolved" without writing to the render target.
1464 if (iview
->image
->aux_usage
!= ISL_AUX_USAGE_CCS_E
) {
1465 /* The image destination surface doesn't support compression outside
1466 * the render pass. We need a full resolve.
1468 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1469 } else if (att_state
->fast_clear
) {
1470 /* We don't know what to do with clear colors outside the render
1471 * pass. We need a partial resolve. Only transparent black is
1472 * built into the surface state object and thus no resolve is
1473 * required for this case.
1475 if (att_state
->clear_value
.color
.uint32
[0] ||
1476 att_state
->clear_value
.color
.uint32
[1] ||
1477 att_state
->clear_value
.color
.uint32
[2] ||
1478 att_state
->clear_value
.color
.uint32
[3])
1479 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1481 /* The image "natively" supports all the compression we care about
1482 * and we don't need to resolve at all. If this is the case, we also
1483 * don't need to resolve for any of the input attachment cases below.
1486 } else if (usage
& ANV_SUBPASS_USAGE_INPUT
) {
1487 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1488 * can frequently sample from them with no resolves at all.
1490 if (att_state
->aux_usage
!= att_state
->input_aux_usage
) {
1491 assert(att_state
->input_aux_usage
== ISL_AUX_USAGE_NONE
);
1492 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1493 } else if (!att_state
->clear_color_is_zero_one
) {
1494 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1496 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1497 * is fast cleared with non-0/1 clear value, this RT must be
1498 * partially resolved (refer to Partial Resolve operation) before
1499 * binding this surface to Sampler."
1501 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1505 if (resolve_op
== BLORP_FAST_CLEAR_OP_NONE
)
1508 struct blorp_surf surf
;
1509 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1510 att_state
->aux_usage
, &surf
);
1511 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1513 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1515 * "When performing a render target resolve, PIPE_CONTROL with end of
1516 * pipe sync must be delivered."
1518 * This comment is a bit cryptic and doesn't really tell you what's going
1519 * or what's really needed. It appears that fast clear ops are not
1520 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1521 * to ensure that the contents of the previous draw hit the render target
1522 * before we resolve and then use a second PIPE_CONTROL after the resolve
1523 * to ensure that it is completed before any additional drawing occurs.
1525 cmd_buffer
->state
.pending_pipe_bits
|=
1526 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1528 for (uint32_t layer
= 0; layer
< fb
->layers
; layer
++) {
1529 blorp_ccs_resolve(batch
, &surf
,
1530 iview
->isl
.base_level
,
1531 iview
->isl
.base_array_layer
+ layer
,
1532 iview
->isl
.format
, resolve_op
);
1535 cmd_buffer
->state
.pending_pipe_bits
|=
1536 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1538 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1539 att_state
->fast_clear
= false;
1543 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1545 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1546 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1549 struct blorp_batch batch
;
1550 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1552 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1553 ccs_resolve_attachment(cmd_buffer
, &batch
,
1554 subpass
->color_attachments
[i
].attachment
);
1557 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_DRAW
);
1559 if (subpass
->has_resolve
) {
1560 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1561 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
1562 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
1564 if (dst_att
== VK_ATTACHMENT_UNUSED
)
1567 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
1568 /* From the Vulkan 1.0 spec:
1570 * If the first use of an attachment in a render pass is as a
1571 * resolve attachment, then the loadOp is effectively ignored
1572 * as the resolve is guaranteed to overwrite all pixels in the
1575 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
1578 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
1579 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
1581 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1583 assert(src_iview
->aspect_mask
== dst_iview
->aspect_mask
);
1584 resolve_image(&batch
, src_iview
->image
,
1585 src_iview
->isl
.base_level
,
1586 src_iview
->isl
.base_array_layer
,
1588 dst_iview
->isl
.base_level
,
1589 dst_iview
->isl
.base_array_layer
,
1590 src_iview
->aspect_mask
,
1591 render_area
.offset
.x
, render_area
.offset
.y
,
1592 render_area
.offset
.x
, render_area
.offset
.y
,
1593 render_area
.extent
.width
, render_area
.extent
.height
);
1595 ccs_resolve_attachment(cmd_buffer
, &batch
, dst_att
);
1598 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_RESOLVE
);
1601 blorp_batch_finish(&batch
);
1605 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1606 const struct anv_image
*image
,
1607 enum blorp_hiz_op op
)
1611 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1612 * don't perform such a resolve on gens that don't support it.
1614 if (cmd_buffer
->device
->info
.gen
< 8 ||
1615 image
->aux_usage
!= ISL_AUX_USAGE_HIZ
)
1618 assert(op
== BLORP_HIZ_OP_HIZ_RESOLVE
||
1619 op
== BLORP_HIZ_OP_DEPTH_RESOLVE
);
1621 struct blorp_batch batch
;
1622 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1624 struct blorp_surf surf
;
1625 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1626 ISL_AUX_USAGE_NONE
, &surf
);
1628 /* Manually add the aux HiZ surf */
1629 surf
.aux_surf
= &image
->aux_surface
.isl
,
1630 surf
.aux_addr
= (struct blorp_address
) {
1631 .buffer
= image
->bo
,
1632 .offset
= image
->offset
+ image
->aux_surface
.offset
,
1634 surf
.aux_usage
= ISL_AUX_USAGE_HIZ
;
1636 surf
.clear_color
.u32
[0] = (uint32_t) ANV_HZ_FC_VAL
;
1638 blorp_gen6_hiz_op(&batch
, &surf
, 0, 0, op
);
1639 blorp_batch_finish(&batch
);