2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
27 lookup_blorp_shader(struct blorp_batch
*batch
,
28 const void *key
, uint32_t key_size
,
29 uint32_t *kernel_out
, void *prog_data_out
)
31 struct blorp_context
*blorp
= batch
->blorp
;
32 struct anv_device
*device
= blorp
->driver_ctx
;
34 /* The default cache must be a real cache */
35 assert(device
->default_pipeline_cache
.cache
);
37 struct anv_shader_bin
*bin
=
38 anv_pipeline_cache_search(&device
->default_pipeline_cache
, key
, key_size
);
42 /* The cache already has a reference and it's not going anywhere so there
43 * is no need to hold a second reference.
45 anv_shader_bin_unref(device
, bin
);
47 *kernel_out
= bin
->kernel
.offset
;
48 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
54 upload_blorp_shader(struct blorp_batch
*batch
,
55 const void *key
, uint32_t key_size
,
56 const void *kernel
, uint32_t kernel_size
,
57 const struct brw_stage_prog_data
*prog_data
,
58 uint32_t prog_data_size
,
59 uint32_t *kernel_out
, void *prog_data_out
)
61 struct blorp_context
*blorp
= batch
->blorp
;
62 struct anv_device
*device
= blorp
->driver_ctx
;
64 /* The blorp cache must be a real cache */
65 assert(device
->default_pipeline_cache
.cache
);
67 struct anv_pipeline_bind_map bind_map
= {
72 struct anv_shader_bin
*bin
=
73 anv_pipeline_cache_upload_kernel(&device
->default_pipeline_cache
,
74 key
, key_size
, kernel
, kernel_size
,
76 prog_data
, prog_data_size
,
82 /* The cache already has a reference and it's not going anywhere so there
83 * is no need to hold a second reference.
85 anv_shader_bin_unref(device
, bin
);
87 *kernel_out
= bin
->kernel
.offset
;
88 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
94 anv_device_init_blorp(struct anv_device
*device
)
96 blorp_init(&device
->blorp
, device
, &device
->isl_dev
);
97 device
->blorp
.compiler
= device
->instance
->physicalDevice
.compiler
;
98 device
->blorp
.lookup_shader
= lookup_blorp_shader
;
99 device
->blorp
.upload_shader
= upload_blorp_shader
;
100 switch (device
->info
.gen
) {
102 if (device
->info
.is_haswell
) {
103 device
->blorp
.exec
= gen75_blorp_exec
;
105 device
->blorp
.exec
= gen7_blorp_exec
;
109 device
->blorp
.exec
= gen8_blorp_exec
;
112 device
->blorp
.exec
= gen9_blorp_exec
;
115 device
->blorp
.exec
= gen10_blorp_exec
;
118 device
->blorp
.exec
= gen11_blorp_exec
;
121 unreachable("Unknown hardware generation");
126 anv_device_finish_blorp(struct anv_device
*device
)
128 blorp_finish(&device
->blorp
);
132 get_blorp_surf_for_anv_buffer(struct anv_device
*device
,
133 struct anv_buffer
*buffer
, uint64_t offset
,
134 uint32_t width
, uint32_t height
,
135 uint32_t row_pitch
, enum isl_format format
,
136 struct blorp_surf
*blorp_surf
,
137 struct isl_surf
*isl_surf
)
139 const struct isl_format_layout
*fmtl
=
140 isl_format_get_layout(format
);
143 /* ASTC is the only format which doesn't support linear layouts.
144 * Create an equivalently sized surface with ISL to get around this.
146 if (fmtl
->txc
== ISL_TXC_ASTC
) {
147 /* Use an equivalently sized format */
148 format
= ISL_FORMAT_R32G32B32A32_UINT
;
149 assert(fmtl
->bpb
== isl_format_get_layout(format
)->bpb
);
151 /* Shrink the dimensions for the new format */
152 width
= DIV_ROUND_UP(width
, fmtl
->bw
);
153 height
= DIV_ROUND_UP(height
, fmtl
->bh
);
156 *blorp_surf
= (struct blorp_surf
) {
159 .buffer
= buffer
->address
.bo
,
160 .offset
= buffer
->address
.offset
+ offset
,
161 .mocs
= anv_mocs_for_bo(device
, buffer
->address
.bo
),
165 ok
= isl_surf_init(&device
->isl_dev
, isl_surf
,
166 .dim
= ISL_SURF_DIM_2D
,
174 .row_pitch_B
= row_pitch
,
175 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
176 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
177 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
181 /* Pick something high enough that it won't be used in core and low enough it
182 * will never map to an extension.
184 #define ANV_IMAGE_LAYOUT_EXPLICIT_AUX (VkImageLayout)10000000
186 static struct blorp_address
187 anv_to_blorp_address(struct anv_address addr
)
189 return (struct blorp_address
) {
191 .offset
= addr
.offset
,
196 get_blorp_surf_for_anv_image(const struct anv_device
*device
,
197 const struct anv_image
*image
,
198 VkImageAspectFlags aspect
,
199 VkImageLayout layout
,
200 enum isl_aux_usage aux_usage
,
201 struct blorp_surf
*blorp_surf
)
203 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
205 if (layout
!= ANV_IMAGE_LAYOUT_EXPLICIT_AUX
)
206 aux_usage
= anv_layout_to_aux_usage(&device
->info
, image
, aspect
, layout
);
208 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
;
209 *blorp_surf
= (struct blorp_surf
) {
210 .surf
= &surface
->isl
,
212 .buffer
= image
->planes
[plane
].address
.bo
,
213 .offset
= image
->planes
[plane
].address
.offset
+ surface
->offset
,
214 .mocs
= anv_mocs_for_bo(device
, image
->planes
[plane
].address
.bo
),
218 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
219 const struct anv_surface
*aux_surface
= &image
->planes
[plane
].aux_surface
;
220 blorp_surf
->aux_surf
= &aux_surface
->isl
,
221 blorp_surf
->aux_addr
= (struct blorp_address
) {
222 .buffer
= image
->planes
[plane
].address
.bo
,
223 .offset
= image
->planes
[plane
].address
.offset
+ aux_surface
->offset
,
224 .mocs
= anv_mocs_for_bo(device
, image
->planes
[plane
].address
.bo
),
226 blorp_surf
->aux_usage
= aux_usage
;
228 /* If we're doing a partial resolve, then we need the indirect clear
229 * color. If we are doing a fast clear and want to store/update the
230 * clear color, we also pass the address to blorp, otherwise it will only
231 * stomp the CCS to a particular value and won't care about format or
234 if (aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
235 const struct anv_address clear_color_addr
=
236 anv_image_get_clear_color_addr(device
, image
, aspect
);
237 blorp_surf
->clear_color_addr
= anv_to_blorp_address(clear_color_addr
);
238 } else if (aspect
& VK_IMAGE_ASPECT_DEPTH_BIT
239 && device
->info
.gen
>= 10) {
240 /* Vulkan always clears to 1.0. On gen < 10, we set that directly in
241 * the state packet. For gen >= 10, must provide the clear value in a
242 * buffer. We have a single global buffer that stores the 1.0 value.
244 const struct anv_address clear_color_addr
= (struct anv_address
) {
245 .bo
= (struct anv_bo
*)&device
->hiz_clear_bo
247 blorp_surf
->clear_color_addr
= anv_to_blorp_address(clear_color_addr
);
252 void anv_CmdCopyImage(
253 VkCommandBuffer commandBuffer
,
255 VkImageLayout srcImageLayout
,
257 VkImageLayout dstImageLayout
,
258 uint32_t regionCount
,
259 const VkImageCopy
* pRegions
)
261 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
262 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
263 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
265 struct blorp_batch batch
;
266 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
268 for (unsigned r
= 0; r
< regionCount
; r
++) {
269 VkOffset3D srcOffset
=
270 anv_sanitize_image_offset(src_image
->type
, pRegions
[r
].srcOffset
);
271 VkOffset3D dstOffset
=
272 anv_sanitize_image_offset(dst_image
->type
, pRegions
[r
].dstOffset
);
274 anv_sanitize_image_extent(src_image
->type
, pRegions
[r
].extent
);
276 const uint32_t dst_level
= pRegions
[r
].dstSubresource
.mipLevel
;
277 unsigned dst_base_layer
, layer_count
;
278 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
279 dst_base_layer
= pRegions
[r
].dstOffset
.z
;
280 layer_count
= pRegions
[r
].extent
.depth
;
282 dst_base_layer
= pRegions
[r
].dstSubresource
.baseArrayLayer
;
284 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
);
287 const uint32_t src_level
= pRegions
[r
].srcSubresource
.mipLevel
;
288 unsigned src_base_layer
;
289 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
290 src_base_layer
= pRegions
[r
].srcOffset
.z
;
292 src_base_layer
= pRegions
[r
].srcSubresource
.baseArrayLayer
;
293 assert(layer_count
==
294 anv_get_layerCount(src_image
, &pRegions
[r
].srcSubresource
));
297 VkImageAspectFlags src_mask
= pRegions
[r
].srcSubresource
.aspectMask
,
298 dst_mask
= pRegions
[r
].dstSubresource
.aspectMask
;
300 assert(anv_image_aspects_compatible(src_mask
, dst_mask
));
302 if (util_bitcount(src_mask
) > 1) {
304 anv_foreach_image_aspect_bit(aspect_bit
, src_image
, src_mask
) {
305 struct blorp_surf src_surf
, dst_surf
;
306 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
307 src_image
, 1UL << aspect_bit
,
308 srcImageLayout
, ISL_AUX_USAGE_NONE
,
310 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
311 dst_image
, 1UL << aspect_bit
,
312 dstImageLayout
, ISL_AUX_USAGE_NONE
,
314 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
316 dst_surf
.aux_usage
, dst_level
,
317 dst_base_layer
, layer_count
);
319 for (unsigned i
= 0; i
< layer_count
; i
++) {
320 blorp_copy(&batch
, &src_surf
, src_level
, src_base_layer
+ i
,
321 &dst_surf
, dst_level
, dst_base_layer
+ i
,
322 srcOffset
.x
, srcOffset
.y
,
323 dstOffset
.x
, dstOffset
.y
,
324 extent
.width
, extent
.height
);
328 struct blorp_surf src_surf
, dst_surf
;
329 get_blorp_surf_for_anv_image(cmd_buffer
->device
, src_image
, src_mask
,
330 srcImageLayout
, ISL_AUX_USAGE_NONE
,
332 get_blorp_surf_for_anv_image(cmd_buffer
->device
, dst_image
, dst_mask
,
333 dstImageLayout
, ISL_AUX_USAGE_NONE
,
335 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
, dst_mask
,
336 dst_surf
.aux_usage
, dst_level
,
337 dst_base_layer
, layer_count
);
339 for (unsigned i
= 0; i
< layer_count
; i
++) {
340 blorp_copy(&batch
, &src_surf
, src_level
, src_base_layer
+ i
,
341 &dst_surf
, dst_level
, dst_base_layer
+ i
,
342 srcOffset
.x
, srcOffset
.y
,
343 dstOffset
.x
, dstOffset
.y
,
344 extent
.width
, extent
.height
);
349 blorp_batch_finish(&batch
);
353 copy_buffer_to_image(struct anv_cmd_buffer
*cmd_buffer
,
354 struct anv_buffer
*anv_buffer
,
355 struct anv_image
*anv_image
,
356 VkImageLayout image_layout
,
357 uint32_t regionCount
,
358 const VkBufferImageCopy
* pRegions
,
359 bool buffer_to_image
)
361 struct blorp_batch batch
;
362 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
365 struct blorp_surf surf
;
368 } image
, buffer
, *src
, *dst
;
371 buffer
.offset
= (VkOffset3D
) { 0, 0, 0 };
373 if (buffer_to_image
) {
381 for (unsigned r
= 0; r
< regionCount
; r
++) {
382 const VkImageAspectFlags aspect
= pRegions
[r
].imageSubresource
.aspectMask
;
384 get_blorp_surf_for_anv_image(cmd_buffer
->device
, anv_image
, aspect
,
385 image_layout
, ISL_AUX_USAGE_NONE
,
388 anv_sanitize_image_offset(anv_image
->type
, pRegions
[r
].imageOffset
);
389 image
.level
= pRegions
[r
].imageSubresource
.mipLevel
;
392 anv_sanitize_image_extent(anv_image
->type
, pRegions
[r
].imageExtent
);
393 if (anv_image
->type
!= VK_IMAGE_TYPE_3D
) {
394 image
.offset
.z
= pRegions
[r
].imageSubresource
.baseArrayLayer
;
396 anv_get_layerCount(anv_image
, &pRegions
[r
].imageSubresource
);
399 const enum isl_format buffer_format
=
400 anv_get_isl_format(&cmd_buffer
->device
->info
, anv_image
->vk_format
,
401 aspect
, VK_IMAGE_TILING_LINEAR
);
403 const VkExtent3D bufferImageExtent
= {
404 .width
= pRegions
[r
].bufferRowLength
?
405 pRegions
[r
].bufferRowLength
: extent
.width
,
406 .height
= pRegions
[r
].bufferImageHeight
?
407 pRegions
[r
].bufferImageHeight
: extent
.height
,
410 const struct isl_format_layout
*buffer_fmtl
=
411 isl_format_get_layout(buffer_format
);
413 const uint32_t buffer_row_pitch
=
414 DIV_ROUND_UP(bufferImageExtent
.width
, buffer_fmtl
->bw
) *
415 (buffer_fmtl
->bpb
/ 8);
417 const uint32_t buffer_layer_stride
=
418 DIV_ROUND_UP(bufferImageExtent
.height
, buffer_fmtl
->bh
) *
421 struct isl_surf buffer_isl_surf
;
422 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
423 anv_buffer
, pRegions
[r
].bufferOffset
,
424 extent
.width
, extent
.height
,
425 buffer_row_pitch
, buffer_format
,
426 &buffer
.surf
, &buffer_isl_surf
);
429 anv_cmd_buffer_mark_image_written(cmd_buffer
, anv_image
,
430 aspect
, dst
->surf
.aux_usage
,
432 dst
->offset
.z
, extent
.depth
);
435 for (unsigned z
= 0; z
< extent
.depth
; z
++) {
436 blorp_copy(&batch
, &src
->surf
, src
->level
, src
->offset
.z
,
437 &dst
->surf
, dst
->level
, dst
->offset
.z
,
438 src
->offset
.x
, src
->offset
.y
, dst
->offset
.x
, dst
->offset
.y
,
439 extent
.width
, extent
.height
);
442 buffer
.surf
.addr
.offset
+= buffer_layer_stride
;
446 blorp_batch_finish(&batch
);
449 void anv_CmdCopyBufferToImage(
450 VkCommandBuffer commandBuffer
,
453 VkImageLayout dstImageLayout
,
454 uint32_t regionCount
,
455 const VkBufferImageCopy
* pRegions
)
457 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
458 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
459 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
461 copy_buffer_to_image(cmd_buffer
, src_buffer
, dst_image
, dstImageLayout
,
462 regionCount
, pRegions
, true);
465 void anv_CmdCopyImageToBuffer(
466 VkCommandBuffer commandBuffer
,
468 VkImageLayout srcImageLayout
,
470 uint32_t regionCount
,
471 const VkBufferImageCopy
* pRegions
)
473 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
474 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
475 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
477 copy_buffer_to_image(cmd_buffer
, dst_buffer
, src_image
, srcImageLayout
,
478 regionCount
, pRegions
, false);
480 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
;
484 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
488 unsigned tmp
= *src0
;
495 unsigned tmp
= *dst0
;
504 void anv_CmdBlitImage(
505 VkCommandBuffer commandBuffer
,
507 VkImageLayout srcImageLayout
,
509 VkImageLayout dstImageLayout
,
510 uint32_t regionCount
,
511 const VkImageBlit
* pRegions
,
515 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
516 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
517 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
519 struct blorp_surf src
, dst
;
521 enum blorp_filter blorp_filter
;
523 case VK_FILTER_NEAREST
:
524 blorp_filter
= BLORP_FILTER_NEAREST
;
526 case VK_FILTER_LINEAR
:
527 blorp_filter
= BLORP_FILTER_BILINEAR
;
530 unreachable("Invalid filter");
533 struct blorp_batch batch
;
534 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
536 for (unsigned r
= 0; r
< regionCount
; r
++) {
537 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
538 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
540 assert(anv_image_aspects_compatible(src_res
->aspectMask
,
541 dst_res
->aspectMask
));
544 anv_foreach_image_aspect_bit(aspect_bit
, src_image
, src_res
->aspectMask
) {
545 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
546 src_image
, 1U << aspect_bit
,
547 srcImageLayout
, ISL_AUX_USAGE_NONE
, &src
);
548 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
549 dst_image
, 1U << aspect_bit
,
550 dstImageLayout
, ISL_AUX_USAGE_NONE
, &dst
);
552 struct anv_format_plane src_format
=
553 anv_get_format_plane(&cmd_buffer
->device
->info
, src_image
->vk_format
,
554 1U << aspect_bit
, src_image
->tiling
);
555 struct anv_format_plane dst_format
=
556 anv_get_format_plane(&cmd_buffer
->device
->info
, dst_image
->vk_format
,
557 1U << aspect_bit
, dst_image
->tiling
);
559 unsigned dst_start
, dst_end
;
560 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
561 assert(dst_res
->baseArrayLayer
== 0);
562 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
563 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
565 dst_start
= dst_res
->baseArrayLayer
;
566 dst_end
= dst_start
+ anv_get_layerCount(dst_image
, dst_res
);
569 unsigned src_start
, src_end
;
570 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
571 assert(src_res
->baseArrayLayer
== 0);
572 src_start
= pRegions
[r
].srcOffsets
[0].z
;
573 src_end
= pRegions
[r
].srcOffsets
[1].z
;
575 src_start
= src_res
->baseArrayLayer
;
576 src_end
= src_start
+ anv_get_layerCount(src_image
, src_res
);
579 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
580 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
581 (float)(dst_end
+ 1 - dst_start
);
588 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
589 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
590 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
591 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
592 bool flip_x
= flip_coords(&src_x0
, &src_x1
, &dst_x0
, &dst_x1
);
594 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
595 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
596 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
597 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
598 bool flip_y
= flip_coords(&src_y0
, &src_y1
, &dst_y0
, &dst_y1
);
600 const unsigned num_layers
= dst_end
- dst_start
;
601 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
605 dst_start
, num_layers
);
607 for (unsigned i
= 0; i
< num_layers
; i
++) {
608 unsigned dst_z
= dst_start
+ i
;
609 unsigned src_z
= src_start
+ i
* src_z_step
;
611 blorp_blit(&batch
, &src
, src_res
->mipLevel
, src_z
,
612 src_format
.isl_format
, src_format
.swizzle
,
613 &dst
, dst_res
->mipLevel
, dst_z
,
614 dst_format
.isl_format
, dst_format
.swizzle
,
615 src_x0
, src_y0
, src_x1
, src_y1
,
616 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
617 blorp_filter
, flip_x
, flip_y
);
622 blorp_batch_finish(&batch
);
625 static enum isl_format
626 isl_format_for_size(unsigned size_B
)
629 case 4: return ISL_FORMAT_R32_UINT
;
630 case 8: return ISL_FORMAT_R32G32_UINT
;
631 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
633 unreachable("Not a power-of-two format size");
638 * Returns the greatest common divisor of a and b that is a power of two.
641 gcd_pow2_u64(uint64_t a
, uint64_t b
)
643 assert(a
> 0 || b
> 0);
645 unsigned a_log2
= ffsll(a
) - 1;
646 unsigned b_log2
= ffsll(b
) - 1;
648 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
649 * case, the MIN2() will take the other one. If both are 0 then we will
650 * hit the assert above.
652 return 1 << MIN2(a_log2
, b_log2
);
655 /* This is maximum possible width/height our HW can handle */
656 #define MAX_SURFACE_DIM (1ull << 14)
658 void anv_CmdCopyBuffer(
659 VkCommandBuffer commandBuffer
,
662 uint32_t regionCount
,
663 const VkBufferCopy
* pRegions
)
665 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
666 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
667 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
669 struct blorp_batch batch
;
670 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
672 for (unsigned r
= 0; r
< regionCount
; r
++) {
673 struct blorp_address src
= {
674 .buffer
= src_buffer
->address
.bo
,
675 .offset
= src_buffer
->address
.offset
+ pRegions
[r
].srcOffset
,
676 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, src_buffer
->address
.bo
),
678 struct blorp_address dst
= {
679 .buffer
= dst_buffer
->address
.bo
,
680 .offset
= dst_buffer
->address
.offset
+ pRegions
[r
].dstOffset
,
681 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, dst_buffer
->address
.bo
),
684 blorp_buffer_copy(&batch
, src
, dst
, pRegions
[r
].size
);
687 blorp_batch_finish(&batch
);
689 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
;
692 void anv_CmdUpdateBuffer(
693 VkCommandBuffer commandBuffer
,
695 VkDeviceSize dstOffset
,
696 VkDeviceSize dataSize
,
699 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
700 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
702 struct blorp_batch batch
;
703 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
705 /* We can't quite grab a full block because the state stream needs a
706 * little data at the top to build its linked list.
708 const uint32_t max_update_size
=
709 cmd_buffer
->device
->dynamic_state_pool
.block_size
- 64;
711 assert(max_update_size
< MAX_SURFACE_DIM
* 4);
713 /* We're about to read data that was written from the CPU. Flush the
714 * texture cache so we don't get anything stale.
716 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
719 const uint32_t copy_size
= MIN2(dataSize
, max_update_size
);
721 struct anv_state tmp_data
=
722 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, copy_size
, 64);
724 memcpy(tmp_data
.map
, pData
, copy_size
);
726 struct blorp_address src
= {
727 .buffer
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
728 .offset
= tmp_data
.offset
,
729 .mocs
= cmd_buffer
->device
->default_mocs
,
731 struct blorp_address dst
= {
732 .buffer
= dst_buffer
->address
.bo
,
733 .offset
= dst_buffer
->address
.offset
+ dstOffset
,
734 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, dst_buffer
->address
.bo
),
737 blorp_buffer_copy(&batch
, src
, dst
, copy_size
);
739 dataSize
-= copy_size
;
740 dstOffset
+= copy_size
;
741 pData
= (void *)pData
+ copy_size
;
744 blorp_batch_finish(&batch
);
746 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
;
749 void anv_CmdFillBuffer(
750 VkCommandBuffer commandBuffer
,
752 VkDeviceSize dstOffset
,
753 VkDeviceSize fillSize
,
756 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
757 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
758 struct blorp_surf surf
;
759 struct isl_surf isl_surf
;
761 struct blorp_batch batch
;
762 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
764 fillSize
= anv_buffer_get_range(dst_buffer
, dstOffset
, fillSize
);
766 /* From the Vulkan spec:
768 * "size is the number of bytes to fill, and must be either a multiple
769 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
770 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
771 * buffer is not a multiple of 4, then the nearest smaller multiple is
776 /* First, we compute the biggest format that can be used with the
777 * given offsets and size.
780 bs
= gcd_pow2_u64(bs
, dstOffset
);
781 bs
= gcd_pow2_u64(bs
, fillSize
);
782 enum isl_format isl_format
= isl_format_for_size(bs
);
784 union isl_color_value color
= {
785 .u32
= { data
, data
, data
, data
},
788 const uint64_t max_fill_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
789 while (fillSize
>= max_fill_size
) {
790 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
791 dst_buffer
, dstOffset
,
792 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
793 MAX_SURFACE_DIM
* bs
, isl_format
,
796 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
797 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
799 fillSize
-= max_fill_size
;
800 dstOffset
+= max_fill_size
;
803 uint64_t height
= fillSize
/ (MAX_SURFACE_DIM
* bs
);
804 assert(height
< MAX_SURFACE_DIM
);
806 const uint64_t rect_fill_size
= height
* MAX_SURFACE_DIM
* bs
;
807 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
808 dst_buffer
, dstOffset
,
809 MAX_SURFACE_DIM
, height
,
810 MAX_SURFACE_DIM
* bs
, isl_format
,
813 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
814 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, height
,
816 fillSize
-= rect_fill_size
;
817 dstOffset
+= rect_fill_size
;
821 const uint32_t width
= fillSize
/ bs
;
822 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
823 dst_buffer
, dstOffset
,
825 width
* bs
, isl_format
,
828 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
829 0, 0, 1, 0, 0, width
, 1,
833 blorp_batch_finish(&batch
);
835 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
;
838 void anv_CmdClearColorImage(
839 VkCommandBuffer commandBuffer
,
841 VkImageLayout imageLayout
,
842 const VkClearColorValue
* pColor
,
844 const VkImageSubresourceRange
* pRanges
)
846 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
847 ANV_FROM_HANDLE(anv_image
, image
, _image
);
849 static const bool color_write_disable
[4] = { false, false, false, false };
851 struct blorp_batch batch
;
852 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
855 for (unsigned r
= 0; r
< rangeCount
; r
++) {
856 if (pRanges
[r
].aspectMask
== 0)
859 assert(pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
861 struct blorp_surf surf
;
862 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
863 image
, pRanges
[r
].aspectMask
,
864 imageLayout
, ISL_AUX_USAGE_NONE
, &surf
);
866 struct anv_format_plane src_format
=
867 anv_get_format_plane(&cmd_buffer
->device
->info
, image
->vk_format
,
868 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
870 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
871 unsigned layer_count
= anv_get_layerCount(image
, &pRanges
[r
]);
873 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
874 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
875 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
876 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
878 if (image
->type
== VK_IMAGE_TYPE_3D
) {
880 layer_count
= anv_minify(image
->extent
.depth
, level
);
883 anv_cmd_buffer_mark_image_written(cmd_buffer
, image
,
884 pRanges
[r
].aspectMask
,
885 surf
.aux_usage
, level
,
886 base_layer
, layer_count
);
888 blorp_clear(&batch
, &surf
,
889 src_format
.isl_format
, src_format
.swizzle
,
890 level
, base_layer
, layer_count
,
891 0, 0, level_width
, level_height
,
892 vk_to_isl_color(*pColor
), color_write_disable
);
896 blorp_batch_finish(&batch
);
899 void anv_CmdClearDepthStencilImage(
900 VkCommandBuffer commandBuffer
,
902 VkImageLayout imageLayout
,
903 const VkClearDepthStencilValue
* pDepthStencil
,
905 const VkImageSubresourceRange
* pRanges
)
907 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
908 ANV_FROM_HANDLE(anv_image
, image
, image_h
);
910 struct blorp_batch batch
;
911 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
913 struct blorp_surf depth
, stencil
;
914 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
915 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
916 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
917 imageLayout
, ISL_AUX_USAGE_NONE
, &depth
);
919 memset(&depth
, 0, sizeof(depth
));
922 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
923 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
924 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
925 imageLayout
, ISL_AUX_USAGE_NONE
, &stencil
);
927 memset(&stencil
, 0, sizeof(stencil
));
930 for (unsigned r
= 0; r
< rangeCount
; r
++) {
931 if (pRanges
[r
].aspectMask
== 0)
934 bool clear_depth
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
935 bool clear_stencil
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
937 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
938 unsigned layer_count
= anv_get_layerCount(image
, &pRanges
[r
]);
940 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
941 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
942 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
943 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
945 if (image
->type
== VK_IMAGE_TYPE_3D
)
946 layer_count
= anv_minify(image
->extent
.depth
, level
);
948 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
949 level
, base_layer
, layer_count
,
950 0, 0, level_width
, level_height
,
951 clear_depth
, pDepthStencil
->depth
,
952 clear_stencil
? 0xff : 0,
953 pDepthStencil
->stencil
);
957 blorp_batch_finish(&batch
);
961 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
962 uint32_t num_entries
,
963 uint32_t *state_offset
,
964 struct anv_state
*bt_state
)
966 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
968 if (bt_state
->map
== NULL
) {
969 /* We ran out of space. Grab a new binding table block. */
970 VkResult result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
971 if (result
!= VK_SUCCESS
)
974 /* Re-emit state base addresses so we get the new surface state base
975 * address before we start emitting binding tables etc.
977 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
979 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
981 assert(bt_state
->map
!= NULL
);
988 binding_table_for_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
989 struct anv_state surface_state
,
992 uint32_t state_offset
;
993 struct anv_state bt_state
;
996 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, 1, &state_offset
,
998 if (result
!= VK_SUCCESS
)
1001 uint32_t *bt_map
= bt_state
.map
;
1002 bt_map
[0] = surface_state
.offset
+ state_offset
;
1004 *bt_offset
= bt_state
.offset
;
1009 clear_color_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1010 struct blorp_batch
*batch
,
1011 const VkClearAttachment
*attachment
,
1012 uint32_t rectCount
, const VkClearRect
*pRects
)
1014 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1015 const uint32_t color_att
= attachment
->colorAttachment
;
1016 assert(color_att
< subpass
->color_count
);
1017 const uint32_t att_idx
= subpass
->color_attachments
[color_att
].attachment
;
1019 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1022 struct anv_render_pass_attachment
*pass_att
=
1023 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
1024 struct anv_attachment_state
*att_state
=
1025 &cmd_buffer
->state
.attachments
[att_idx
];
1027 uint32_t binding_table
;
1029 binding_table_for_surface_state(cmd_buffer
, att_state
->color
.state
,
1031 if (result
!= VK_SUCCESS
)
1034 union isl_color_value clear_color
=
1035 vk_to_isl_color(attachment
->clearValue
.color
);
1037 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1038 if (subpass
->view_mask
) {
1040 for_each_bit(view_idx
, subpass
->view_mask
) {
1041 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1042 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1043 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1044 blorp_clear_attachments(batch
, binding_table
,
1045 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
1048 offset
.x
+ extent
.width
,
1049 offset
.y
+ extent
.height
,
1050 true, clear_color
, false, 0.0f
, 0, 0);
1056 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1057 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1058 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1059 assert(pRects
[r
].layerCount
!= VK_REMAINING_ARRAY_LAYERS
);
1060 blorp_clear_attachments(batch
, binding_table
,
1061 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
1062 pRects
[r
].baseArrayLayer
,
1063 pRects
[r
].layerCount
,
1065 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1066 true, clear_color
, false, 0.0f
, 0, 0);
1071 clear_depth_stencil_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1072 struct blorp_batch
*batch
,
1073 const VkClearAttachment
*attachment
,
1074 uint32_t rectCount
, const VkClearRect
*pRects
)
1076 static const union isl_color_value color_value
= { .u32
= { 0, } };
1077 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1078 const uint32_t att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1080 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1083 struct anv_render_pass_attachment
*pass_att
=
1084 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
1086 bool clear_depth
= attachment
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
1087 bool clear_stencil
= attachment
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
1089 enum isl_format depth_format
= ISL_FORMAT_UNSUPPORTED
;
1091 depth_format
= anv_get_isl_format(&cmd_buffer
->device
->info
,
1093 VK_IMAGE_ASPECT_DEPTH_BIT
,
1094 VK_IMAGE_TILING_OPTIMAL
);
1097 uint32_t binding_table
;
1099 binding_table_for_surface_state(cmd_buffer
,
1100 cmd_buffer
->state
.null_surface_state
,
1102 if (result
!= VK_SUCCESS
)
1105 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1106 if (subpass
->view_mask
) {
1108 for_each_bit(view_idx
, subpass
->view_mask
) {
1109 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1110 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1111 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1112 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1113 blorp_clear_attachments(batch
, binding_table
,
1114 depth_format
, pass_att
->samples
,
1117 offset
.x
+ extent
.width
,
1118 offset
.y
+ extent
.height
,
1120 clear_depth
, value
.depth
,
1121 clear_stencil
? 0xff : 0, value
.stencil
);
1127 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1128 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1129 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1130 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1131 assert(pRects
[r
].layerCount
!= VK_REMAINING_ARRAY_LAYERS
);
1132 blorp_clear_attachments(batch
, binding_table
,
1133 depth_format
, pass_att
->samples
,
1134 pRects
[r
].baseArrayLayer
,
1135 pRects
[r
].layerCount
,
1137 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1139 clear_depth
, value
.depth
,
1140 clear_stencil
? 0xff : 0, value
.stencil
);
1144 void anv_CmdClearAttachments(
1145 VkCommandBuffer commandBuffer
,
1146 uint32_t attachmentCount
,
1147 const VkClearAttachment
* pAttachments
,
1149 const VkClearRect
* pRects
)
1151 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1153 /* Because this gets called within a render pass, we tell blorp not to
1154 * trash our depth and stencil buffers.
1156 struct blorp_batch batch
;
1157 enum blorp_batch_flags flags
= BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
;
1158 if (cmd_buffer
->state
.conditional_render_enabled
) {
1159 anv_cmd_emit_conditional_render_predicate(cmd_buffer
);
1160 flags
|= BLORP_BATCH_PREDICATE_ENABLE
;
1162 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, flags
);
1164 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1165 if (pAttachments
[a
].aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1166 assert(pAttachments
[a
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1167 clear_color_attachment(cmd_buffer
, &batch
,
1171 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1177 blorp_batch_finish(&batch
);
1180 enum subpass_stage
{
1183 SUBPASS_STAGE_RESOLVE
,
1187 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1188 const struct anv_image
*src_image
,
1189 enum isl_aux_usage src_aux_usage
,
1190 uint32_t src_level
, uint32_t src_base_layer
,
1191 const struct anv_image
*dst_image
,
1192 enum isl_aux_usage dst_aux_usage
,
1193 uint32_t dst_level
, uint32_t dst_base_layer
,
1194 VkImageAspectFlagBits aspect
,
1195 uint32_t src_x
, uint32_t src_y
,
1196 uint32_t dst_x
, uint32_t dst_y
,
1197 uint32_t width
, uint32_t height
,
1198 uint32_t layer_count
,
1199 enum blorp_filter filter
)
1201 struct blorp_batch batch
;
1202 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1204 assert(src_image
->type
== VK_IMAGE_TYPE_2D
);
1205 assert(src_image
->samples
> 1);
1206 assert(dst_image
->type
== VK_IMAGE_TYPE_2D
);
1207 assert(dst_image
->samples
== 1);
1208 assert(src_image
->n_planes
== dst_image
->n_planes
);
1209 assert(!src_image
->format
->can_ycbcr
);
1210 assert(!dst_image
->format
->can_ycbcr
);
1212 struct blorp_surf src_surf
, dst_surf
;
1213 get_blorp_surf_for_anv_image(cmd_buffer
->device
, src_image
, aspect
,
1214 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1215 src_aux_usage
, &src_surf
);
1216 if (src_aux_usage
== ISL_AUX_USAGE_MCS
) {
1217 src_surf
.clear_color_addr
= anv_to_blorp_address(
1218 anv_image_get_clear_color_addr(cmd_buffer
->device
, src_image
,
1219 VK_IMAGE_ASPECT_COLOR_BIT
));
1221 get_blorp_surf_for_anv_image(cmd_buffer
->device
, dst_image
, aspect
,
1222 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1223 dst_aux_usage
, &dst_surf
);
1224 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
1225 aspect
, dst_aux_usage
,
1226 dst_level
, dst_base_layer
, layer_count
);
1228 if (filter
== BLORP_FILTER_NONE
) {
1229 /* If no explicit filter is provided, then it's implied by the type of
1232 if ((src_surf
.surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) ||
1233 (src_surf
.surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) ||
1234 isl_format_has_int_channel(src_surf
.surf
->format
)) {
1235 filter
= BLORP_FILTER_SAMPLE_0
;
1237 filter
= BLORP_FILTER_AVERAGE
;
1241 for (uint32_t l
= 0; l
< layer_count
; l
++) {
1243 &src_surf
, src_level
, src_base_layer
+ l
,
1244 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1245 &dst_surf
, dst_level
, dst_base_layer
+ l
,
1246 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1247 src_x
, src_y
, src_x
+ width
, src_y
+ height
,
1248 dst_x
, dst_y
, dst_x
+ width
, dst_y
+ height
,
1249 filter
, false, false);
1252 blorp_batch_finish(&batch
);
1255 void anv_CmdResolveImage(
1256 VkCommandBuffer commandBuffer
,
1258 VkImageLayout srcImageLayout
,
1260 VkImageLayout dstImageLayout
,
1261 uint32_t regionCount
,
1262 const VkImageResolve
* pRegions
)
1264 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1265 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
1266 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
1268 assert(!src_image
->format
->can_ycbcr
);
1270 for (uint32_t r
= 0; r
< regionCount
; r
++) {
1271 assert(pRegions
[r
].srcSubresource
.aspectMask
==
1272 pRegions
[r
].dstSubresource
.aspectMask
);
1273 assert(anv_get_layerCount(src_image
, &pRegions
[r
].srcSubresource
) ==
1274 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
));
1276 const uint32_t layer_count
=
1277 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
);
1279 VkImageAspectFlags src_mask
= pRegions
[r
].srcSubresource
.aspectMask
;
1280 VkImageAspectFlags dst_mask
= pRegions
[r
].dstSubresource
.aspectMask
;
1282 assert(anv_image_aspects_compatible(src_mask
, dst_mask
));
1284 uint32_t aspect_bit
;
1285 anv_foreach_image_aspect_bit(aspect_bit
, src_image
,
1286 pRegions
[r
].srcSubresource
.aspectMask
) {
1287 enum isl_aux_usage src_aux_usage
=
1288 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_image
,
1289 (1 << aspect_bit
), srcImageLayout
);
1290 enum isl_aux_usage dst_aux_usage
=
1291 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_image
,
1292 (1 << aspect_bit
), dstImageLayout
);
1294 anv_image_msaa_resolve(cmd_buffer
,
1295 src_image
, src_aux_usage
,
1296 pRegions
[r
].srcSubresource
.mipLevel
,
1297 pRegions
[r
].srcSubresource
.baseArrayLayer
,
1298 dst_image
, dst_aux_usage
,
1299 pRegions
[r
].dstSubresource
.mipLevel
,
1300 pRegions
[r
].dstSubresource
.baseArrayLayer
,
1302 pRegions
[r
].srcOffset
.x
,
1303 pRegions
[r
].srcOffset
.y
,
1304 pRegions
[r
].dstOffset
.x
,
1305 pRegions
[r
].dstOffset
.y
,
1306 pRegions
[r
].extent
.width
,
1307 pRegions
[r
].extent
.height
,
1308 layer_count
, BLORP_FILTER_NONE
);
1313 static enum isl_aux_usage
1314 fast_clear_aux_usage(const struct anv_image
*image
,
1315 VkImageAspectFlagBits aspect
)
1317 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1318 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
1319 return ISL_AUX_USAGE_CCS_D
;
1321 return image
->planes
[plane
].aux_usage
;
1325 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
1326 const struct anv_image
*image
,
1327 uint32_t base_level
, uint32_t level_count
,
1328 uint32_t base_layer
, uint32_t layer_count
)
1330 struct blorp_batch batch
;
1331 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1333 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
&& image
->n_planes
== 1);
1335 struct blorp_surf surf
;
1336 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1337 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1338 VK_IMAGE_LAYOUT_GENERAL
,
1339 ISL_AUX_USAGE_NONE
, &surf
);
1340 assert(surf
.aux_usage
== ISL_AUX_USAGE_NONE
);
1342 struct blorp_surf shadow_surf
= {
1343 .surf
= &image
->planes
[0].shadow_surface
.isl
,
1345 .buffer
= image
->planes
[0].address
.bo
,
1346 .offset
= image
->planes
[0].address
.offset
+
1347 image
->planes
[0].shadow_surface
.offset
,
1348 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
,
1349 image
->planes
[0].address
.bo
),
1353 for (uint32_t l
= 0; l
< level_count
; l
++) {
1354 const uint32_t level
= base_level
+ l
;
1356 const VkExtent3D extent
= {
1357 .width
= anv_minify(image
->extent
.width
, level
),
1358 .height
= anv_minify(image
->extent
.height
, level
),
1359 .depth
= anv_minify(image
->extent
.depth
, level
),
1362 if (image
->type
== VK_IMAGE_TYPE_3D
)
1363 layer_count
= extent
.depth
;
1365 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1366 const uint32_t layer
= base_layer
+ a
;
1368 blorp_copy(&batch
, &surf
, level
, layer
,
1369 &shadow_surf
, level
, layer
,
1370 0, 0, 0, 0, extent
.width
, extent
.height
);
1374 blorp_batch_finish(&batch
);
1378 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
1379 const struct anv_image
*image
,
1380 VkImageAspectFlagBits aspect
,
1381 enum isl_aux_usage aux_usage
,
1382 enum isl_format format
, struct isl_swizzle swizzle
,
1383 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
1384 VkRect2D area
, union isl_color_value clear_color
)
1386 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1388 /* We don't support planar images with multisampling yet */
1389 assert(image
->n_planes
== 1);
1391 struct blorp_batch batch
;
1392 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1394 struct blorp_surf surf
;
1395 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1396 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1398 anv_cmd_buffer_mark_image_written(cmd_buffer
, image
, aspect
, aux_usage
,
1399 level
, base_layer
, layer_count
);
1401 blorp_clear(&batch
, &surf
, format
, anv_swizzle_for_render(swizzle
),
1402 level
, base_layer
, layer_count
,
1403 area
.offset
.x
, area
.offset
.y
,
1404 area
.offset
.x
+ area
.extent
.width
,
1405 area
.offset
.y
+ area
.extent
.height
,
1408 blorp_batch_finish(&batch
);
1412 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
1413 const struct anv_image
*image
,
1414 VkImageAspectFlags aspects
,
1415 enum isl_aux_usage depth_aux_usage
,
1417 uint32_t base_layer
, uint32_t layer_count
,
1419 float depth_value
, uint8_t stencil_value
)
1421 assert(image
->aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1422 VK_IMAGE_ASPECT_STENCIL_BIT
));
1424 struct blorp_batch batch
;
1425 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1427 struct blorp_surf depth
= {};
1428 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1429 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1430 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1431 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1432 depth_aux_usage
, &depth
);
1433 depth
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1436 struct blorp_surf stencil
= {};
1437 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1438 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1439 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
1440 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1441 ISL_AUX_USAGE_NONE
, &stencil
);
1444 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
1445 level
, base_layer
, layer_count
,
1446 area
.offset
.x
, area
.offset
.y
,
1447 area
.offset
.x
+ area
.extent
.width
,
1448 area
.offset
.y
+ area
.extent
.height
,
1449 aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
,
1451 (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) ? 0xff : 0,
1454 blorp_batch_finish(&batch
);
1458 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
1459 const struct anv_image
*image
,
1460 VkImageAspectFlagBits aspect
, uint32_t level
,
1461 uint32_t base_layer
, uint32_t layer_count
,
1462 enum isl_aux_op hiz_op
)
1464 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
1465 assert(base_layer
+ layer_count
<= anv_image_aux_layers(image
, aspect
, level
));
1466 assert(anv_image_aspect_to_plane(image
->aspects
,
1467 VK_IMAGE_ASPECT_DEPTH_BIT
) == 0);
1469 struct blorp_batch batch
;
1470 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1472 struct blorp_surf surf
;
1473 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1474 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1475 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1476 ISL_AUX_USAGE_HIZ
, &surf
);
1477 surf
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1479 blorp_hiz_op(&batch
, &surf
, level
, base_layer
, layer_count
, hiz_op
);
1481 blorp_batch_finish(&batch
);
1485 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
1486 const struct anv_image
*image
,
1487 VkImageAspectFlags aspects
,
1489 uint32_t base_layer
, uint32_t layer_count
,
1490 VkRect2D area
, uint8_t stencil_value
)
1492 assert(image
->aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1493 VK_IMAGE_ASPECT_STENCIL_BIT
));
1495 struct blorp_batch batch
;
1496 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1498 struct blorp_surf depth
= {};
1499 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1500 assert(base_layer
+ layer_count
<=
1501 anv_image_aux_layers(image
, VK_IMAGE_ASPECT_DEPTH_BIT
, level
));
1502 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1503 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1504 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1505 ISL_AUX_USAGE_HIZ
, &depth
);
1506 depth
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1509 struct blorp_surf stencil
= {};
1510 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1511 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1512 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
1513 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1514 ISL_AUX_USAGE_NONE
, &stencil
);
1517 /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
1519 * "The following is required when performing a depth buffer clear with
1520 * using the WM_STATE or 3DSTATE_WM:
1522 * * If other rendering operations have preceded this clear, a
1523 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1524 * enabled must be issued before the rectangle primitive used for
1525 * the depth buffer clear operation.
1528 * Even though the PRM only says that this is required if using 3DSTATE_WM
1529 * and a 3DPRIMITIVE, the GPU appears to also need this to avoid occasional
1530 * hangs when doing a clear with WM_HZ_OP.
1532 cmd_buffer
->state
.pending_pipe_bits
|=
1533 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
| ANV_PIPE_DEPTH_STALL_BIT
;
1535 blorp_hiz_clear_depth_stencil(&batch
, &depth
, &stencil
,
1536 level
, base_layer
, layer_count
,
1537 area
.offset
.x
, area
.offset
.y
,
1538 area
.offset
.x
+ area
.extent
.width
,
1539 area
.offset
.y
+ area
.extent
.height
,
1540 aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
,
1542 aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
,
1545 blorp_batch_finish(&batch
);
1547 /* From the SKL PRM, Depth Buffer Clear:
1549 * "Depth Buffer Clear Workaround
1551 * Depth buffer clear pass using any of the methods (WM_STATE,
1552 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
1553 * command with DEPTH_STALL bit and Depth FLUSH bits “set” before
1554 * starting to render. DepthStall and DepthFlush are not needed between
1555 * consecutive depth clear passes nor is it required if the depth-clear
1556 * pass was done with “full_surf_clear” bit set in the
1557 * 3DSTATE_WM_HZ_OP."
1559 * Even though the PRM provides a bunch of conditions under which this is
1560 * supposedly unnecessary, we choose to perform the flush unconditionally
1563 cmd_buffer
->state
.pending_pipe_bits
|=
1564 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
| ANV_PIPE_DEPTH_STALL_BIT
;
1568 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
1569 const struct anv_image
*image
,
1570 enum isl_format format
,
1571 VkImageAspectFlagBits aspect
,
1572 uint32_t base_layer
, uint32_t layer_count
,
1573 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
1576 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1577 assert(image
->samples
> 1);
1578 assert(base_layer
+ layer_count
<= anv_image_aux_layers(image
, aspect
, 0));
1580 /* Multisampling with multi-planar formats is not supported */
1581 assert(image
->n_planes
== 1);
1583 struct blorp_batch batch
;
1584 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1585 predicate
? BLORP_BATCH_PREDICATE_ENABLE
: 0);
1587 struct blorp_surf surf
;
1588 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1589 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1590 ISL_AUX_USAGE_MCS
, &surf
);
1592 /* Blorp will store the clear color for us if we provide the clear color
1593 * address and we are doing a fast clear. So we save the clear value into
1594 * the blorp surface. However, in some situations we want to do a fast clear
1595 * without changing the clear value stored in the state buffer. For those
1596 * cases, we set the clear color address pointer to NULL, so blorp will not
1597 * try to store a garbage color.
1599 if (mcs_op
== ISL_AUX_OP_FAST_CLEAR
) {
1601 surf
.clear_color
= *clear_value
;
1603 surf
.clear_color_addr
.buffer
= NULL
;
1606 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1608 * "After Render target fast clear, pipe-control with color cache
1609 * write-flush must be issued before sending any DRAW commands on
1610 * that render target."
1612 * This comment is a bit cryptic and doesn't really tell you what's going
1613 * or what's really needed. It appears that fast clear ops are not
1614 * properly synchronized with other drawing. This means that we cannot
1615 * have a fast clear operation in the pipe at the same time as other
1616 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1617 * that the contents of the previous draw hit the render target before we
1618 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1619 * that it is completed before any additional drawing occurs.
1621 cmd_buffer
->state
.pending_pipe_bits
|=
1622 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1625 case ISL_AUX_OP_FAST_CLEAR
:
1626 blorp_fast_clear(&batch
, &surf
, format
,
1627 0, base_layer
, layer_count
,
1628 0, 0, image
->extent
.width
, image
->extent
.height
);
1630 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1631 blorp_mcs_partial_resolve(&batch
, &surf
, format
,
1632 base_layer
, layer_count
);
1634 case ISL_AUX_OP_FULL_RESOLVE
:
1635 case ISL_AUX_OP_AMBIGUATE
:
1637 unreachable("Unsupported MCS operation");
1640 cmd_buffer
->state
.pending_pipe_bits
|=
1641 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1643 blorp_batch_finish(&batch
);
1647 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
1648 const struct anv_image
*image
,
1649 enum isl_format format
,
1650 VkImageAspectFlagBits aspect
, uint32_t level
,
1651 uint32_t base_layer
, uint32_t layer_count
,
1652 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
1655 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1656 assert(image
->samples
== 1);
1657 assert(level
< anv_image_aux_levels(image
, aspect
));
1658 /* Multi-LOD YcBcR is not allowed */
1659 assert(image
->n_planes
== 1 || level
== 0);
1660 assert(base_layer
+ layer_count
<=
1661 anv_image_aux_layers(image
, aspect
, level
));
1663 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1664 uint32_t width_div
= image
->format
->planes
[plane
].denominator_scales
[0];
1665 uint32_t height_div
= image
->format
->planes
[plane
].denominator_scales
[1];
1666 uint32_t level_width
= anv_minify(image
->extent
.width
, level
) / width_div
;
1667 uint32_t level_height
= anv_minify(image
->extent
.height
, level
) / height_div
;
1669 struct blorp_batch batch
;
1670 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1671 predicate
? BLORP_BATCH_PREDICATE_ENABLE
: 0);
1673 struct blorp_surf surf
;
1674 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1675 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1676 fast_clear_aux_usage(image
, aspect
),
1679 /* Blorp will store the clear color for us if we provide the clear color
1680 * address and we are doing a fast clear. So we save the clear value into
1681 * the blorp surface. However, in some situations we want to do a fast clear
1682 * without changing the clear value stored in the state buffer. For those
1683 * cases, we set the clear color address pointer to NULL, so blorp will not
1684 * try to store a garbage color.
1686 if (ccs_op
== ISL_AUX_OP_FAST_CLEAR
) {
1688 surf
.clear_color
= *clear_value
;
1690 surf
.clear_color_addr
.buffer
= NULL
;
1693 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1695 * "After Render target fast clear, pipe-control with color cache
1696 * write-flush must be issued before sending any DRAW commands on
1697 * that render target."
1699 * This comment is a bit cryptic and doesn't really tell you what's going
1700 * or what's really needed. It appears that fast clear ops are not
1701 * properly synchronized with other drawing. This means that we cannot
1702 * have a fast clear operation in the pipe at the same time as other
1703 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1704 * that the contents of the previous draw hit the render target before we
1705 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1706 * that it is completed before any additional drawing occurs.
1708 cmd_buffer
->state
.pending_pipe_bits
|=
1709 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1712 case ISL_AUX_OP_FAST_CLEAR
:
1713 blorp_fast_clear(&batch
, &surf
, format
,
1714 level
, base_layer
, layer_count
,
1715 0, 0, level_width
, level_height
);
1717 case ISL_AUX_OP_FULL_RESOLVE
:
1718 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1719 blorp_ccs_resolve(&batch
, &surf
, level
, base_layer
, layer_count
,
1722 case ISL_AUX_OP_AMBIGUATE
:
1723 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1724 const uint32_t layer
= base_layer
+ a
;
1725 blorp_ccs_ambiguate(&batch
, &surf
, level
, layer
);
1729 unreachable("Unsupported CCS operation");
1732 cmd_buffer
->state
.pending_pipe_bits
|=
1733 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1735 blorp_batch_finish(&batch
);