2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
27 lookup_blorp_shader(struct blorp_context
*blorp
,
28 const void *key
, uint32_t key_size
,
29 uint32_t *kernel_out
, void *prog_data_out
)
31 struct anv_device
*device
= blorp
->driver_ctx
;
33 /* The blorp cache must be a real cache */
34 assert(device
->blorp_shader_cache
.cache
);
36 struct anv_shader_bin
*bin
=
37 anv_pipeline_cache_search(&device
->blorp_shader_cache
, key
, key_size
);
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
44 anv_shader_bin_unref(device
, bin
);
46 *kernel_out
= bin
->kernel
.offset
;
47 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
53 upload_blorp_shader(struct blorp_context
*blorp
,
54 const void *key
, uint32_t key_size
,
55 const void *kernel
, uint32_t kernel_size
,
56 const struct brw_stage_prog_data
*prog_data
,
57 uint32_t prog_data_size
,
58 uint32_t *kernel_out
, void *prog_data_out
)
60 struct anv_device
*device
= blorp
->driver_ctx
;
62 /* The blorp cache must be a real cache */
63 assert(device
->blorp_shader_cache
.cache
);
65 struct anv_pipeline_bind_map bind_map
= {
70 struct anv_shader_bin
*bin
=
71 anv_pipeline_cache_upload_kernel(&device
->blorp_shader_cache
,
72 key
, key_size
, kernel
, kernel_size
,
73 prog_data
, prog_data_size
, &bind_map
);
75 /* The cache already has a reference and it's not going anywhere so there
76 * is no need to hold a second reference.
78 anv_shader_bin_unref(device
, bin
);
80 *kernel_out
= bin
->kernel
.offset
;
81 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
85 anv_device_init_blorp(struct anv_device
*device
)
87 anv_pipeline_cache_init(&device
->blorp_shader_cache
, device
, true);
88 blorp_init(&device
->blorp
, device
, &device
->isl_dev
);
89 device
->blorp
.compiler
= device
->instance
->physicalDevice
.compiler
;
90 device
->blorp
.mocs
.tex
= device
->default_mocs
;
91 device
->blorp
.mocs
.rb
= device
->default_mocs
;
92 device
->blorp
.mocs
.vb
= device
->default_mocs
;
93 device
->blorp
.lookup_shader
= lookup_blorp_shader
;
94 device
->blorp
.upload_shader
= upload_blorp_shader
;
95 switch (device
->info
.gen
) {
97 if (device
->info
.is_haswell
) {
98 device
->blorp
.exec
= gen75_blorp_exec
;
100 device
->blorp
.exec
= gen7_blorp_exec
;
104 device
->blorp
.exec
= gen8_blorp_exec
;
107 device
->blorp
.exec
= gen9_blorp_exec
;
110 unreachable("Unknown hardware generation");
115 anv_device_finish_blorp(struct anv_device
*device
)
117 blorp_finish(&device
->blorp
);
118 anv_pipeline_cache_finish(&device
->blorp_shader_cache
);
122 get_blorp_surf_for_anv_buffer(struct anv_device
*device
,
123 struct anv_buffer
*buffer
, uint64_t offset
,
124 uint32_t width
, uint32_t height
,
125 uint32_t row_pitch
, enum isl_format format
,
126 struct blorp_surf
*blorp_surf
,
127 struct isl_surf
*isl_surf
)
129 const struct isl_format_layout
*fmtl
=
130 isl_format_get_layout(format
);
132 /* ASTC is the only format which doesn't support linear layouts.
133 * Create an equivalently sized surface with ISL to get around this.
135 if (fmtl
->txc
== ISL_TXC_ASTC
) {
136 /* Use an equivalently sized format */
137 format
= ISL_FORMAT_R32G32B32A32_UINT
;
138 assert(fmtl
->bpb
== isl_format_get_layout(format
)->bpb
);
140 /* Shrink the dimensions for the new format */
141 width
= DIV_ROUND_UP(width
, fmtl
->bw
);
142 height
= DIV_ROUND_UP(height
, fmtl
->bh
);
145 *blorp_surf
= (struct blorp_surf
) {
148 .buffer
= buffer
->bo
,
149 .offset
= buffer
->offset
+ offset
,
153 isl_surf_init(&device
->isl_dev
, isl_surf
,
154 .dim
= ISL_SURF_DIM_2D
,
162 .min_pitch
= row_pitch
,
163 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
164 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
165 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
166 assert(isl_surf
->row_pitch
== row_pitch
);
170 get_blorp_surf_for_anv_image(const struct anv_image
*image
,
171 VkImageAspectFlags aspect
,
172 enum isl_aux_usage aux_usage
,
173 struct blorp_surf
*blorp_surf
)
175 if (aspect
== VK_IMAGE_ASPECT_STENCIL_BIT
||
176 aux_usage
== ISL_AUX_USAGE_HIZ
)
177 aux_usage
= ISL_AUX_USAGE_NONE
;
179 const struct anv_surface
*surface
=
180 anv_image_get_surface_for_aspect_mask(image
, aspect
);
182 *blorp_surf
= (struct blorp_surf
) {
183 .surf
= &surface
->isl
,
186 .offset
= image
->offset
+ surface
->offset
,
190 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
191 blorp_surf
->aux_surf
= &image
->aux_surface
.isl
,
192 blorp_surf
->aux_addr
= (struct blorp_address
) {
194 .offset
= image
->offset
+ image
->aux_surface
.offset
,
196 blorp_surf
->aux_usage
= aux_usage
;
200 void anv_CmdCopyImage(
201 VkCommandBuffer commandBuffer
,
203 VkImageLayout srcImageLayout
,
205 VkImageLayout dstImageLayout
,
206 uint32_t regionCount
,
207 const VkImageCopy
* pRegions
)
209 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
210 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
211 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
213 struct blorp_batch batch
;
214 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
216 for (unsigned r
= 0; r
< regionCount
; r
++) {
217 VkOffset3D srcOffset
=
218 anv_sanitize_image_offset(src_image
->type
, pRegions
[r
].srcOffset
);
219 VkOffset3D dstOffset
=
220 anv_sanitize_image_offset(dst_image
->type
, pRegions
[r
].dstOffset
);
222 anv_sanitize_image_extent(src_image
->type
, pRegions
[r
].extent
);
224 unsigned dst_base_layer
, layer_count
;
225 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
226 dst_base_layer
= pRegions
[r
].dstOffset
.z
;
227 layer_count
= pRegions
[r
].extent
.depth
;
229 dst_base_layer
= pRegions
[r
].dstSubresource
.baseArrayLayer
;
230 layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
233 unsigned src_base_layer
;
234 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
235 src_base_layer
= pRegions
[r
].srcOffset
.z
;
237 src_base_layer
= pRegions
[r
].srcSubresource
.baseArrayLayer
;
238 assert(pRegions
[r
].srcSubresource
.layerCount
== layer_count
);
241 assert(pRegions
[r
].srcSubresource
.aspectMask
==
242 pRegions
[r
].dstSubresource
.aspectMask
);
245 for_each_bit(a
, pRegions
[r
].dstSubresource
.aspectMask
) {
246 VkImageAspectFlagBits aspect
= (1 << a
);
248 struct blorp_surf src_surf
, dst_surf
;
249 get_blorp_surf_for_anv_image(src_image
, aspect
, src_image
->aux_usage
,
251 get_blorp_surf_for_anv_image(dst_image
, aspect
, dst_image
->aux_usage
,
254 for (unsigned i
= 0; i
< layer_count
; i
++) {
255 blorp_copy(&batch
, &src_surf
, pRegions
[r
].srcSubresource
.mipLevel
,
257 &dst_surf
, pRegions
[r
].dstSubresource
.mipLevel
,
259 srcOffset
.x
, srcOffset
.y
,
260 dstOffset
.x
, dstOffset
.y
,
261 extent
.width
, extent
.height
);
266 blorp_batch_finish(&batch
);
270 copy_buffer_to_image(struct anv_cmd_buffer
*cmd_buffer
,
271 struct anv_buffer
*anv_buffer
,
272 struct anv_image
*anv_image
,
273 uint32_t regionCount
,
274 const VkBufferImageCopy
* pRegions
,
275 bool buffer_to_image
)
277 struct blorp_batch batch
;
278 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
281 struct blorp_surf surf
;
284 } image
, buffer
, *src
, *dst
;
287 buffer
.offset
= (VkOffset3D
) { 0, 0, 0 };
289 if (buffer_to_image
) {
297 for (unsigned r
= 0; r
< regionCount
; r
++) {
298 const VkImageAspectFlags aspect
= pRegions
[r
].imageSubresource
.aspectMask
;
300 get_blorp_surf_for_anv_image(anv_image
, aspect
, anv_image
->aux_usage
,
303 anv_sanitize_image_offset(anv_image
->type
, pRegions
[r
].imageOffset
);
304 image
.level
= pRegions
[r
].imageSubresource
.mipLevel
;
307 anv_sanitize_image_extent(anv_image
->type
, pRegions
[r
].imageExtent
);
308 if (anv_image
->type
!= VK_IMAGE_TYPE_3D
) {
309 image
.offset
.z
= pRegions
[r
].imageSubresource
.baseArrayLayer
;
310 extent
.depth
= pRegions
[r
].imageSubresource
.layerCount
;
313 const enum isl_format buffer_format
=
314 anv_get_isl_format(&cmd_buffer
->device
->info
, anv_image
->vk_format
,
315 aspect
, VK_IMAGE_TILING_LINEAR
);
317 const VkExtent3D bufferImageExtent
= {
318 .width
= pRegions
[r
].bufferRowLength
?
319 pRegions
[r
].bufferRowLength
: extent
.width
,
320 .height
= pRegions
[r
].bufferImageHeight
?
321 pRegions
[r
].bufferImageHeight
: extent
.height
,
324 const struct isl_format_layout
*buffer_fmtl
=
325 isl_format_get_layout(buffer_format
);
327 const uint32_t buffer_row_pitch
=
328 DIV_ROUND_UP(bufferImageExtent
.width
, buffer_fmtl
->bw
) *
329 (buffer_fmtl
->bpb
/ 8);
331 const uint32_t buffer_layer_stride
=
332 DIV_ROUND_UP(bufferImageExtent
.height
, buffer_fmtl
->bh
) *
335 struct isl_surf buffer_isl_surf
;
336 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
337 anv_buffer
, pRegions
[r
].bufferOffset
,
338 extent
.width
, extent
.height
,
339 buffer_row_pitch
, buffer_format
,
340 &buffer
.surf
, &buffer_isl_surf
);
342 for (unsigned z
= 0; z
< extent
.depth
; z
++) {
343 blorp_copy(&batch
, &src
->surf
, src
->level
, src
->offset
.z
,
344 &dst
->surf
, dst
->level
, dst
->offset
.z
,
345 src
->offset
.x
, src
->offset
.y
, dst
->offset
.x
, dst
->offset
.y
,
346 extent
.width
, extent
.height
);
349 buffer
.surf
.addr
.offset
+= buffer_layer_stride
;
353 blorp_batch_finish(&batch
);
356 void anv_CmdCopyBufferToImage(
357 VkCommandBuffer commandBuffer
,
360 VkImageLayout dstImageLayout
,
361 uint32_t regionCount
,
362 const VkBufferImageCopy
* pRegions
)
364 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
365 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
366 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
368 copy_buffer_to_image(cmd_buffer
, src_buffer
, dst_image
,
369 regionCount
, pRegions
, true);
372 void anv_CmdCopyImageToBuffer(
373 VkCommandBuffer commandBuffer
,
375 VkImageLayout srcImageLayout
,
377 uint32_t regionCount
,
378 const VkBufferImageCopy
* pRegions
)
380 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
381 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
382 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
384 copy_buffer_to_image(cmd_buffer
, dst_buffer
, src_image
,
385 regionCount
, pRegions
, false);
389 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
393 unsigned tmp
= *src0
;
400 unsigned tmp
= *dst0
;
409 void anv_CmdBlitImage(
410 VkCommandBuffer commandBuffer
,
412 VkImageLayout srcImageLayout
,
414 VkImageLayout dstImageLayout
,
415 uint32_t regionCount
,
416 const VkImageBlit
* pRegions
,
420 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
421 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
422 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
424 struct blorp_surf src
, dst
;
428 case VK_FILTER_NEAREST
:
429 gl_filter
= 0x2600; /* GL_NEAREST */
431 case VK_FILTER_LINEAR
:
432 gl_filter
= 0x2601; /* GL_LINEAR */
435 unreachable("Invalid filter");
438 struct blorp_batch batch
;
439 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
441 for (unsigned r
= 0; r
< regionCount
; r
++) {
442 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
443 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
445 get_blorp_surf_for_anv_image(src_image
, src_res
->aspectMask
,
446 src_image
->aux_usage
, &src
);
447 get_blorp_surf_for_anv_image(dst_image
, dst_res
->aspectMask
,
448 dst_image
->aux_usage
, &dst
);
450 struct anv_format src_format
=
451 anv_get_format(&cmd_buffer
->device
->info
, src_image
->vk_format
,
452 src_res
->aspectMask
, src_image
->tiling
);
453 struct anv_format dst_format
=
454 anv_get_format(&cmd_buffer
->device
->info
, dst_image
->vk_format
,
455 dst_res
->aspectMask
, dst_image
->tiling
);
457 unsigned dst_start
, dst_end
;
458 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
459 assert(dst_res
->baseArrayLayer
== 0);
460 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
461 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
463 dst_start
= dst_res
->baseArrayLayer
;
464 dst_end
= dst_start
+ dst_res
->layerCount
;
467 unsigned src_start
, src_end
;
468 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
469 assert(src_res
->baseArrayLayer
== 0);
470 src_start
= pRegions
[r
].srcOffsets
[0].z
;
471 src_end
= pRegions
[r
].srcOffsets
[1].z
;
473 src_start
= src_res
->baseArrayLayer
;
474 src_end
= src_start
+ src_res
->layerCount
;
477 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
478 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
479 (float)(dst_end
+ 1 - dst_start
);
486 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
487 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
488 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
489 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
490 bool flip_x
= flip_coords(&src_x0
, &src_x1
, &dst_x0
, &dst_x1
);
492 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
493 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
494 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
495 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
496 bool flip_y
= flip_coords(&src_y0
, &src_y1
, &dst_y0
, &dst_y1
);
498 const unsigned num_layers
= dst_end
- dst_start
;
499 for (unsigned i
= 0; i
< num_layers
; i
++) {
500 unsigned dst_z
= dst_start
+ i
;
501 unsigned src_z
= src_start
+ i
* src_z_step
;
503 blorp_blit(&batch
, &src
, src_res
->mipLevel
, src_z
,
504 src_format
.isl_format
, src_format
.swizzle
,
505 &dst
, dst_res
->mipLevel
, dst_z
,
506 dst_format
.isl_format
, dst_format
.swizzle
,
507 src_x0
, src_y0
, src_x1
, src_y1
,
508 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
509 gl_filter
, flip_x
, flip_y
);
514 blorp_batch_finish(&batch
);
517 static enum isl_format
518 isl_format_for_size(unsigned size_B
)
521 case 1: return ISL_FORMAT_R8_UINT
;
522 case 2: return ISL_FORMAT_R8G8_UINT
;
523 case 4: return ISL_FORMAT_R8G8B8A8_UINT
;
524 case 8: return ISL_FORMAT_R16G16B16A16_UINT
;
525 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
527 unreachable("Not a power-of-two format size");
532 do_buffer_copy(struct blorp_batch
*batch
,
533 struct anv_bo
*src
, uint64_t src_offset
,
534 struct anv_bo
*dst
, uint64_t dst_offset
,
535 int width
, int height
, int block_size
)
537 struct anv_device
*device
= batch
->blorp
->driver_ctx
;
539 /* The actual format we pick doesn't matter as blorp will throw it away.
540 * The only thing that actually matters is the size.
542 enum isl_format format
= isl_format_for_size(block_size
);
544 struct isl_surf surf
;
545 isl_surf_init(&device
->isl_dev
, &surf
,
546 .dim
= ISL_SURF_DIM_2D
,
554 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
555 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
556 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
557 assert(surf
.row_pitch
== width
* block_size
);
559 struct blorp_surf src_blorp_surf
= {
563 .offset
= src_offset
,
567 struct blorp_surf dst_blorp_surf
= {
571 .offset
= dst_offset
,
575 blorp_copy(batch
, &src_blorp_surf
, 0, 0, &dst_blorp_surf
, 0, 0,
576 0, 0, 0, 0, width
, height
);
580 * Returns the greatest common divisor of a and b that is a power of two.
582 static inline uint64_t
583 gcd_pow2_u64(uint64_t a
, uint64_t b
)
585 assert(a
> 0 || b
> 0);
587 unsigned a_log2
= ffsll(a
) - 1;
588 unsigned b_log2
= ffsll(b
) - 1;
590 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
591 * case, the MIN2() will take the other one. If both are 0 then we will
592 * hit the assert above.
594 return 1 << MIN2(a_log2
, b_log2
);
597 /* This is maximum possible width/height our HW can handle */
598 #define MAX_SURFACE_DIM (1ull << 14)
600 void anv_CmdCopyBuffer(
601 VkCommandBuffer commandBuffer
,
604 uint32_t regionCount
,
605 const VkBufferCopy
* pRegions
)
607 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
608 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
609 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
611 struct blorp_batch batch
;
612 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
614 for (unsigned r
= 0; r
< regionCount
; r
++) {
615 uint64_t src_offset
= src_buffer
->offset
+ pRegions
[r
].srcOffset
;
616 uint64_t dst_offset
= dst_buffer
->offset
+ pRegions
[r
].dstOffset
;
617 uint64_t copy_size
= pRegions
[r
].size
;
619 /* First, we compute the biggest format that can be used with the
620 * given offsets and size.
623 bs
= gcd_pow2_u64(bs
, src_offset
);
624 bs
= gcd_pow2_u64(bs
, dst_offset
);
625 bs
= gcd_pow2_u64(bs
, pRegions
[r
].size
);
627 /* First, we make a bunch of max-sized copies */
628 uint64_t max_copy_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
629 while (copy_size
>= max_copy_size
) {
630 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
631 dst_buffer
->bo
, dst_offset
,
632 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
, bs
);
633 copy_size
-= max_copy_size
;
634 src_offset
+= max_copy_size
;
635 dst_offset
+= max_copy_size
;
638 /* Now make a max-width copy */
639 uint64_t height
= copy_size
/ (MAX_SURFACE_DIM
* bs
);
640 assert(height
< MAX_SURFACE_DIM
);
642 uint64_t rect_copy_size
= height
* MAX_SURFACE_DIM
* bs
;
643 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
644 dst_buffer
->bo
, dst_offset
,
645 MAX_SURFACE_DIM
, height
, bs
);
646 copy_size
-= rect_copy_size
;
647 src_offset
+= rect_copy_size
;
648 dst_offset
+= rect_copy_size
;
651 /* Finally, make a small copy to finish it off */
652 if (copy_size
!= 0) {
653 do_buffer_copy(&batch
, src_buffer
->bo
, src_offset
,
654 dst_buffer
->bo
, dst_offset
,
655 copy_size
/ bs
, 1, bs
);
659 blorp_batch_finish(&batch
);
662 void anv_CmdUpdateBuffer(
663 VkCommandBuffer commandBuffer
,
665 VkDeviceSize dstOffset
,
666 VkDeviceSize dataSize
,
669 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
670 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
672 struct blorp_batch batch
;
673 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
675 /* We can't quite grab a full block because the state stream needs a
676 * little data at the top to build its linked list.
678 const uint32_t max_update_size
=
679 cmd_buffer
->device
->dynamic_state_block_pool
.block_size
- 64;
681 assert(max_update_size
< MAX_SURFACE_DIM
* 4);
684 const uint32_t copy_size
= MIN2(dataSize
, max_update_size
);
686 struct anv_state tmp_data
=
687 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, copy_size
, 64);
689 memcpy(tmp_data
.map
, pData
, copy_size
);
692 bs
= gcd_pow2_u64(bs
, dstOffset
);
693 bs
= gcd_pow2_u64(bs
, copy_size
);
695 do_buffer_copy(&batch
,
696 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
698 dst_buffer
->bo
, dst_buffer
->offset
+ dstOffset
,
699 copy_size
/ bs
, 1, bs
);
701 dataSize
-= copy_size
;
702 dstOffset
+= copy_size
;
703 pData
= (void *)pData
+ copy_size
;
706 blorp_batch_finish(&batch
);
709 void anv_CmdFillBuffer(
710 VkCommandBuffer commandBuffer
,
712 VkDeviceSize dstOffset
,
713 VkDeviceSize fillSize
,
716 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
717 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
718 struct blorp_surf surf
;
719 struct isl_surf isl_surf
;
721 struct blorp_batch batch
;
722 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
724 if (fillSize
== VK_WHOLE_SIZE
) {
725 fillSize
= dst_buffer
->size
- dstOffset
;
726 /* Make sure fillSize is a multiple of 4 */
730 /* First, we compute the biggest format that can be used with the
731 * given offsets and size.
734 bs
= gcd_pow2_u64(bs
, dstOffset
);
735 bs
= gcd_pow2_u64(bs
, fillSize
);
736 enum isl_format isl_format
= isl_format_for_size(bs
);
738 union isl_color_value color
= {
739 .u32
= { data
, data
, data
, data
},
742 const uint64_t max_fill_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
743 while (fillSize
>= max_fill_size
) {
744 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
745 dst_buffer
, dstOffset
,
746 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
747 MAX_SURFACE_DIM
* bs
, isl_format
,
750 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
751 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
753 fillSize
-= max_fill_size
;
754 dstOffset
+= max_fill_size
;
757 uint64_t height
= fillSize
/ (MAX_SURFACE_DIM
* bs
);
758 assert(height
< MAX_SURFACE_DIM
);
760 const uint64_t rect_fill_size
= height
* MAX_SURFACE_DIM
* bs
;
761 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
762 dst_buffer
, dstOffset
,
763 MAX_SURFACE_DIM
, height
,
764 MAX_SURFACE_DIM
* bs
, isl_format
,
767 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
768 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, height
,
770 fillSize
-= rect_fill_size
;
771 dstOffset
+= rect_fill_size
;
775 const uint32_t width
= fillSize
/ bs
;
776 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
777 dst_buffer
, dstOffset
,
779 width
* bs
, isl_format
,
782 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
783 0, 0, 1, 0, 0, width
, 1,
787 blorp_batch_finish(&batch
);
790 void anv_CmdClearColorImage(
791 VkCommandBuffer commandBuffer
,
793 VkImageLayout imageLayout
,
794 const VkClearColorValue
* pColor
,
796 const VkImageSubresourceRange
* pRanges
)
798 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
799 ANV_FROM_HANDLE(anv_image
, image
, _image
);
801 static const bool color_write_disable
[4] = { false, false, false, false };
803 struct blorp_batch batch
;
804 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
806 struct blorp_surf surf
;
807 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
808 image
->aux_usage
, &surf
);
810 for (unsigned r
= 0; r
< rangeCount
; r
++) {
811 if (pRanges
[r
].aspectMask
== 0)
814 assert(pRanges
[r
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
816 struct anv_format src_format
=
817 anv_get_format(&cmd_buffer
->device
->info
, image
->vk_format
,
818 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
820 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
821 unsigned layer_count
= pRanges
[r
].layerCount
;
823 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
824 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
825 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
826 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
828 if (image
->type
== VK_IMAGE_TYPE_3D
) {
830 layer_count
= anv_minify(image
->extent
.depth
, level
);
833 blorp_clear(&batch
, &surf
,
834 src_format
.isl_format
, src_format
.swizzle
,
835 level
, base_layer
, layer_count
,
836 0, 0, level_width
, level_height
,
837 vk_to_isl_color(*pColor
), color_write_disable
);
841 blorp_batch_finish(&batch
);
844 void anv_CmdClearDepthStencilImage(
845 VkCommandBuffer commandBuffer
,
847 VkImageLayout imageLayout
,
848 const VkClearDepthStencilValue
* pDepthStencil
,
850 const VkImageSubresourceRange
* pRanges
)
852 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
853 ANV_FROM_HANDLE(anv_image
, image
, image_h
);
855 struct blorp_batch batch
;
856 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
858 struct blorp_surf depth
, stencil
;
859 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
860 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
861 ISL_AUX_USAGE_NONE
, &depth
);
863 memset(&depth
, 0, sizeof(depth
));
866 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
867 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
868 ISL_AUX_USAGE_NONE
, &stencil
);
870 memset(&stencil
, 0, sizeof(stencil
));
873 for (unsigned r
= 0; r
< rangeCount
; r
++) {
874 if (pRanges
[r
].aspectMask
== 0)
877 bool clear_depth
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
878 bool clear_stencil
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
880 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
881 unsigned layer_count
= pRanges
[r
].layerCount
;
883 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
884 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
885 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
886 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
888 if (image
->type
== VK_IMAGE_TYPE_3D
)
889 layer_count
= anv_minify(image
->extent
.depth
, level
);
891 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
892 level
, base_layer
, layer_count
,
893 0, 0, level_width
, level_height
,
894 clear_depth
, pDepthStencil
->depth
,
895 clear_stencil
? 0xff : 0,
896 pDepthStencil
->stencil
);
900 blorp_batch_finish(&batch
);
904 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
905 uint32_t num_entries
,
906 uint32_t *state_offset
)
908 struct anv_state bt_state
=
909 anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
911 if (bt_state
.map
== NULL
) {
912 /* We ran out of space. Grab a new binding table block. */
913 MAYBE_UNUSED VkResult result
=
914 anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
915 assert(result
== VK_SUCCESS
);
917 /* Re-emit state base addresses so we get the new surface state base
918 * address before we start emitting binding tables etc.
920 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
922 bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
924 assert(bt_state
.map
!= NULL
);
931 binding_table_for_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
932 struct anv_state surface_state
)
934 uint32_t state_offset
;
935 struct anv_state bt_state
=
936 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, 1, &state_offset
);
938 uint32_t *bt_map
= bt_state
.map
;
939 bt_map
[0] = surface_state
.offset
+ state_offset
;
941 return bt_state
.offset
;
945 clear_color_attachment(struct anv_cmd_buffer
*cmd_buffer
,
946 struct blorp_batch
*batch
,
947 const VkClearAttachment
*attachment
,
948 uint32_t rectCount
, const VkClearRect
*pRects
)
950 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
951 const uint32_t color_att
= attachment
->colorAttachment
;
952 const uint32_t att_idx
= subpass
->color_attachments
[color_att
];
954 if (att_idx
== VK_ATTACHMENT_UNUSED
)
957 struct anv_render_pass_attachment
*pass_att
=
958 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
959 struct anv_attachment_state
*att_state
=
960 &cmd_buffer
->state
.attachments
[att_idx
];
962 uint32_t binding_table
=
963 binding_table_for_surface_state(cmd_buffer
, att_state
->color_rt_state
);
965 union isl_color_value clear_color
=
966 vk_to_isl_color(attachment
->clearValue
.color
);
968 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
969 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
970 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
971 blorp_clear_attachments(batch
, binding_table
,
972 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
973 pRects
[r
].baseArrayLayer
,
974 pRects
[r
].layerCount
,
976 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
977 true, clear_color
, false, 0.0f
, 0, 0);
982 clear_depth_stencil_attachment(struct anv_cmd_buffer
*cmd_buffer
,
983 struct blorp_batch
*batch
,
984 const VkClearAttachment
*attachment
,
985 uint32_t rectCount
, const VkClearRect
*pRects
)
987 static const union isl_color_value color_value
= { .u32
= { 0, } };
988 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
989 const uint32_t att_idx
= subpass
->depth_stencil_attachment
;
991 if (att_idx
== VK_ATTACHMENT_UNUSED
)
994 struct anv_render_pass_attachment
*pass_att
=
995 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
997 bool clear_depth
= attachment
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
998 bool clear_stencil
= attachment
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
1000 enum isl_format depth_format
= ISL_FORMAT_UNSUPPORTED
;
1002 depth_format
= anv_get_isl_format(&cmd_buffer
->device
->info
,
1004 VK_IMAGE_ASPECT_DEPTH_BIT
,
1005 VK_IMAGE_TILING_OPTIMAL
);
1008 uint32_t binding_table
=
1009 binding_table_for_surface_state(cmd_buffer
,
1010 cmd_buffer
->state
.null_surface_state
);
1012 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1013 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1014 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1015 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1016 blorp_clear_attachments(batch
, binding_table
,
1017 depth_format
, pass_att
->samples
,
1018 pRects
[r
].baseArrayLayer
,
1019 pRects
[r
].layerCount
,
1021 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1023 clear_depth
, value
.depth
,
1024 clear_stencil
? 0xff : 0, value
.stencil
);
1028 void anv_CmdClearAttachments(
1029 VkCommandBuffer commandBuffer
,
1030 uint32_t attachmentCount
,
1031 const VkClearAttachment
* pAttachments
,
1033 const VkClearRect
* pRects
)
1035 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1037 /* Because this gets called within a render pass, we tell blorp not to
1038 * trash our depth and stencil buffers.
1040 struct blorp_batch batch
;
1041 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1042 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1044 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1045 if (pAttachments
[a
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1046 clear_color_attachment(cmd_buffer
, &batch
,
1050 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1056 blorp_batch_finish(&batch
);
1059 enum subpass_stage
{
1062 SUBPASS_STAGE_RESOLVE
,
1066 attachment_needs_flush(struct anv_cmd_buffer
*cmd_buffer
,
1067 struct anv_render_pass_attachment
*att
,
1068 enum subpass_stage stage
)
1070 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1071 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1072 unsigned subpass_idx
= subpass
- pass
->subpasses
;
1073 assert(subpass_idx
< pass
->subpass_count
);
1075 /* We handle this subpass specially based on the current stage */
1076 enum anv_subpass_usage usage
= att
->subpass_usage
[subpass_idx
];
1078 case SUBPASS_STAGE_LOAD
:
1079 if (usage
& (ANV_SUBPASS_USAGE_INPUT
| ANV_SUBPASS_USAGE_RESOLVE_SRC
))
1083 case SUBPASS_STAGE_DRAW
:
1084 if (usage
& ANV_SUBPASS_USAGE_RESOLVE_SRC
)
1092 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1093 usage
= att
->subpass_usage
[s
];
1095 /* If this attachment is going to be used as an input in this or any
1096 * future subpass, then we need to flush its cache and invalidate the
1099 if (att
->subpass_usage
[s
] & ANV_SUBPASS_USAGE_INPUT
)
1102 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1103 /* We found another subpass that draws to this attachment. We'll
1104 * wait to resolve until then.
1114 anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer
*cmd_buffer
,
1115 enum subpass_stage stage
)
1117 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1118 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1120 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1121 uint32_t att
= subpass
->color_attachments
[i
];
1122 assert(att
< pass
->attachment_count
);
1123 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1124 cmd_buffer
->state
.pending_pipe_bits
|=
1125 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1126 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1130 if (subpass
->depth_stencil_attachment
!= VK_ATTACHMENT_UNUSED
) {
1131 uint32_t att
= subpass
->depth_stencil_attachment
;
1132 assert(att
< pass
->attachment_count
);
1133 if (attachment_needs_flush(cmd_buffer
, &pass
->attachments
[att
], stage
)) {
1134 cmd_buffer
->state
.pending_pipe_bits
|=
1135 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
1136 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1142 subpass_needs_clear(const struct anv_cmd_buffer
*cmd_buffer
)
1144 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1145 uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
1147 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1148 uint32_t a
= cmd_state
->subpass
->color_attachments
[i
];
1149 if (cmd_state
->attachments
[a
].pending_clear_aspects
) {
1154 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1155 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1163 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1165 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1166 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1169 if (!subpass_needs_clear(cmd_buffer
))
1172 /* Because this gets called within a render pass, we tell blorp not to
1173 * trash our depth and stencil buffers.
1175 struct blorp_batch batch
;
1176 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1177 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1179 VkClearRect clear_rect
= {
1180 .rect
= cmd_buffer
->state
.render_area
,
1181 .baseArrayLayer
= 0,
1182 .layerCount
= cmd_buffer
->state
.framebuffer
->layers
,
1185 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1186 for (uint32_t i
= 0; i
< cmd_state
->subpass
->color_count
; ++i
) {
1187 const uint32_t a
= cmd_state
->subpass
->color_attachments
[i
];
1188 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
1190 if (!att_state
->pending_clear_aspects
)
1193 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1195 struct anv_image_view
*iview
= fb
->attachments
[a
];
1196 const struct anv_image
*image
= iview
->image
;
1197 struct blorp_surf surf
;
1198 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1199 att_state
->aux_usage
, &surf
);
1200 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1202 if (att_state
->fast_clear
) {
1203 blorp_fast_clear(&batch
, &surf
, iview
->isl
.format
,
1204 iview
->isl
.base_level
,
1205 iview
->isl
.base_array_layer
, fb
->layers
,
1206 render_area
.offset
.x
, render_area
.offset
.y
,
1207 render_area
.offset
.x
+ render_area
.extent
.width
,
1208 render_area
.offset
.y
+ render_area
.extent
.height
);
1210 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1212 * "After Render target fast clear, pipe-control with color cache
1213 * write-flush must be issued before sending any DRAW commands on
1214 * that render target."
1216 cmd_buffer
->state
.pending_pipe_bits
|=
1217 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1219 blorp_clear(&batch
, &surf
, iview
->isl
.format
, iview
->isl
.swizzle
,
1220 iview
->isl
.base_level
,
1221 iview
->isl
.base_array_layer
, fb
->layers
,
1222 render_area
.offset
.x
, render_area
.offset
.y
,
1223 render_area
.offset
.x
+ render_area
.extent
.width
,
1224 render_area
.offset
.y
+ render_area
.extent
.height
,
1225 surf
.clear_color
, NULL
);
1228 att_state
->pending_clear_aspects
= 0;
1231 const uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
1233 if (ds
!= VK_ATTACHMENT_UNUSED
&&
1234 cmd_state
->attachments
[ds
].pending_clear_aspects
) {
1236 VkClearAttachment clear_att
= {
1237 .aspectMask
= cmd_state
->attachments
[ds
].pending_clear_aspects
,
1238 .clearValue
= cmd_state
->attachments
[ds
].clear_value
,
1242 const uint8_t gen
= cmd_buffer
->device
->info
.gen
;
1243 bool clear_with_hiz
= gen
>= 8 && cmd_state
->attachments
[ds
].aux_usage
==
1245 const struct anv_image_view
*iview
= fb
->attachments
[ds
];
1247 if (clear_with_hiz
) {
1248 const bool clear_depth
= clear_att
.aspectMask
&
1249 VK_IMAGE_ASPECT_DEPTH_BIT
;
1250 const bool clear_stencil
= clear_att
.aspectMask
&
1251 VK_IMAGE_ASPECT_STENCIL_BIT
;
1253 /* Check against restrictions for depth buffer clearing. A great GPU
1254 * performance benefit isn't expected when using the HZ sequence for
1255 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1256 * a stencil clear in addition to using the BLORP-fallback for depth.
1259 if (!blorp_can_hiz_clear_depth(gen
, iview
->isl
.format
,
1260 iview
->image
->samples
,
1261 render_area
.offset
.x
,
1262 render_area
.offset
.y
,
1263 render_area
.offset
.x
+
1264 render_area
.extent
.width
,
1265 render_area
.offset
.y
+
1266 render_area
.extent
.height
)) {
1267 clear_with_hiz
= false;
1268 } else if (clear_att
.clearValue
.depthStencil
.depth
!=
1270 /* Don't enable fast depth clears for any color not equal to
1273 clear_with_hiz
= false;
1277 if (clear_with_hiz
) {
1278 blorp_gen8_hiz_clear_attachments(&batch
, iview
->image
->samples
,
1279 render_area
.offset
.x
,
1280 render_area
.offset
.y
,
1281 render_area
.offset
.x
+
1282 render_area
.extent
.width
,
1283 render_area
.offset
.y
+
1284 render_area
.extent
.height
,
1285 clear_depth
, clear_stencil
,
1286 clear_att
.clearValue
.
1287 depthStencil
.stencil
);
1291 if (!clear_with_hiz
) {
1292 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1293 &clear_att
, 1, &clear_rect
);
1296 cmd_state
->attachments
[ds
].pending_clear_aspects
= 0;
1299 blorp_batch_finish(&batch
);
1301 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_LOAD
);
1305 resolve_image(struct blorp_batch
*batch
,
1306 const struct anv_image
*src_image
,
1307 uint32_t src_level
, uint32_t src_layer
,
1308 const struct anv_image
*dst_image
,
1309 uint32_t dst_level
, uint32_t dst_layer
,
1310 VkImageAspectFlags aspect_mask
,
1311 uint32_t src_x
, uint32_t src_y
, uint32_t dst_x
, uint32_t dst_y
,
1312 uint32_t width
, uint32_t height
)
1314 assert(src_image
->type
== VK_IMAGE_TYPE_2D
);
1315 assert(src_image
->samples
> 1);
1316 assert(dst_image
->type
== VK_IMAGE_TYPE_2D
);
1317 assert(dst_image
->samples
== 1);
1320 for_each_bit(a
, aspect_mask
) {
1321 VkImageAspectFlagBits aspect
= 1 << a
;
1323 struct blorp_surf src_surf
, dst_surf
;
1324 get_blorp_surf_for_anv_image(src_image
, aspect
,
1325 src_image
->aux_usage
, &src_surf
);
1326 get_blorp_surf_for_anv_image(dst_image
, aspect
,
1327 dst_image
->aux_usage
, &dst_surf
);
1330 &src_surf
, src_level
, src_layer
,
1331 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1332 &dst_surf
, dst_level
, dst_layer
,
1333 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1334 src_x
, src_y
, src_x
+ width
, src_y
+ height
,
1335 dst_x
, dst_y
, dst_x
+ width
, dst_y
+ height
,
1336 0x2600 /* GL_NEAREST */, false, false);
1340 void anv_CmdResolveImage(
1341 VkCommandBuffer commandBuffer
,
1343 VkImageLayout srcImageLayout
,
1345 VkImageLayout dstImageLayout
,
1346 uint32_t regionCount
,
1347 const VkImageResolve
* pRegions
)
1349 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1350 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
1351 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
1353 struct blorp_batch batch
;
1354 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1356 for (uint32_t r
= 0; r
< regionCount
; r
++) {
1357 assert(pRegions
[r
].srcSubresource
.aspectMask
==
1358 pRegions
[r
].dstSubresource
.aspectMask
);
1359 assert(pRegions
[r
].srcSubresource
.layerCount
==
1360 pRegions
[r
].dstSubresource
.layerCount
);
1362 const uint32_t layer_count
= pRegions
[r
].dstSubresource
.layerCount
;
1364 for (uint32_t layer
= 0; layer
< layer_count
; layer
++) {
1365 resolve_image(&batch
,
1366 src_image
, pRegions
[r
].srcSubresource
.mipLevel
,
1367 pRegions
[r
].srcSubresource
.baseArrayLayer
+ layer
,
1368 dst_image
, pRegions
[r
].dstSubresource
.mipLevel
,
1369 pRegions
[r
].dstSubresource
.baseArrayLayer
+ layer
,
1370 pRegions
[r
].dstSubresource
.aspectMask
,
1371 pRegions
[r
].srcOffset
.x
, pRegions
[r
].srcOffset
.y
,
1372 pRegions
[r
].dstOffset
.x
, pRegions
[r
].dstOffset
.y
,
1373 pRegions
[r
].extent
.width
, pRegions
[r
].extent
.height
);
1377 blorp_batch_finish(&batch
);
1381 ccs_resolve_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1382 struct blorp_batch
*batch
,
1385 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1386 struct anv_attachment_state
*att_state
=
1387 &cmd_buffer
->state
.attachments
[att
];
1389 if (att_state
->aux_usage
== ISL_AUX_USAGE_NONE
)
1390 return; /* Nothing to resolve */
1392 assert(att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
1393 att_state
->aux_usage
== ISL_AUX_USAGE_CCS_D
);
1395 struct anv_render_pass
*pass
= cmd_buffer
->state
.pass
;
1396 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1397 unsigned subpass_idx
= subpass
- pass
->subpasses
;
1398 assert(subpass_idx
< pass
->subpass_count
);
1400 /* Scan forward to see what all ways this attachment will be used.
1401 * Ideally, we would like to resolve in the same subpass as the last write
1402 * of a particular attachment. That way we only resolve once but it's
1403 * still hot in the cache.
1405 bool found_draw
= false;
1406 enum anv_subpass_usage usage
= 0;
1407 for (uint32_t s
= subpass_idx
+ 1; s
< pass
->subpass_count
; s
++) {
1408 usage
|= pass
->attachments
[att
].subpass_usage
[s
];
1410 if (usage
& (ANV_SUBPASS_USAGE_DRAW
| ANV_SUBPASS_USAGE_RESOLVE_DST
)) {
1411 /* We found another subpass that draws to this attachment. We'll
1412 * wait to resolve until then.
1419 struct anv_image_view
*iview
= fb
->attachments
[att
];
1420 const struct anv_image
*image
= iview
->image
;
1421 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1423 enum blorp_fast_clear_op resolve_op
= BLORP_FAST_CLEAR_OP_NONE
;
1425 /* This is the last subpass that writes to this attachment so we need to
1426 * resolve here. Ideally, we would like to only resolve if the storeOp
1427 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1428 * that the CCS bits are set to "resolved" because there may be copy or
1429 * blit operations (which may ignore CCS) between now and the next time
1430 * we render and we need to ensure that anything they write will be
1431 * respected in the next render. Unfortunately, the hardware does not
1432 * provide us with any sort of "invalidate" pass that sets the CCS to
1433 * "resolved" without writing to the render target.
1435 if (iview
->image
->aux_usage
!= ISL_AUX_USAGE_CCS_E
) {
1436 /* The image destination surface doesn't support compression outside
1437 * the render pass. We need a full resolve.
1439 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1440 } else if (att_state
->fast_clear
) {
1441 /* We don't know what to do with clear colors outside the render
1442 * pass. We need a partial resolve.
1444 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1446 /* The image "natively" supports all the compression we care about
1447 * and we don't need to resolve at all. If this is the case, we also
1448 * don't need to resolve for any of the input attachment cases below.
1451 } else if (usage
& ANV_SUBPASS_USAGE_INPUT
) {
1452 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1453 * can frequently sample from them with no resolves at all.
1455 if (att_state
->aux_usage
!= att_state
->input_aux_usage
) {
1456 assert(att_state
->input_aux_usage
== ISL_AUX_USAGE_NONE
);
1457 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_FULL
;
1458 } else if (!att_state
->clear_color_is_zero_one
) {
1459 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1461 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1462 * is fast cleared with non-0/1 clear value, this RT must be
1463 * partially resolved (refer to Partial Resolve operation) before
1464 * binding this surface to Sampler."
1466 resolve_op
= BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL
;
1470 if (resolve_op
== BLORP_FAST_CLEAR_OP_NONE
)
1473 struct blorp_surf surf
;
1474 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1475 att_state
->aux_usage
, &surf
);
1476 surf
.clear_color
= vk_to_isl_color(att_state
->clear_value
.color
);
1478 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1480 * "When performing a render target resolve, PIPE_CONTROL with end of
1481 * pipe sync must be delivered."
1483 * This comment is a bit cryptic and doesn't really tell you what's going
1484 * or what's really needed. It appears that fast clear ops are not
1485 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1486 * to ensure that the contents of the previous draw hit the render target
1487 * before we resolve and then use a second PIPE_CONTROL after the resolve
1488 * to ensure that it is completed before any additional drawing occurs.
1490 cmd_buffer
->state
.pending_pipe_bits
|=
1491 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1493 for (uint32_t layer
= 0; layer
< fb
->layers
; layer
++) {
1494 blorp_ccs_resolve(batch
, &surf
,
1495 iview
->isl
.base_level
,
1496 iview
->isl
.base_array_layer
+ layer
,
1497 iview
->isl
.format
, resolve_op
);
1500 cmd_buffer
->state
.pending_pipe_bits
|=
1501 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1503 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1504 att_state
->fast_clear
= false;
1508 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer
)
1510 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1511 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1514 struct blorp_batch batch
;
1515 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1517 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1518 ccs_resolve_attachment(cmd_buffer
, &batch
,
1519 subpass
->color_attachments
[i
]);
1522 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_DRAW
);
1524 if (subpass
->has_resolve
) {
1525 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1526 uint32_t src_att
= subpass
->color_attachments
[i
];
1527 uint32_t dst_att
= subpass
->resolve_attachments
[i
];
1529 if (dst_att
== VK_ATTACHMENT_UNUSED
)
1532 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
1533 /* From the Vulkan 1.0 spec:
1535 * If the first use of an attachment in a render pass is as a
1536 * resolve attachment, then the loadOp is effectively ignored
1537 * as the resolve is guaranteed to overwrite all pixels in the
1540 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
1543 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
1544 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
1546 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
1548 assert(src_iview
->aspect_mask
== dst_iview
->aspect_mask
);
1549 resolve_image(&batch
, src_iview
->image
,
1550 src_iview
->isl
.base_level
,
1551 src_iview
->isl
.base_array_layer
,
1553 dst_iview
->isl
.base_level
,
1554 dst_iview
->isl
.base_array_layer
,
1555 src_iview
->aspect_mask
,
1556 render_area
.offset
.x
, render_area
.offset
.y
,
1557 render_area
.offset
.x
, render_area
.offset
.y
,
1558 render_area
.extent
.width
, render_area
.extent
.height
);
1560 ccs_resolve_attachment(cmd_buffer
, &batch
, dst_att
);
1563 anv_cmd_buffer_flush_attachments(cmd_buffer
, SUBPASS_STAGE_RESOLVE
);
1566 blorp_batch_finish(&batch
);
1570 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1571 const struct anv_image
*image
,
1572 enum blorp_hiz_op op
)
1576 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1577 * don't perform such a resolve on gens that don't support it.
1579 if (cmd_buffer
->device
->info
.gen
< 8 ||
1580 image
->aux_usage
!= ISL_AUX_USAGE_HIZ
)
1583 const struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
1584 const uint32_t ds
= cmd_state
->subpass
->depth_stencil_attachment
;
1586 /* Section 7.4. of the Vulkan 1.0.27 spec states:
1588 * "The render area must be contained within the framebuffer dimensions."
1590 * Therefore, the only way the extent of the render area can match that of
1591 * the image view is if the render area offset equals (0, 0).
1593 const bool full_surface_op
=
1594 cmd_state
->render_area
.extent
.width
== image
->extent
.width
&&
1595 cmd_state
->render_area
.extent
.height
== image
->extent
.height
;
1596 if (full_surface_op
)
1597 assert(cmd_state
->render_area
.offset
.x
== 0 &&
1598 cmd_state
->render_area
.offset
.y
== 0);
1600 /* Check the subpass index to determine if skipping a resolve is allowed */
1601 const uint32_t subpass_idx
= cmd_state
->subpass
- cmd_state
->pass
->subpasses
;
1603 case BLORP_HIZ_OP_DEPTH_RESOLVE
:
1604 if (cmd_buffer
->state
.pass
->attachments
[ds
].store_op
!=
1605 VK_ATTACHMENT_STORE_OP_STORE
&&
1606 subpass_idx
== cmd_state
->pass
->subpass_count
- 1)
1609 case BLORP_HIZ_OP_HIZ_RESOLVE
:
1610 /* If the render area covers the entire surface *and* load_op is either
1611 * CLEAR or DONT_CARE then the previous contents of the depth buffer
1612 * will be entirely discarded. In this case, we can skip the HiZ
1615 * If the render area is not the full surface, we need to do
1616 * the resolve because otherwise data outside the render area may get
1617 * garbled by the resolve at the end of the render pass.
1619 if (full_surface_op
&&
1620 cmd_buffer
->state
.pass
->attachments
[ds
].load_op
!=
1621 VK_ATTACHMENT_LOAD_OP_LOAD
&& subpass_idx
== 0)
1624 case BLORP_HIZ_OP_DEPTH_CLEAR
:
1625 case BLORP_HIZ_OP_NONE
:
1626 unreachable("Invalid HiZ OP");
1630 struct blorp_batch batch
;
1631 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1633 struct blorp_surf surf
;
1634 get_blorp_surf_for_anv_image(image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1635 ISL_AUX_USAGE_NONE
, &surf
);
1637 /* Manually add the aux HiZ surf */
1638 surf
.aux_surf
= &image
->aux_surface
.isl
,
1639 surf
.aux_addr
= (struct blorp_address
) {
1640 .buffer
= image
->bo
,
1641 .offset
= image
->offset
+ image
->aux_surface
.offset
,
1643 surf
.aux_usage
= ISL_AUX_USAGE_HIZ
;
1645 surf
.clear_color
.u32
[0] = (uint32_t) ANV_HZ_FC_VAL
;
1647 blorp_gen6_hiz_op(&batch
, &surf
, 0, 0, op
);
1648 blorp_batch_finish(&batch
);