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anv: Don't use bogus alpha swizzles
[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_context *blorp,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct anv_device *device = blorp->driver_ctx;
32
33 /* The blorp cache must be a real cache */
34 assert(device->blorp_shader_cache.cache);
35
36 struct anv_shader_bin *bin =
37 anv_pipeline_cache_search(&device->blorp_shader_cache, key, key_size);
38 if (!bin)
39 return false;
40
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
43 */
44 anv_shader_bin_unref(device, bin);
45
46 *kernel_out = bin->kernel.offset;
47 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
48
49 return true;
50 }
51
52 static void
53 upload_blorp_shader(struct blorp_context *blorp,
54 const void *key, uint32_t key_size,
55 const void *kernel, uint32_t kernel_size,
56 const struct brw_stage_prog_data *prog_data,
57 uint32_t prog_data_size,
58 uint32_t *kernel_out, void *prog_data_out)
59 {
60 struct anv_device *device = blorp->driver_ctx;
61
62 /* The blorp cache must be a real cache */
63 assert(device->blorp_shader_cache.cache);
64
65 struct anv_pipeline_bind_map bind_map = {
66 .surface_count = 0,
67 .sampler_count = 0,
68 };
69
70 struct anv_shader_bin *bin =
71 anv_pipeline_cache_upload_kernel(&device->blorp_shader_cache,
72 key, key_size, kernel, kernel_size,
73 prog_data, prog_data_size, &bind_map);
74
75 /* The cache already has a reference and it's not going anywhere so there
76 * is no need to hold a second reference.
77 */
78 anv_shader_bin_unref(device, bin);
79
80 *kernel_out = bin->kernel.offset;
81 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
82 }
83
84 void
85 anv_device_init_blorp(struct anv_device *device)
86 {
87 anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
88 blorp_init(&device->blorp, device, &device->isl_dev);
89 device->blorp.compiler = device->instance->physicalDevice.compiler;
90 device->blorp.mocs.tex = device->default_mocs;
91 device->blorp.mocs.rb = device->default_mocs;
92 device->blorp.mocs.vb = device->default_mocs;
93 device->blorp.lookup_shader = lookup_blorp_shader;
94 device->blorp.upload_shader = upload_blorp_shader;
95 switch (device->info.gen) {
96 case 7:
97 if (device->info.is_haswell) {
98 device->blorp.exec = gen75_blorp_exec;
99 } else {
100 device->blorp.exec = gen7_blorp_exec;
101 }
102 break;
103 case 8:
104 device->blorp.exec = gen8_blorp_exec;
105 break;
106 case 9:
107 device->blorp.exec = gen9_blorp_exec;
108 break;
109 default:
110 unreachable("Unknown hardware generation");
111 }
112 }
113
114 void
115 anv_device_finish_blorp(struct anv_device *device)
116 {
117 blorp_finish(&device->blorp);
118 anv_pipeline_cache_finish(&device->blorp_shader_cache);
119 }
120
121 static void
122 get_blorp_surf_for_anv_buffer(struct anv_device *device,
123 struct anv_buffer *buffer, uint64_t offset,
124 uint32_t width, uint32_t height,
125 uint32_t row_pitch, enum isl_format format,
126 struct blorp_surf *blorp_surf,
127 struct isl_surf *isl_surf)
128 {
129 const struct isl_format_layout *fmtl =
130 isl_format_get_layout(format);
131
132 /* ASTC is the only format which doesn't support linear layouts.
133 * Create an equivalently sized surface with ISL to get around this.
134 */
135 if (fmtl->txc == ISL_TXC_ASTC) {
136 /* Use an equivalently sized format */
137 format = ISL_FORMAT_R32G32B32A32_UINT;
138 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
139
140 /* Shrink the dimensions for the new format */
141 width = DIV_ROUND_UP(width, fmtl->bw);
142 height = DIV_ROUND_UP(height, fmtl->bh);
143 }
144
145 *blorp_surf = (struct blorp_surf) {
146 .surf = isl_surf,
147 .addr = {
148 .buffer = buffer->bo,
149 .offset = buffer->offset + offset,
150 },
151 };
152
153 isl_surf_init(&device->isl_dev, isl_surf,
154 .dim = ISL_SURF_DIM_2D,
155 .format = format,
156 .width = width,
157 .height = height,
158 .depth = 1,
159 .levels = 1,
160 .array_len = 1,
161 .samples = 1,
162 .min_pitch = row_pitch,
163 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
164 ISL_SURF_USAGE_RENDER_TARGET_BIT,
165 .tiling_flags = ISL_TILING_LINEAR_BIT);
166 assert(isl_surf->row_pitch == row_pitch);
167 }
168
169 static void
170 get_blorp_surf_for_anv_image(const struct anv_image *image,
171 VkImageAspectFlags aspect,
172 enum isl_aux_usage aux_usage,
173 struct blorp_surf *blorp_surf)
174 {
175 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
176 aux_usage == ISL_AUX_USAGE_HIZ)
177 aux_usage = ISL_AUX_USAGE_NONE;
178
179 const struct anv_surface *surface =
180 anv_image_get_surface_for_aspect_mask(image, aspect);
181
182 *blorp_surf = (struct blorp_surf) {
183 .surf = &surface->isl,
184 .addr = {
185 .buffer = image->bo,
186 .offset = image->offset + surface->offset,
187 },
188 };
189
190 if (aux_usage != ISL_AUX_USAGE_NONE) {
191 blorp_surf->aux_surf = &image->aux_surface.isl,
192 blorp_surf->aux_addr = (struct blorp_address) {
193 .buffer = image->bo,
194 .offset = image->offset + image->aux_surface.offset,
195 };
196 blorp_surf->aux_usage = aux_usage;
197 }
198 }
199
200 void anv_CmdCopyImage(
201 VkCommandBuffer commandBuffer,
202 VkImage srcImage,
203 VkImageLayout srcImageLayout,
204 VkImage dstImage,
205 VkImageLayout dstImageLayout,
206 uint32_t regionCount,
207 const VkImageCopy* pRegions)
208 {
209 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
210 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
211 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
212
213 struct blorp_batch batch;
214 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
215
216 for (unsigned r = 0; r < regionCount; r++) {
217 VkOffset3D srcOffset =
218 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
219 VkOffset3D dstOffset =
220 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
221 VkExtent3D extent =
222 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
223
224 unsigned dst_base_layer, layer_count;
225 if (dst_image->type == VK_IMAGE_TYPE_3D) {
226 dst_base_layer = pRegions[r].dstOffset.z;
227 layer_count = pRegions[r].extent.depth;
228 } else {
229 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
230 layer_count = pRegions[r].dstSubresource.layerCount;
231 }
232
233 unsigned src_base_layer;
234 if (src_image->type == VK_IMAGE_TYPE_3D) {
235 src_base_layer = pRegions[r].srcOffset.z;
236 } else {
237 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
238 assert(pRegions[r].srcSubresource.layerCount == layer_count);
239 }
240
241 assert(pRegions[r].srcSubresource.aspectMask ==
242 pRegions[r].dstSubresource.aspectMask);
243
244 uint32_t a;
245 for_each_bit(a, pRegions[r].dstSubresource.aspectMask) {
246 VkImageAspectFlagBits aspect = (1 << a);
247
248 struct blorp_surf src_surf, dst_surf;
249 get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
250 &src_surf);
251 get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
252 &dst_surf);
253
254 for (unsigned i = 0; i < layer_count; i++) {
255 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
256 src_base_layer + i,
257 &dst_surf, pRegions[r].dstSubresource.mipLevel,
258 dst_base_layer + i,
259 srcOffset.x, srcOffset.y,
260 dstOffset.x, dstOffset.y,
261 extent.width, extent.height);
262 }
263 }
264 }
265
266 blorp_batch_finish(&batch);
267 }
268
269 static void
270 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
271 struct anv_buffer *anv_buffer,
272 struct anv_image *anv_image,
273 uint32_t regionCount,
274 const VkBufferImageCopy* pRegions,
275 bool buffer_to_image)
276 {
277 struct blorp_batch batch;
278 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
279
280 struct {
281 struct blorp_surf surf;
282 uint32_t level;
283 VkOffset3D offset;
284 } image, buffer, *src, *dst;
285
286 buffer.level = 0;
287 buffer.offset = (VkOffset3D) { 0, 0, 0 };
288
289 if (buffer_to_image) {
290 src = &buffer;
291 dst = &image;
292 } else {
293 src = &image;
294 dst = &buffer;
295 }
296
297 for (unsigned r = 0; r < regionCount; r++) {
298 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
299
300 get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
301 &image.surf);
302 image.offset =
303 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
304 image.level = pRegions[r].imageSubresource.mipLevel;
305
306 VkExtent3D extent =
307 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
308 if (anv_image->type != VK_IMAGE_TYPE_3D) {
309 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
310 extent.depth = pRegions[r].imageSubresource.layerCount;
311 }
312
313 const enum isl_format buffer_format =
314 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
315 aspect, VK_IMAGE_TILING_LINEAR);
316
317 const VkExtent3D bufferImageExtent = {
318 .width = pRegions[r].bufferRowLength ?
319 pRegions[r].bufferRowLength : extent.width,
320 .height = pRegions[r].bufferImageHeight ?
321 pRegions[r].bufferImageHeight : extent.height,
322 };
323
324 const struct isl_format_layout *buffer_fmtl =
325 isl_format_get_layout(buffer_format);
326
327 const uint32_t buffer_row_pitch =
328 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
329 (buffer_fmtl->bpb / 8);
330
331 const uint32_t buffer_layer_stride =
332 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
333 buffer_row_pitch;
334
335 struct isl_surf buffer_isl_surf;
336 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
337 anv_buffer, pRegions[r].bufferOffset,
338 extent.width, extent.height,
339 buffer_row_pitch, buffer_format,
340 &buffer.surf, &buffer_isl_surf);
341
342 for (unsigned z = 0; z < extent.depth; z++) {
343 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
344 &dst->surf, dst->level, dst->offset.z,
345 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
346 extent.width, extent.height);
347
348 image.offset.z++;
349 buffer.surf.addr.offset += buffer_layer_stride;
350 }
351 }
352
353 blorp_batch_finish(&batch);
354 }
355
356 void anv_CmdCopyBufferToImage(
357 VkCommandBuffer commandBuffer,
358 VkBuffer srcBuffer,
359 VkImage dstImage,
360 VkImageLayout dstImageLayout,
361 uint32_t regionCount,
362 const VkBufferImageCopy* pRegions)
363 {
364 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
365 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
366 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
367
368 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image,
369 regionCount, pRegions, true);
370 }
371
372 void anv_CmdCopyImageToBuffer(
373 VkCommandBuffer commandBuffer,
374 VkImage srcImage,
375 VkImageLayout srcImageLayout,
376 VkBuffer dstBuffer,
377 uint32_t regionCount,
378 const VkBufferImageCopy* pRegions)
379 {
380 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
381 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
382 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
383
384 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image,
385 regionCount, pRegions, false);
386 }
387
388 static bool
389 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
390 {
391 bool flip = false;
392 if (*src0 > *src1) {
393 unsigned tmp = *src0;
394 *src0 = *src1;
395 *src1 = tmp;
396 flip = !flip;
397 }
398
399 if (*dst0 > *dst1) {
400 unsigned tmp = *dst0;
401 *dst0 = *dst1;
402 *dst1 = tmp;
403 flip = !flip;
404 }
405
406 return flip;
407 }
408
409 void anv_CmdBlitImage(
410 VkCommandBuffer commandBuffer,
411 VkImage srcImage,
412 VkImageLayout srcImageLayout,
413 VkImage dstImage,
414 VkImageLayout dstImageLayout,
415 uint32_t regionCount,
416 const VkImageBlit* pRegions,
417 VkFilter filter)
418
419 {
420 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
421 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
422 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
423
424 struct blorp_surf src, dst;
425
426 uint32_t gl_filter;
427 switch (filter) {
428 case VK_FILTER_NEAREST:
429 gl_filter = 0x2600; /* GL_NEAREST */
430 break;
431 case VK_FILTER_LINEAR:
432 gl_filter = 0x2601; /* GL_LINEAR */
433 break;
434 default:
435 unreachable("Invalid filter");
436 }
437
438 struct blorp_batch batch;
439 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
440
441 for (unsigned r = 0; r < regionCount; r++) {
442 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
443 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
444
445 get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
446 src_image->aux_usage, &src);
447 get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
448 dst_image->aux_usage, &dst);
449
450 struct anv_format src_format =
451 anv_get_format(&cmd_buffer->device->info, src_image->vk_format,
452 src_res->aspectMask, src_image->tiling);
453 struct anv_format dst_format =
454 anv_get_format(&cmd_buffer->device->info, dst_image->vk_format,
455 dst_res->aspectMask, dst_image->tiling);
456
457 unsigned dst_start, dst_end;
458 if (dst_image->type == VK_IMAGE_TYPE_3D) {
459 assert(dst_res->baseArrayLayer == 0);
460 dst_start = pRegions[r].dstOffsets[0].z;
461 dst_end = pRegions[r].dstOffsets[1].z;
462 } else {
463 dst_start = dst_res->baseArrayLayer;
464 dst_end = dst_start + dst_res->layerCount;
465 }
466
467 unsigned src_start, src_end;
468 if (src_image->type == VK_IMAGE_TYPE_3D) {
469 assert(src_res->baseArrayLayer == 0);
470 src_start = pRegions[r].srcOffsets[0].z;
471 src_end = pRegions[r].srcOffsets[1].z;
472 } else {
473 src_start = src_res->baseArrayLayer;
474 src_end = src_start + src_res->layerCount;
475 }
476
477 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
478 float src_z_step = (float)(src_end + 1 - src_start) /
479 (float)(dst_end + 1 - dst_start);
480
481 if (flip_z) {
482 src_start = src_end;
483 src_z_step *= -1;
484 }
485
486 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
487 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
488 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
489 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
490 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
491
492 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
493 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
494 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
495 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
496 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
497
498 const unsigned num_layers = dst_end - dst_start;
499 for (unsigned i = 0; i < num_layers; i++) {
500 unsigned dst_z = dst_start + i;
501 unsigned src_z = src_start + i * src_z_step;
502
503 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
504 src_format.isl_format, src_format.swizzle,
505 &dst, dst_res->mipLevel, dst_z,
506 dst_format.isl_format,
507 anv_swizzle_for_render(dst_format.swizzle),
508 src_x0, src_y0, src_x1, src_y1,
509 dst_x0, dst_y0, dst_x1, dst_y1,
510 gl_filter, flip_x, flip_y);
511 }
512
513 }
514
515 blorp_batch_finish(&batch);
516 }
517
518 static enum isl_format
519 isl_format_for_size(unsigned size_B)
520 {
521 switch (size_B) {
522 case 1: return ISL_FORMAT_R8_UINT;
523 case 2: return ISL_FORMAT_R8G8_UINT;
524 case 4: return ISL_FORMAT_R8G8B8A8_UINT;
525 case 8: return ISL_FORMAT_R16G16B16A16_UINT;
526 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
527 default:
528 unreachable("Not a power-of-two format size");
529 }
530 }
531
532 static void
533 do_buffer_copy(struct blorp_batch *batch,
534 struct anv_bo *src, uint64_t src_offset,
535 struct anv_bo *dst, uint64_t dst_offset,
536 int width, int height, int block_size)
537 {
538 struct anv_device *device = batch->blorp->driver_ctx;
539
540 /* The actual format we pick doesn't matter as blorp will throw it away.
541 * The only thing that actually matters is the size.
542 */
543 enum isl_format format = isl_format_for_size(block_size);
544
545 struct isl_surf surf;
546 isl_surf_init(&device->isl_dev, &surf,
547 .dim = ISL_SURF_DIM_2D,
548 .format = format,
549 .width = width,
550 .height = height,
551 .depth = 1,
552 .levels = 1,
553 .array_len = 1,
554 .samples = 1,
555 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
556 ISL_SURF_USAGE_RENDER_TARGET_BIT,
557 .tiling_flags = ISL_TILING_LINEAR_BIT);
558 assert(surf.row_pitch == width * block_size);
559
560 struct blorp_surf src_blorp_surf = {
561 .surf = &surf,
562 .addr = {
563 .buffer = src,
564 .offset = src_offset,
565 },
566 };
567
568 struct blorp_surf dst_blorp_surf = {
569 .surf = &surf,
570 .addr = {
571 .buffer = dst,
572 .offset = dst_offset,
573 },
574 };
575
576 blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
577 0, 0, 0, 0, width, height);
578 }
579
580 /**
581 * Returns the greatest common divisor of a and b that is a power of two.
582 */
583 static inline uint64_t
584 gcd_pow2_u64(uint64_t a, uint64_t b)
585 {
586 assert(a > 0 || b > 0);
587
588 unsigned a_log2 = ffsll(a) - 1;
589 unsigned b_log2 = ffsll(b) - 1;
590
591 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
592 * case, the MIN2() will take the other one. If both are 0 then we will
593 * hit the assert above.
594 */
595 return 1 << MIN2(a_log2, b_log2);
596 }
597
598 /* This is maximum possible width/height our HW can handle */
599 #define MAX_SURFACE_DIM (1ull << 14)
600
601 void anv_CmdCopyBuffer(
602 VkCommandBuffer commandBuffer,
603 VkBuffer srcBuffer,
604 VkBuffer dstBuffer,
605 uint32_t regionCount,
606 const VkBufferCopy* pRegions)
607 {
608 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
609 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
610 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
611
612 struct blorp_batch batch;
613 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
614
615 for (unsigned r = 0; r < regionCount; r++) {
616 uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
617 uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
618 uint64_t copy_size = pRegions[r].size;
619
620 /* First, we compute the biggest format that can be used with the
621 * given offsets and size.
622 */
623 int bs = 16;
624 bs = gcd_pow2_u64(bs, src_offset);
625 bs = gcd_pow2_u64(bs, dst_offset);
626 bs = gcd_pow2_u64(bs, pRegions[r].size);
627
628 /* First, we make a bunch of max-sized copies */
629 uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
630 while (copy_size >= max_copy_size) {
631 do_buffer_copy(&batch, src_buffer->bo, src_offset,
632 dst_buffer->bo, dst_offset,
633 MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
634 copy_size -= max_copy_size;
635 src_offset += max_copy_size;
636 dst_offset += max_copy_size;
637 }
638
639 /* Now make a max-width copy */
640 uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
641 assert(height < MAX_SURFACE_DIM);
642 if (height != 0) {
643 uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
644 do_buffer_copy(&batch, src_buffer->bo, src_offset,
645 dst_buffer->bo, dst_offset,
646 MAX_SURFACE_DIM, height, bs);
647 copy_size -= rect_copy_size;
648 src_offset += rect_copy_size;
649 dst_offset += rect_copy_size;
650 }
651
652 /* Finally, make a small copy to finish it off */
653 if (copy_size != 0) {
654 do_buffer_copy(&batch, src_buffer->bo, src_offset,
655 dst_buffer->bo, dst_offset,
656 copy_size / bs, 1, bs);
657 }
658 }
659
660 blorp_batch_finish(&batch);
661 }
662
663 void anv_CmdUpdateBuffer(
664 VkCommandBuffer commandBuffer,
665 VkBuffer dstBuffer,
666 VkDeviceSize dstOffset,
667 VkDeviceSize dataSize,
668 const void* pData)
669 {
670 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
671 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
672
673 struct blorp_batch batch;
674 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
675
676 /* We can't quite grab a full block because the state stream needs a
677 * little data at the top to build its linked list.
678 */
679 const uint32_t max_update_size =
680 cmd_buffer->device->dynamic_state_block_pool.block_size - 64;
681
682 assert(max_update_size < MAX_SURFACE_DIM * 4);
683
684 while (dataSize) {
685 const uint32_t copy_size = MIN2(dataSize, max_update_size);
686
687 struct anv_state tmp_data =
688 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
689
690 memcpy(tmp_data.map, pData, copy_size);
691
692 int bs = 16;
693 bs = gcd_pow2_u64(bs, dstOffset);
694 bs = gcd_pow2_u64(bs, copy_size);
695
696 do_buffer_copy(&batch,
697 &cmd_buffer->device->dynamic_state_block_pool.bo,
698 tmp_data.offset,
699 dst_buffer->bo, dst_buffer->offset + dstOffset,
700 copy_size / bs, 1, bs);
701
702 dataSize -= copy_size;
703 dstOffset += copy_size;
704 pData = (void *)pData + copy_size;
705 }
706
707 blorp_batch_finish(&batch);
708 }
709
710 void anv_CmdFillBuffer(
711 VkCommandBuffer commandBuffer,
712 VkBuffer dstBuffer,
713 VkDeviceSize dstOffset,
714 VkDeviceSize fillSize,
715 uint32_t data)
716 {
717 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
718 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
719 struct blorp_surf surf;
720 struct isl_surf isl_surf;
721
722 struct blorp_batch batch;
723 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
724
725 if (fillSize == VK_WHOLE_SIZE) {
726 fillSize = dst_buffer->size - dstOffset;
727 /* Make sure fillSize is a multiple of 4 */
728 fillSize &= ~3ull;
729 }
730
731 /* First, we compute the biggest format that can be used with the
732 * given offsets and size.
733 */
734 int bs = 16;
735 bs = gcd_pow2_u64(bs, dstOffset);
736 bs = gcd_pow2_u64(bs, fillSize);
737 enum isl_format isl_format = isl_format_for_size(bs);
738
739 union isl_color_value color = {
740 .u32 = { data, data, data, data },
741 };
742
743 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
744 while (fillSize >= max_fill_size) {
745 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
746 dst_buffer, dstOffset,
747 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
748 MAX_SURFACE_DIM * bs, isl_format,
749 &surf, &isl_surf);
750
751 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
752 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
753 color, NULL);
754 fillSize -= max_fill_size;
755 dstOffset += max_fill_size;
756 }
757
758 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
759 assert(height < MAX_SURFACE_DIM);
760 if (height != 0) {
761 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
762 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
763 dst_buffer, dstOffset,
764 MAX_SURFACE_DIM, height,
765 MAX_SURFACE_DIM * bs, isl_format,
766 &surf, &isl_surf);
767
768 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
769 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
770 color, NULL);
771 fillSize -= rect_fill_size;
772 dstOffset += rect_fill_size;
773 }
774
775 if (fillSize != 0) {
776 const uint32_t width = fillSize / bs;
777 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
778 dst_buffer, dstOffset,
779 width, 1,
780 width * bs, isl_format,
781 &surf, &isl_surf);
782
783 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
784 0, 0, 1, 0, 0, width, 1,
785 color, NULL);
786 }
787
788 blorp_batch_finish(&batch);
789 }
790
791 void anv_CmdClearColorImage(
792 VkCommandBuffer commandBuffer,
793 VkImage _image,
794 VkImageLayout imageLayout,
795 const VkClearColorValue* pColor,
796 uint32_t rangeCount,
797 const VkImageSubresourceRange* pRanges)
798 {
799 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
800 ANV_FROM_HANDLE(anv_image, image, _image);
801
802 static const bool color_write_disable[4] = { false, false, false, false };
803
804 struct blorp_batch batch;
805 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
806
807 struct blorp_surf surf;
808 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
809 image->aux_usage, &surf);
810
811 for (unsigned r = 0; r < rangeCount; r++) {
812 if (pRanges[r].aspectMask == 0)
813 continue;
814
815 assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
816
817 struct anv_format src_format =
818 anv_get_format(&cmd_buffer->device->info, image->vk_format,
819 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
820
821 unsigned base_layer = pRanges[r].baseArrayLayer;
822 unsigned layer_count = pRanges[r].layerCount;
823
824 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
825 const unsigned level = pRanges[r].baseMipLevel + i;
826 const unsigned level_width = anv_minify(image->extent.width, level);
827 const unsigned level_height = anv_minify(image->extent.height, level);
828
829 if (image->type == VK_IMAGE_TYPE_3D) {
830 base_layer = 0;
831 layer_count = anv_minify(image->extent.depth, level);
832 }
833
834 blorp_clear(&batch, &surf,
835 src_format.isl_format,
836 anv_swizzle_for_render(src_format.swizzle),
837 level, base_layer, layer_count,
838 0, 0, level_width, level_height,
839 vk_to_isl_color(*pColor), color_write_disable);
840 }
841 }
842
843 blorp_batch_finish(&batch);
844 }
845
846 void anv_CmdClearDepthStencilImage(
847 VkCommandBuffer commandBuffer,
848 VkImage image_h,
849 VkImageLayout imageLayout,
850 const VkClearDepthStencilValue* pDepthStencil,
851 uint32_t rangeCount,
852 const VkImageSubresourceRange* pRanges)
853 {
854 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
855 ANV_FROM_HANDLE(anv_image, image, image_h);
856
857 struct blorp_batch batch;
858 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
859
860 struct blorp_surf depth, stencil;
861 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
862 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
863 ISL_AUX_USAGE_NONE, &depth);
864 } else {
865 memset(&depth, 0, sizeof(depth));
866 }
867
868 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
869 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
870 ISL_AUX_USAGE_NONE, &stencil);
871 } else {
872 memset(&stencil, 0, sizeof(stencil));
873 }
874
875 for (unsigned r = 0; r < rangeCount; r++) {
876 if (pRanges[r].aspectMask == 0)
877 continue;
878
879 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
880 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
881
882 unsigned base_layer = pRanges[r].baseArrayLayer;
883 unsigned layer_count = pRanges[r].layerCount;
884
885 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
886 const unsigned level = pRanges[r].baseMipLevel + i;
887 const unsigned level_width = anv_minify(image->extent.width, level);
888 const unsigned level_height = anv_minify(image->extent.height, level);
889
890 if (image->type == VK_IMAGE_TYPE_3D)
891 layer_count = anv_minify(image->extent.depth, level);
892
893 blorp_clear_depth_stencil(&batch, &depth, &stencil,
894 level, base_layer, layer_count,
895 0, 0, level_width, level_height,
896 clear_depth, pDepthStencil->depth,
897 clear_stencil ? 0xff : 0,
898 pDepthStencil->stencil);
899 }
900 }
901
902 blorp_batch_finish(&batch);
903 }
904
905 struct anv_state
906 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
907 uint32_t num_entries,
908 uint32_t *state_offset)
909 {
910 struct anv_state bt_state =
911 anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
912 state_offset);
913 if (bt_state.map == NULL) {
914 /* We ran out of space. Grab a new binding table block. */
915 MAYBE_UNUSED VkResult result =
916 anv_cmd_buffer_new_binding_table_block(cmd_buffer);
917 assert(result == VK_SUCCESS);
918
919 /* Re-emit state base addresses so we get the new surface state base
920 * address before we start emitting binding tables etc.
921 */
922 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
923
924 bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
925 state_offset);
926 assert(bt_state.map != NULL);
927 }
928
929 return bt_state;
930 }
931
932 static uint32_t
933 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
934 struct anv_state surface_state)
935 {
936 uint32_t state_offset;
937 struct anv_state bt_state =
938 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset);
939
940 uint32_t *bt_map = bt_state.map;
941 bt_map[0] = surface_state.offset + state_offset;
942
943 return bt_state.offset;
944 }
945
946 static void
947 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
948 struct blorp_batch *batch,
949 const VkClearAttachment *attachment,
950 uint32_t rectCount, const VkClearRect *pRects)
951 {
952 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
953 const uint32_t color_att = attachment->colorAttachment;
954 const uint32_t att_idx = subpass->color_attachments[color_att];
955
956 if (att_idx == VK_ATTACHMENT_UNUSED)
957 return;
958
959 struct anv_render_pass_attachment *pass_att =
960 &cmd_buffer->state.pass->attachments[att_idx];
961 struct anv_attachment_state *att_state =
962 &cmd_buffer->state.attachments[att_idx];
963
964 uint32_t binding_table =
965 binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state);
966
967 union isl_color_value clear_color =
968 vk_to_isl_color(attachment->clearValue.color);
969
970 for (uint32_t r = 0; r < rectCount; ++r) {
971 const VkOffset2D offset = pRects[r].rect.offset;
972 const VkExtent2D extent = pRects[r].rect.extent;
973 blorp_clear_attachments(batch, binding_table,
974 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
975 pRects[r].baseArrayLayer,
976 pRects[r].layerCount,
977 offset.x, offset.y,
978 offset.x + extent.width, offset.y + extent.height,
979 true, clear_color, false, 0.0f, 0, 0);
980 }
981 }
982
983 static void
984 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
985 struct blorp_batch *batch,
986 const VkClearAttachment *attachment,
987 uint32_t rectCount, const VkClearRect *pRects)
988 {
989 static const union isl_color_value color_value = { .u32 = { 0, } };
990 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
991 const uint32_t att_idx = subpass->depth_stencil_attachment;
992
993 if (att_idx == VK_ATTACHMENT_UNUSED)
994 return;
995
996 struct anv_render_pass_attachment *pass_att =
997 &cmd_buffer->state.pass->attachments[att_idx];
998
999 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
1000 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
1001
1002 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
1003 if (clear_depth) {
1004 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
1005 pass_att->format,
1006 VK_IMAGE_ASPECT_DEPTH_BIT,
1007 VK_IMAGE_TILING_OPTIMAL);
1008 }
1009
1010 uint32_t binding_table =
1011 binding_table_for_surface_state(cmd_buffer,
1012 cmd_buffer->state.null_surface_state);
1013
1014 for (uint32_t r = 0; r < rectCount; ++r) {
1015 const VkOffset2D offset = pRects[r].rect.offset;
1016 const VkExtent2D extent = pRects[r].rect.extent;
1017 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1018 blorp_clear_attachments(batch, binding_table,
1019 depth_format, pass_att->samples,
1020 pRects[r].baseArrayLayer,
1021 pRects[r].layerCount,
1022 offset.x, offset.y,
1023 offset.x + extent.width, offset.y + extent.height,
1024 false, color_value,
1025 clear_depth, value.depth,
1026 clear_stencil ? 0xff : 0, value.stencil);
1027 }
1028 }
1029
1030 void anv_CmdClearAttachments(
1031 VkCommandBuffer commandBuffer,
1032 uint32_t attachmentCount,
1033 const VkClearAttachment* pAttachments,
1034 uint32_t rectCount,
1035 const VkClearRect* pRects)
1036 {
1037 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1038
1039 /* Because this gets called within a render pass, we tell blorp not to
1040 * trash our depth and stencil buffers.
1041 */
1042 struct blorp_batch batch;
1043 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1044 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1045
1046 for (uint32_t a = 0; a < attachmentCount; ++a) {
1047 if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
1048 clear_color_attachment(cmd_buffer, &batch,
1049 &pAttachments[a],
1050 rectCount, pRects);
1051 } else {
1052 clear_depth_stencil_attachment(cmd_buffer, &batch,
1053 &pAttachments[a],
1054 rectCount, pRects);
1055 }
1056 }
1057
1058 blorp_batch_finish(&batch);
1059 }
1060
1061 enum subpass_stage {
1062 SUBPASS_STAGE_LOAD,
1063 SUBPASS_STAGE_DRAW,
1064 SUBPASS_STAGE_RESOLVE,
1065 };
1066
1067 static bool
1068 attachment_needs_flush(struct anv_cmd_buffer *cmd_buffer,
1069 struct anv_render_pass_attachment *att,
1070 enum subpass_stage stage)
1071 {
1072 struct anv_render_pass *pass = cmd_buffer->state.pass;
1073 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1074 unsigned subpass_idx = subpass - pass->subpasses;
1075 assert(subpass_idx < pass->subpass_count);
1076
1077 /* We handle this subpass specially based on the current stage */
1078 enum anv_subpass_usage usage = att->subpass_usage[subpass_idx];
1079 switch (stage) {
1080 case SUBPASS_STAGE_LOAD:
1081 if (usage & (ANV_SUBPASS_USAGE_INPUT | ANV_SUBPASS_USAGE_RESOLVE_SRC))
1082 return true;
1083 break;
1084
1085 case SUBPASS_STAGE_DRAW:
1086 if (usage & ANV_SUBPASS_USAGE_RESOLVE_SRC)
1087 return true;
1088 break;
1089
1090 default:
1091 break;
1092 }
1093
1094 for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
1095 usage = att->subpass_usage[s];
1096
1097 /* If this attachment is going to be used as an input in this or any
1098 * future subpass, then we need to flush its cache and invalidate the
1099 * texture cache.
1100 */
1101 if (att->subpass_usage[s] & ANV_SUBPASS_USAGE_INPUT)
1102 return true;
1103
1104 if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
1105 /* We found another subpass that draws to this attachment. We'll
1106 * wait to resolve until then.
1107 */
1108 return false;
1109 }
1110 }
1111
1112 return false;
1113 }
1114
1115 static void
1116 anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer *cmd_buffer,
1117 enum subpass_stage stage)
1118 {
1119 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1120 struct anv_render_pass *pass = cmd_buffer->state.pass;
1121
1122 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1123 uint32_t att = subpass->color_attachments[i];
1124 assert(att < pass->attachment_count);
1125 if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
1126 cmd_buffer->state.pending_pipe_bits |=
1127 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1128 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1129 }
1130 }
1131
1132 if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
1133 uint32_t att = subpass->depth_stencil_attachment;
1134 assert(att < pass->attachment_count);
1135 if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
1136 cmd_buffer->state.pending_pipe_bits |=
1137 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1138 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
1139 }
1140 }
1141 }
1142
1143 static bool
1144 subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
1145 {
1146 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1147 uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
1148
1149 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1150 uint32_t a = cmd_state->subpass->color_attachments[i];
1151 if (cmd_state->attachments[a].pending_clear_aspects) {
1152 return true;
1153 }
1154 }
1155
1156 if (ds != VK_ATTACHMENT_UNUSED &&
1157 cmd_state->attachments[ds].pending_clear_aspects) {
1158 return true;
1159 }
1160
1161 return false;
1162 }
1163
1164 void
1165 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
1166 {
1167 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1168 const VkRect2D render_area = cmd_buffer->state.render_area;
1169
1170
1171 if (!subpass_needs_clear(cmd_buffer))
1172 return;
1173
1174 /* Because this gets called within a render pass, we tell blorp not to
1175 * trash our depth and stencil buffers.
1176 */
1177 struct blorp_batch batch;
1178 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1179 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1180
1181 VkClearRect clear_rect = {
1182 .rect = cmd_buffer->state.render_area,
1183 .baseArrayLayer = 0,
1184 .layerCount = cmd_buffer->state.framebuffer->layers,
1185 };
1186
1187 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1188 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1189 const uint32_t a = cmd_state->subpass->color_attachments[i];
1190 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
1191
1192 if (!att_state->pending_clear_aspects)
1193 continue;
1194
1195 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1196
1197 struct anv_image_view *iview = fb->attachments[a];
1198 const struct anv_image *image = iview->image;
1199 struct blorp_surf surf;
1200 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1201 att_state->aux_usage, &surf);
1202 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1203
1204 if (att_state->fast_clear) {
1205 blorp_fast_clear(&batch, &surf, iview->isl.format,
1206 iview->isl.base_level,
1207 iview->isl.base_array_layer, fb->layers,
1208 render_area.offset.x, render_area.offset.y,
1209 render_area.offset.x + render_area.extent.width,
1210 render_area.offset.y + render_area.extent.height);
1211
1212 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1213 *
1214 * "After Render target fast clear, pipe-control with color cache
1215 * write-flush must be issued before sending any DRAW commands on
1216 * that render target."
1217 */
1218 cmd_buffer->state.pending_pipe_bits |=
1219 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1220 } else {
1221 blorp_clear(&batch, &surf, iview->isl.format,
1222 anv_swizzle_for_render(iview->isl.swizzle),
1223 iview->isl.base_level,
1224 iview->isl.base_array_layer, fb->layers,
1225 render_area.offset.x, render_area.offset.y,
1226 render_area.offset.x + render_area.extent.width,
1227 render_area.offset.y + render_area.extent.height,
1228 surf.clear_color, NULL);
1229 }
1230
1231 att_state->pending_clear_aspects = 0;
1232 }
1233
1234 const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
1235
1236 if (ds != VK_ATTACHMENT_UNUSED &&
1237 cmd_state->attachments[ds].pending_clear_aspects) {
1238
1239 VkClearAttachment clear_att = {
1240 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1241 .clearValue = cmd_state->attachments[ds].clear_value,
1242 };
1243
1244
1245 const uint8_t gen = cmd_buffer->device->info.gen;
1246 bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
1247 ISL_AUX_USAGE_HIZ;
1248 const struct anv_image_view *iview = fb->attachments[ds];
1249
1250 if (clear_with_hiz) {
1251 const bool clear_depth = clear_att.aspectMask &
1252 VK_IMAGE_ASPECT_DEPTH_BIT;
1253 const bool clear_stencil = clear_att.aspectMask &
1254 VK_IMAGE_ASPECT_STENCIL_BIT;
1255
1256 /* Check against restrictions for depth buffer clearing. A great GPU
1257 * performance benefit isn't expected when using the HZ sequence for
1258 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1259 * a stencil clear in addition to using the BLORP-fallback for depth.
1260 */
1261 if (clear_depth) {
1262 if (!blorp_can_hiz_clear_depth(gen, iview->isl.format,
1263 iview->image->samples,
1264 render_area.offset.x,
1265 render_area.offset.y,
1266 render_area.offset.x +
1267 render_area.extent.width,
1268 render_area.offset.y +
1269 render_area.extent.height)) {
1270 clear_with_hiz = false;
1271 } else if (clear_att.clearValue.depthStencil.depth !=
1272 ANV_HZ_FC_VAL) {
1273 /* Don't enable fast depth clears for any color not equal to
1274 * ANV_HZ_FC_VAL.
1275 */
1276 clear_with_hiz = false;
1277 } else if (gen == 8 &&
1278 anv_can_sample_with_hiz(cmd_buffer->device->info.gen,
1279 iview->image->samples)) {
1280 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
1281 * fast-cleared portion of a HiZ buffer. Testing has revealed
1282 * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
1283 * not support this feature at all.
1284 */
1285 clear_with_hiz = false;
1286 }
1287 }
1288
1289 if (clear_with_hiz) {
1290 blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
1291 render_area.offset.x,
1292 render_area.offset.y,
1293 render_area.offset.x +
1294 render_area.extent.width,
1295 render_area.offset.y +
1296 render_area.extent.height,
1297 clear_depth, clear_stencil,
1298 clear_att.clearValue.
1299 depthStencil.stencil);
1300 }
1301 }
1302
1303 if (!clear_with_hiz) {
1304 clear_depth_stencil_attachment(cmd_buffer, &batch,
1305 &clear_att, 1, &clear_rect);
1306 }
1307
1308 cmd_state->attachments[ds].pending_clear_aspects = 0;
1309 }
1310
1311 blorp_batch_finish(&batch);
1312
1313 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_LOAD);
1314 }
1315
1316 static void
1317 resolve_image(struct blorp_batch *batch,
1318 const struct anv_image *src_image,
1319 uint32_t src_level, uint32_t src_layer,
1320 const struct anv_image *dst_image,
1321 uint32_t dst_level, uint32_t dst_layer,
1322 VkImageAspectFlags aspect_mask,
1323 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1324 uint32_t width, uint32_t height)
1325 {
1326 assert(src_image->type == VK_IMAGE_TYPE_2D);
1327 assert(src_image->samples > 1);
1328 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1329 assert(dst_image->samples == 1);
1330
1331 uint32_t a;
1332 for_each_bit(a, aspect_mask) {
1333 VkImageAspectFlagBits aspect = 1 << a;
1334
1335 struct blorp_surf src_surf, dst_surf;
1336 get_blorp_surf_for_anv_image(src_image, aspect,
1337 src_image->aux_usage, &src_surf);
1338 get_blorp_surf_for_anv_image(dst_image, aspect,
1339 dst_image->aux_usage, &dst_surf);
1340
1341 blorp_blit(batch,
1342 &src_surf, src_level, src_layer,
1343 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1344 &dst_surf, dst_level, dst_layer,
1345 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1346 src_x, src_y, src_x + width, src_y + height,
1347 dst_x, dst_y, dst_x + width, dst_y + height,
1348 0x2600 /* GL_NEAREST */, false, false);
1349 }
1350 }
1351
1352 void anv_CmdResolveImage(
1353 VkCommandBuffer commandBuffer,
1354 VkImage srcImage,
1355 VkImageLayout srcImageLayout,
1356 VkImage dstImage,
1357 VkImageLayout dstImageLayout,
1358 uint32_t regionCount,
1359 const VkImageResolve* pRegions)
1360 {
1361 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1362 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1363 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1364
1365 struct blorp_batch batch;
1366 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1367
1368 for (uint32_t r = 0; r < regionCount; r++) {
1369 assert(pRegions[r].srcSubresource.aspectMask ==
1370 pRegions[r].dstSubresource.aspectMask);
1371 assert(pRegions[r].srcSubresource.layerCount ==
1372 pRegions[r].dstSubresource.layerCount);
1373
1374 const uint32_t layer_count = pRegions[r].dstSubresource.layerCount;
1375
1376 for (uint32_t layer = 0; layer < layer_count; layer++) {
1377 resolve_image(&batch,
1378 src_image, pRegions[r].srcSubresource.mipLevel,
1379 pRegions[r].srcSubresource.baseArrayLayer + layer,
1380 dst_image, pRegions[r].dstSubresource.mipLevel,
1381 pRegions[r].dstSubresource.baseArrayLayer + layer,
1382 pRegions[r].dstSubresource.aspectMask,
1383 pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
1384 pRegions[r].dstOffset.x, pRegions[r].dstOffset.y,
1385 pRegions[r].extent.width, pRegions[r].extent.height);
1386 }
1387 }
1388
1389 blorp_batch_finish(&batch);
1390 }
1391
1392 static void
1393 ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
1394 struct blorp_batch *batch,
1395 uint32_t att)
1396 {
1397 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1398 struct anv_attachment_state *att_state =
1399 &cmd_buffer->state.attachments[att];
1400
1401 if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
1402 return; /* Nothing to resolve */
1403
1404 assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
1405 att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
1406
1407 struct anv_render_pass *pass = cmd_buffer->state.pass;
1408 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1409 unsigned subpass_idx = subpass - pass->subpasses;
1410 assert(subpass_idx < pass->subpass_count);
1411
1412 /* Scan forward to see what all ways this attachment will be used.
1413 * Ideally, we would like to resolve in the same subpass as the last write
1414 * of a particular attachment. That way we only resolve once but it's
1415 * still hot in the cache.
1416 */
1417 bool found_draw = false;
1418 enum anv_subpass_usage usage = 0;
1419 for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
1420 usage |= pass->attachments[att].subpass_usage[s];
1421
1422 if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
1423 /* We found another subpass that draws to this attachment. We'll
1424 * wait to resolve until then.
1425 */
1426 found_draw = true;
1427 break;
1428 }
1429 }
1430
1431 struct anv_image_view *iview = fb->attachments[att];
1432 const struct anv_image *image = iview->image;
1433 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1434
1435 enum blorp_fast_clear_op resolve_op = BLORP_FAST_CLEAR_OP_NONE;
1436 if (!found_draw) {
1437 /* This is the last subpass that writes to this attachment so we need to
1438 * resolve here. Ideally, we would like to only resolve if the storeOp
1439 * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
1440 * that the CCS bits are set to "resolved" because there may be copy or
1441 * blit operations (which may ignore CCS) between now and the next time
1442 * we render and we need to ensure that anything they write will be
1443 * respected in the next render. Unfortunately, the hardware does not
1444 * provide us with any sort of "invalidate" pass that sets the CCS to
1445 * "resolved" without writing to the render target.
1446 */
1447 if (iview->image->aux_usage != ISL_AUX_USAGE_CCS_E) {
1448 /* The image destination surface doesn't support compression outside
1449 * the render pass. We need a full resolve.
1450 */
1451 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1452 } else if (att_state->fast_clear) {
1453 /* We don't know what to do with clear colors outside the render
1454 * pass. We need a partial resolve.
1455 */
1456 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1457 } else {
1458 /* The image "natively" supports all the compression we care about
1459 * and we don't need to resolve at all. If this is the case, we also
1460 * don't need to resolve for any of the input attachment cases below.
1461 */
1462 }
1463 } else if (usage & ANV_SUBPASS_USAGE_INPUT) {
1464 /* Input attachments are clear-color aware so, at least on Sky Lake, we
1465 * can frequently sample from them with no resolves at all.
1466 */
1467 if (att_state->aux_usage != att_state->input_aux_usage) {
1468 assert(att_state->input_aux_usage == ISL_AUX_USAGE_NONE);
1469 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
1470 } else if (!att_state->clear_color_is_zero_one) {
1471 /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
1472 *
1473 * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
1474 * is fast cleared with non-0/1 clear value, this RT must be
1475 * partially resolved (refer to Partial Resolve operation) before
1476 * binding this surface to Sampler."
1477 */
1478 resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
1479 }
1480 }
1481
1482 if (resolve_op == BLORP_FAST_CLEAR_OP_NONE)
1483 return;
1484
1485 struct blorp_surf surf;
1486 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
1487 att_state->aux_usage, &surf);
1488 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1489
1490 /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
1491 *
1492 * "When performing a render target resolve, PIPE_CONTROL with end of
1493 * pipe sync must be delivered."
1494 *
1495 * This comment is a bit cryptic and doesn't really tell you what's going
1496 * or what's really needed. It appears that fast clear ops are not
1497 * properly synchronized with other drawing. We need to use a PIPE_CONTROL
1498 * to ensure that the contents of the previous draw hit the render target
1499 * before we resolve and then use a second PIPE_CONTROL after the resolve
1500 * to ensure that it is completed before any additional drawing occurs.
1501 */
1502 cmd_buffer->state.pending_pipe_bits |=
1503 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1504
1505 for (uint32_t layer = 0; layer < fb->layers; layer++) {
1506 blorp_ccs_resolve(batch, &surf,
1507 iview->isl.base_level,
1508 iview->isl.base_array_layer + layer,
1509 iview->isl.format, resolve_op);
1510 }
1511
1512 cmd_buffer->state.pending_pipe_bits |=
1513 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1514
1515 /* Once we've done any sort of resolve, we're no longer fast-cleared */
1516 att_state->fast_clear = false;
1517 }
1518
1519 void
1520 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
1521 {
1522 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1523 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1524
1525
1526 struct blorp_batch batch;
1527 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1528
1529 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1530 ccs_resolve_attachment(cmd_buffer, &batch,
1531 subpass->color_attachments[i]);
1532 }
1533
1534 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_DRAW);
1535
1536 if (subpass->has_resolve) {
1537 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1538 uint32_t src_att = subpass->color_attachments[i];
1539 uint32_t dst_att = subpass->resolve_attachments[i];
1540
1541 if (dst_att == VK_ATTACHMENT_UNUSED)
1542 continue;
1543
1544 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
1545 /* From the Vulkan 1.0 spec:
1546 *
1547 * If the first use of an attachment in a render pass is as a
1548 * resolve attachment, then the loadOp is effectively ignored
1549 * as the resolve is guaranteed to overwrite all pixels in the
1550 * render area.
1551 */
1552 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
1553 }
1554
1555 struct anv_image_view *src_iview = fb->attachments[src_att];
1556 struct anv_image_view *dst_iview = fb->attachments[dst_att];
1557
1558 const VkRect2D render_area = cmd_buffer->state.render_area;
1559
1560 assert(src_iview->aspect_mask == dst_iview->aspect_mask);
1561 resolve_image(&batch, src_iview->image,
1562 src_iview->isl.base_level,
1563 src_iview->isl.base_array_layer,
1564 dst_iview->image,
1565 dst_iview->isl.base_level,
1566 dst_iview->isl.base_array_layer,
1567 src_iview->aspect_mask,
1568 render_area.offset.x, render_area.offset.y,
1569 render_area.offset.x, render_area.offset.y,
1570 render_area.extent.width, render_area.extent.height);
1571
1572 ccs_resolve_attachment(cmd_buffer, &batch, dst_att);
1573 }
1574
1575 anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_RESOLVE);
1576 }
1577
1578 blorp_batch_finish(&batch);
1579 }
1580
1581 void
1582 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
1583 const struct anv_image *image,
1584 enum blorp_hiz_op op)
1585 {
1586 assert(image);
1587
1588 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1589 * don't perform such a resolve on gens that don't support it.
1590 */
1591 if (cmd_buffer->device->info.gen < 8 ||
1592 image->aux_usage != ISL_AUX_USAGE_HIZ)
1593 return;
1594
1595 assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
1596 op == BLORP_HIZ_OP_DEPTH_RESOLVE);
1597
1598 struct blorp_batch batch;
1599 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1600
1601 struct blorp_surf surf;
1602 get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
1603 ISL_AUX_USAGE_NONE, &surf);
1604
1605 /* Manually add the aux HiZ surf */
1606 surf.aux_surf = &image->aux_surface.isl,
1607 surf.aux_addr = (struct blorp_address) {
1608 .buffer = image->bo,
1609 .offset = image->offset + image->aux_surface.offset,
1610 };
1611 surf.aux_usage = ISL_AUX_USAGE_HIZ;
1612
1613 surf.clear_color.u32[0] = (uint32_t) ANV_HZ_FC_VAL;
1614
1615 blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
1616 blorp_batch_finish(&batch);
1617 }