projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv/blorp: Add a device parameter to blorp_surf_for_anv_image
[mesa.git] / src / intel / vulkan / anv_blorp.c
1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "anv_private.h"
25
26 static bool
27 lookup_blorp_shader(struct blorp_context *blorp,
28 const void *key, uint32_t key_size,
29 uint32_t *kernel_out, void *prog_data_out)
30 {
31 struct anv_device *device = blorp->driver_ctx;
32
33 /* The blorp cache must be a real cache */
34 assert(device->blorp_shader_cache.cache);
35
36 struct anv_shader_bin *bin =
37 anv_pipeline_cache_search(&device->blorp_shader_cache, key, key_size);
38 if (!bin)
39 return false;
40
41 /* The cache already has a reference and it's not going anywhere so there
42 * is no need to hold a second reference.
43 */
44 anv_shader_bin_unref(device, bin);
45
46 *kernel_out = bin->kernel.offset;
47 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
48
49 return true;
50 }
51
52 static bool
53 upload_blorp_shader(struct blorp_context *blorp,
54 const void *key, uint32_t key_size,
55 const void *kernel, uint32_t kernel_size,
56 const struct brw_stage_prog_data *prog_data,
57 uint32_t prog_data_size,
58 uint32_t *kernel_out, void *prog_data_out)
59 {
60 struct anv_device *device = blorp->driver_ctx;
61
62 /* The blorp cache must be a real cache */
63 assert(device->blorp_shader_cache.cache);
64
65 struct anv_pipeline_bind_map bind_map = {
66 .surface_count = 0,
67 .sampler_count = 0,
68 };
69
70 struct anv_shader_bin *bin =
71 anv_pipeline_cache_upload_kernel(&device->blorp_shader_cache,
72 key, key_size, kernel, kernel_size,
73 prog_data, prog_data_size, &bind_map);
74
75 if (!bin)
76 return false;
77
78 /* The cache already has a reference and it's not going anywhere so there
79 * is no need to hold a second reference.
80 */
81 anv_shader_bin_unref(device, bin);
82
83 *kernel_out = bin->kernel.offset;
84 *(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
85
86 return true;
87 }
88
89 void
90 anv_device_init_blorp(struct anv_device *device)
91 {
92 anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
93 blorp_init(&device->blorp, device, &device->isl_dev);
94 device->blorp.compiler = device->instance->physicalDevice.compiler;
95 device->blorp.mocs.tex = device->default_mocs;
96 device->blorp.mocs.rb = device->default_mocs;
97 device->blorp.mocs.vb = device->default_mocs;
98 device->blorp.lookup_shader = lookup_blorp_shader;
99 device->blorp.upload_shader = upload_blorp_shader;
100 switch (device->info.gen) {
101 case 7:
102 if (device->info.is_haswell) {
103 device->blorp.exec = gen75_blorp_exec;
104 } else {
105 device->blorp.exec = gen7_blorp_exec;
106 }
107 break;
108 case 8:
109 device->blorp.exec = gen8_blorp_exec;
110 break;
111 case 9:
112 device->blorp.exec = gen9_blorp_exec;
113 break;
114 case 10:
115 device->blorp.exec = gen10_blorp_exec;
116 break;
117 default:
118 unreachable("Unknown hardware generation");
119 }
120 }
121
122 void
123 anv_device_finish_blorp(struct anv_device *device)
124 {
125 blorp_finish(&device->blorp);
126 anv_pipeline_cache_finish(&device->blorp_shader_cache);
127 }
128
129 static void
130 get_blorp_surf_for_anv_buffer(struct anv_device *device,
131 struct anv_buffer *buffer, uint64_t offset,
132 uint32_t width, uint32_t height,
133 uint32_t row_pitch, enum isl_format format,
134 struct blorp_surf *blorp_surf,
135 struct isl_surf *isl_surf)
136 {
137 const struct isl_format_layout *fmtl =
138 isl_format_get_layout(format);
139 bool ok UNUSED;
140
141 /* ASTC is the only format which doesn't support linear layouts.
142 * Create an equivalently sized surface with ISL to get around this.
143 */
144 if (fmtl->txc == ISL_TXC_ASTC) {
145 /* Use an equivalently sized format */
146 format = ISL_FORMAT_R32G32B32A32_UINT;
147 assert(fmtl->bpb == isl_format_get_layout(format)->bpb);
148
149 /* Shrink the dimensions for the new format */
150 width = DIV_ROUND_UP(width, fmtl->bw);
151 height = DIV_ROUND_UP(height, fmtl->bh);
152 }
153
154 *blorp_surf = (struct blorp_surf) {
155 .surf = isl_surf,
156 .addr = {
157 .buffer = buffer->bo,
158 .offset = buffer->offset + offset,
159 },
160 };
161
162 ok = isl_surf_init(&device->isl_dev, isl_surf,
163 .dim = ISL_SURF_DIM_2D,
164 .format = format,
165 .width = width,
166 .height = height,
167 .depth = 1,
168 .levels = 1,
169 .array_len = 1,
170 .samples = 1,
171 .row_pitch = row_pitch,
172 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
173 ISL_SURF_USAGE_RENDER_TARGET_BIT,
174 .tiling_flags = ISL_TILING_LINEAR_BIT);
175 assert(ok);
176 }
177
178 #define ANV_AUX_USAGE_DEFAULT ((enum isl_aux_usage)0xff)
179
180 static void
181 get_blorp_surf_for_anv_image(const struct anv_device *device,
182 const struct anv_image *image,
183 VkImageAspectFlags aspect,
184 enum isl_aux_usage aux_usage,
185 struct blorp_surf *blorp_surf)
186 {
187 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
188
189 if (aux_usage == ANV_AUX_USAGE_DEFAULT)
190 aux_usage = image->planes[plane].aux_usage;
191
192 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
193 aux_usage == ISL_AUX_USAGE_HIZ)
194 aux_usage = ISL_AUX_USAGE_NONE;
195
196 const struct anv_surface *surface = &image->planes[plane].surface;
197 *blorp_surf = (struct blorp_surf) {
198 .surf = &surface->isl,
199 .addr = {
200 .buffer = image->planes[plane].bo,
201 .offset = image->planes[plane].bo_offset + surface->offset,
202 },
203 };
204
205 if (aux_usage != ISL_AUX_USAGE_NONE) {
206 const struct anv_surface *aux_surface = &image->planes[plane].aux_surface;
207 blorp_surf->aux_surf = &aux_surface->isl,
208 blorp_surf->aux_addr = (struct blorp_address) {
209 .buffer = image->planes[plane].bo,
210 .offset = image->planes[plane].bo_offset + aux_surface->offset,
211 };
212 blorp_surf->aux_usage = aux_usage;
213 }
214 }
215
216 void anv_CmdCopyImage(
217 VkCommandBuffer commandBuffer,
218 VkImage srcImage,
219 VkImageLayout srcImageLayout,
220 VkImage dstImage,
221 VkImageLayout dstImageLayout,
222 uint32_t regionCount,
223 const VkImageCopy* pRegions)
224 {
225 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
226 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
227 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
228
229 struct blorp_batch batch;
230 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
231
232 for (unsigned r = 0; r < regionCount; r++) {
233 VkOffset3D srcOffset =
234 anv_sanitize_image_offset(src_image->type, pRegions[r].srcOffset);
235 VkOffset3D dstOffset =
236 anv_sanitize_image_offset(dst_image->type, pRegions[r].dstOffset);
237 VkExtent3D extent =
238 anv_sanitize_image_extent(src_image->type, pRegions[r].extent);
239
240 unsigned dst_base_layer, layer_count;
241 if (dst_image->type == VK_IMAGE_TYPE_3D) {
242 dst_base_layer = pRegions[r].dstOffset.z;
243 layer_count = pRegions[r].extent.depth;
244 } else {
245 dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
246 layer_count =
247 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
248 }
249
250 unsigned src_base_layer;
251 if (src_image->type == VK_IMAGE_TYPE_3D) {
252 src_base_layer = pRegions[r].srcOffset.z;
253 } else {
254 src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
255 assert(layer_count ==
256 anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
257 }
258
259 VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask,
260 dst_mask = pRegions[r].dstSubresource.aspectMask;
261
262 assert(anv_image_aspects_compatible(src_mask, dst_mask));
263
264 if (_mesa_bitcount(src_mask) > 1) {
265 uint32_t aspect_bit;
266 anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
267 struct blorp_surf src_surf, dst_surf;
268 get_blorp_surf_for_anv_image(cmd_buffer->device,
269 src_image, 1UL << aspect_bit,
270 ANV_AUX_USAGE_DEFAULT, &src_surf);
271 get_blorp_surf_for_anv_image(cmd_buffer->device,
272 dst_image, 1UL << aspect_bit,
273 ANV_AUX_USAGE_DEFAULT, &dst_surf);
274
275 for (unsigned i = 0; i < layer_count; i++) {
276 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
277 src_base_layer + i,
278 &dst_surf, pRegions[r].dstSubresource.mipLevel,
279 dst_base_layer + i,
280 srcOffset.x, srcOffset.y,
281 dstOffset.x, dstOffset.y,
282 extent.width, extent.height);
283 }
284 }
285 } else {
286 struct blorp_surf src_surf, dst_surf;
287 get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
288 ANV_AUX_USAGE_DEFAULT, &src_surf);
289 get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask,
290 ANV_AUX_USAGE_DEFAULT, &dst_surf);
291
292 for (unsigned i = 0; i < layer_count; i++) {
293 blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
294 src_base_layer + i,
295 &dst_surf, pRegions[r].dstSubresource.mipLevel,
296 dst_base_layer + i,
297 srcOffset.x, srcOffset.y,
298 dstOffset.x, dstOffset.y,
299 extent.width, extent.height);
300 }
301 }
302 }
303
304 blorp_batch_finish(&batch);
305 }
306
307 static void
308 copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
309 struct anv_buffer *anv_buffer,
310 struct anv_image *anv_image,
311 uint32_t regionCount,
312 const VkBufferImageCopy* pRegions,
313 bool buffer_to_image)
314 {
315 struct blorp_batch batch;
316 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
317
318 struct {
319 struct blorp_surf surf;
320 uint32_t level;
321 VkOffset3D offset;
322 } image, buffer, *src, *dst;
323
324 buffer.level = 0;
325 buffer.offset = (VkOffset3D) { 0, 0, 0 };
326
327 if (buffer_to_image) {
328 src = &buffer;
329 dst = &image;
330 } else {
331 src = &image;
332 dst = &buffer;
333 }
334
335 for (unsigned r = 0; r < regionCount; r++) {
336 const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
337
338 get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
339 ANV_AUX_USAGE_DEFAULT, &image.surf);
340 image.offset =
341 anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
342 image.level = pRegions[r].imageSubresource.mipLevel;
343
344 VkExtent3D extent =
345 anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
346 if (anv_image->type != VK_IMAGE_TYPE_3D) {
347 image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
348 extent.depth =
349 anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
350 }
351
352 const enum isl_format buffer_format =
353 anv_get_isl_format(&cmd_buffer->device->info, anv_image->vk_format,
354 aspect, VK_IMAGE_TILING_LINEAR);
355
356 const VkExtent3D bufferImageExtent = {
357 .width = pRegions[r].bufferRowLength ?
358 pRegions[r].bufferRowLength : extent.width,
359 .height = pRegions[r].bufferImageHeight ?
360 pRegions[r].bufferImageHeight : extent.height,
361 };
362
363 const struct isl_format_layout *buffer_fmtl =
364 isl_format_get_layout(buffer_format);
365
366 const uint32_t buffer_row_pitch =
367 DIV_ROUND_UP(bufferImageExtent.width, buffer_fmtl->bw) *
368 (buffer_fmtl->bpb / 8);
369
370 const uint32_t buffer_layer_stride =
371 DIV_ROUND_UP(bufferImageExtent.height, buffer_fmtl->bh) *
372 buffer_row_pitch;
373
374 struct isl_surf buffer_isl_surf;
375 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
376 anv_buffer, pRegions[r].bufferOffset,
377 extent.width, extent.height,
378 buffer_row_pitch, buffer_format,
379 &buffer.surf, &buffer_isl_surf);
380
381 for (unsigned z = 0; z < extent.depth; z++) {
382 blorp_copy(&batch, &src->surf, src->level, src->offset.z,
383 &dst->surf, dst->level, dst->offset.z,
384 src->offset.x, src->offset.y, dst->offset.x, dst->offset.y,
385 extent.width, extent.height);
386
387 image.offset.z++;
388 buffer.surf.addr.offset += buffer_layer_stride;
389 }
390 }
391
392 blorp_batch_finish(&batch);
393 }
394
395 void anv_CmdCopyBufferToImage(
396 VkCommandBuffer commandBuffer,
397 VkBuffer srcBuffer,
398 VkImage dstImage,
399 VkImageLayout dstImageLayout,
400 uint32_t regionCount,
401 const VkBufferImageCopy* pRegions)
402 {
403 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
404 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
405 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
406
407 copy_buffer_to_image(cmd_buffer, src_buffer, dst_image,
408 regionCount, pRegions, true);
409 }
410
411 void anv_CmdCopyImageToBuffer(
412 VkCommandBuffer commandBuffer,
413 VkImage srcImage,
414 VkImageLayout srcImageLayout,
415 VkBuffer dstBuffer,
416 uint32_t regionCount,
417 const VkBufferImageCopy* pRegions)
418 {
419 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
420 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
421 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
422
423 copy_buffer_to_image(cmd_buffer, dst_buffer, src_image,
424 regionCount, pRegions, false);
425 }
426
427 static bool
428 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
429 {
430 bool flip = false;
431 if (*src0 > *src1) {
432 unsigned tmp = *src0;
433 *src0 = *src1;
434 *src1 = tmp;
435 flip = !flip;
436 }
437
438 if (*dst0 > *dst1) {
439 unsigned tmp = *dst0;
440 *dst0 = *dst1;
441 *dst1 = tmp;
442 flip = !flip;
443 }
444
445 return flip;
446 }
447
448 void anv_CmdBlitImage(
449 VkCommandBuffer commandBuffer,
450 VkImage srcImage,
451 VkImageLayout srcImageLayout,
452 VkImage dstImage,
453 VkImageLayout dstImageLayout,
454 uint32_t regionCount,
455 const VkImageBlit* pRegions,
456 VkFilter filter)
457
458 {
459 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
460 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
461 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
462
463 struct blorp_surf src, dst;
464
465 uint32_t gl_filter;
466 switch (filter) {
467 case VK_FILTER_NEAREST:
468 gl_filter = 0x2600; /* GL_NEAREST */
469 break;
470 case VK_FILTER_LINEAR:
471 gl_filter = 0x2601; /* GL_LINEAR */
472 break;
473 default:
474 unreachable("Invalid filter");
475 }
476
477 struct blorp_batch batch;
478 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
479
480 for (unsigned r = 0; r < regionCount; r++) {
481 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
482 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
483
484 get_blorp_surf_for_anv_image(cmd_buffer->device,
485 src_image, src_res->aspectMask,
486 ANV_AUX_USAGE_DEFAULT, &src);
487 get_blorp_surf_for_anv_image(cmd_buffer->device,
488 dst_image, dst_res->aspectMask,
489 ANV_AUX_USAGE_DEFAULT, &dst);
490
491 struct anv_format_plane src_format =
492 anv_get_format_plane(&cmd_buffer->device->info, src_image->vk_format,
493 src_res->aspectMask, src_image->tiling);
494 struct anv_format_plane dst_format =
495 anv_get_format_plane(&cmd_buffer->device->info, dst_image->vk_format,
496 dst_res->aspectMask, dst_image->tiling);
497
498 unsigned dst_start, dst_end;
499 if (dst_image->type == VK_IMAGE_TYPE_3D) {
500 assert(dst_res->baseArrayLayer == 0);
501 dst_start = pRegions[r].dstOffsets[0].z;
502 dst_end = pRegions[r].dstOffsets[1].z;
503 } else {
504 dst_start = dst_res->baseArrayLayer;
505 dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
506 }
507
508 unsigned src_start, src_end;
509 if (src_image->type == VK_IMAGE_TYPE_3D) {
510 assert(src_res->baseArrayLayer == 0);
511 src_start = pRegions[r].srcOffsets[0].z;
512 src_end = pRegions[r].srcOffsets[1].z;
513 } else {
514 src_start = src_res->baseArrayLayer;
515 src_end = src_start + anv_get_layerCount(src_image, src_res);
516 }
517
518 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
519 float src_z_step = (float)(src_end + 1 - src_start) /
520 (float)(dst_end + 1 - dst_start);
521
522 if (flip_z) {
523 src_start = src_end;
524 src_z_step *= -1;
525 }
526
527 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
528 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
529 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
530 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
531 bool flip_x = flip_coords(&src_x0, &src_x1, &dst_x0, &dst_x1);
532
533 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
534 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
535 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
536 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
537 bool flip_y = flip_coords(&src_y0, &src_y1, &dst_y0, &dst_y1);
538
539 const unsigned num_layers = dst_end - dst_start;
540 for (unsigned i = 0; i < num_layers; i++) {
541 unsigned dst_z = dst_start + i;
542 unsigned src_z = src_start + i * src_z_step;
543
544 blorp_blit(&batch, &src, src_res->mipLevel, src_z,
545 src_format.isl_format, src_format.swizzle,
546 &dst, dst_res->mipLevel, dst_z,
547 dst_format.isl_format,
548 anv_swizzle_for_render(dst_format.swizzle),
549 src_x0, src_y0, src_x1, src_y1,
550 dst_x0, dst_y0, dst_x1, dst_y1,
551 gl_filter, flip_x, flip_y);
552 }
553
554 }
555
556 blorp_batch_finish(&batch);
557 }
558
559 static enum isl_format
560 isl_format_for_size(unsigned size_B)
561 {
562 switch (size_B) {
563 case 4: return ISL_FORMAT_R32_UINT;
564 case 8: return ISL_FORMAT_R32G32_UINT;
565 case 16: return ISL_FORMAT_R32G32B32A32_UINT;
566 default:
567 unreachable("Not a power-of-two format size");
568 }
569 }
570
571 /**
572 * Returns the greatest common divisor of a and b that is a power of two.
573 */
574 static uint64_t
575 gcd_pow2_u64(uint64_t a, uint64_t b)
576 {
577 assert(a > 0 || b > 0);
578
579 unsigned a_log2 = ffsll(a) - 1;
580 unsigned b_log2 = ffsll(b) - 1;
581
582 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
583 * case, the MIN2() will take the other one. If both are 0 then we will
584 * hit the assert above.
585 */
586 return 1 << MIN2(a_log2, b_log2);
587 }
588
589 /* This is maximum possible width/height our HW can handle */
590 #define MAX_SURFACE_DIM (1ull << 14)
591
592 void anv_CmdCopyBuffer(
593 VkCommandBuffer commandBuffer,
594 VkBuffer srcBuffer,
595 VkBuffer dstBuffer,
596 uint32_t regionCount,
597 const VkBufferCopy* pRegions)
598 {
599 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
600 ANV_FROM_HANDLE(anv_buffer, src_buffer, srcBuffer);
601 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
602
603 struct blorp_batch batch;
604 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
605
606 for (unsigned r = 0; r < regionCount; r++) {
607 struct blorp_address src = {
608 .buffer = src_buffer->bo,
609 .offset = src_buffer->offset + pRegions[r].srcOffset,
610 };
611 struct blorp_address dst = {
612 .buffer = dst_buffer->bo,
613 .offset = dst_buffer->offset + pRegions[r].dstOffset,
614 };
615
616 blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
617 }
618
619 blorp_batch_finish(&batch);
620 }
621
622 void anv_CmdUpdateBuffer(
623 VkCommandBuffer commandBuffer,
624 VkBuffer dstBuffer,
625 VkDeviceSize dstOffset,
626 VkDeviceSize dataSize,
627 const void* pData)
628 {
629 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
630 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
631
632 struct blorp_batch batch;
633 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
634
635 /* We can't quite grab a full block because the state stream needs a
636 * little data at the top to build its linked list.
637 */
638 const uint32_t max_update_size =
639 cmd_buffer->device->dynamic_state_pool.block_size - 64;
640
641 assert(max_update_size < MAX_SURFACE_DIM * 4);
642
643 /* We're about to read data that was written from the CPU. Flush the
644 * texture cache so we don't get anything stale.
645 */
646 cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
647
648 while (dataSize) {
649 const uint32_t copy_size = MIN2(dataSize, max_update_size);
650
651 struct anv_state tmp_data =
652 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64);
653
654 memcpy(tmp_data.map, pData, copy_size);
655
656 anv_state_flush(cmd_buffer->device, tmp_data);
657
658 struct blorp_address src = {
659 .buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
660 .offset = tmp_data.offset,
661 };
662 struct blorp_address dst = {
663 .buffer = dst_buffer->bo,
664 .offset = dst_buffer->offset + dstOffset,
665 };
666
667 blorp_buffer_copy(&batch, src, dst, copy_size);
668
669 dataSize -= copy_size;
670 dstOffset += copy_size;
671 pData = (void *)pData + copy_size;
672 }
673
674 blorp_batch_finish(&batch);
675 }
676
677 void anv_CmdFillBuffer(
678 VkCommandBuffer commandBuffer,
679 VkBuffer dstBuffer,
680 VkDeviceSize dstOffset,
681 VkDeviceSize fillSize,
682 uint32_t data)
683 {
684 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
685 ANV_FROM_HANDLE(anv_buffer, dst_buffer, dstBuffer);
686 struct blorp_surf surf;
687 struct isl_surf isl_surf;
688
689 struct blorp_batch batch;
690 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
691
692 fillSize = anv_buffer_get_range(dst_buffer, dstOffset, fillSize);
693
694 /* From the Vulkan spec:
695 *
696 * "size is the number of bytes to fill, and must be either a multiple
697 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
698 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
699 * buffer is not a multiple of 4, then the nearest smaller multiple is
700 * used."
701 */
702 fillSize &= ~3ull;
703
704 /* First, we compute the biggest format that can be used with the
705 * given offsets and size.
706 */
707 int bs = 16;
708 bs = gcd_pow2_u64(bs, dstOffset);
709 bs = gcd_pow2_u64(bs, fillSize);
710 enum isl_format isl_format = isl_format_for_size(bs);
711
712 union isl_color_value color = {
713 .u32 = { data, data, data, data },
714 };
715
716 const uint64_t max_fill_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
717 while (fillSize >= max_fill_size) {
718 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
719 dst_buffer, dstOffset,
720 MAX_SURFACE_DIM, MAX_SURFACE_DIM,
721 MAX_SURFACE_DIM * bs, isl_format,
722 &surf, &isl_surf);
723
724 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
725 0, 0, 1, 0, 0, MAX_SURFACE_DIM, MAX_SURFACE_DIM,
726 color, NULL);
727 fillSize -= max_fill_size;
728 dstOffset += max_fill_size;
729 }
730
731 uint64_t height = fillSize / (MAX_SURFACE_DIM * bs);
732 assert(height < MAX_SURFACE_DIM);
733 if (height != 0) {
734 const uint64_t rect_fill_size = height * MAX_SURFACE_DIM * bs;
735 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
736 dst_buffer, dstOffset,
737 MAX_SURFACE_DIM, height,
738 MAX_SURFACE_DIM * bs, isl_format,
739 &surf, &isl_surf);
740
741 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
742 0, 0, 1, 0, 0, MAX_SURFACE_DIM, height,
743 color, NULL);
744 fillSize -= rect_fill_size;
745 dstOffset += rect_fill_size;
746 }
747
748 if (fillSize != 0) {
749 const uint32_t width = fillSize / bs;
750 get_blorp_surf_for_anv_buffer(cmd_buffer->device,
751 dst_buffer, dstOffset,
752 width, 1,
753 width * bs, isl_format,
754 &surf, &isl_surf);
755
756 blorp_clear(&batch, &surf, isl_format, ISL_SWIZZLE_IDENTITY,
757 0, 0, 1, 0, 0, width, 1,
758 color, NULL);
759 }
760
761 blorp_batch_finish(&batch);
762 }
763
764 void anv_CmdClearColorImage(
765 VkCommandBuffer commandBuffer,
766 VkImage _image,
767 VkImageLayout imageLayout,
768 const VkClearColorValue* pColor,
769 uint32_t rangeCount,
770 const VkImageSubresourceRange* pRanges)
771 {
772 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
773 ANV_FROM_HANDLE(anv_image, image, _image);
774
775 static const bool color_write_disable[4] = { false, false, false, false };
776
777 struct blorp_batch batch;
778 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
779
780
781 for (unsigned r = 0; r < rangeCount; r++) {
782 if (pRanges[r].aspectMask == 0)
783 continue;
784
785 assert(pRanges[r].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
786
787 struct blorp_surf surf;
788 get_blorp_surf_for_anv_image(cmd_buffer->device,
789 image, pRanges[r].aspectMask,
790 ANV_AUX_USAGE_DEFAULT, &surf);
791
792 struct anv_format_plane src_format =
793 anv_get_format_plane(&cmd_buffer->device->info, image->vk_format,
794 VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
795
796 unsigned base_layer = pRanges[r].baseArrayLayer;
797 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
798
799 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
800 const unsigned level = pRanges[r].baseMipLevel + i;
801 const unsigned level_width = anv_minify(image->extent.width, level);
802 const unsigned level_height = anv_minify(image->extent.height, level);
803
804 if (image->type == VK_IMAGE_TYPE_3D) {
805 base_layer = 0;
806 layer_count = anv_minify(image->extent.depth, level);
807 }
808
809 blorp_clear(&batch, &surf,
810 src_format.isl_format, src_format.swizzle,
811 level, base_layer, layer_count,
812 0, 0, level_width, level_height,
813 vk_to_isl_color(*pColor), color_write_disable);
814 }
815 }
816
817 blorp_batch_finish(&batch);
818 }
819
820 void anv_CmdClearDepthStencilImage(
821 VkCommandBuffer commandBuffer,
822 VkImage image_h,
823 VkImageLayout imageLayout,
824 const VkClearDepthStencilValue* pDepthStencil,
825 uint32_t rangeCount,
826 const VkImageSubresourceRange* pRanges)
827 {
828 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
829 ANV_FROM_HANDLE(anv_image, image, image_h);
830
831 struct blorp_batch batch;
832 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
833
834 struct blorp_surf depth, stencil;
835 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
836 get_blorp_surf_for_anv_image(cmd_buffer->device,
837 image, VK_IMAGE_ASPECT_DEPTH_BIT,
838 ISL_AUX_USAGE_NONE, &depth);
839 } else {
840 memset(&depth, 0, sizeof(depth));
841 }
842
843 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
844 get_blorp_surf_for_anv_image(cmd_buffer->device,
845 image, VK_IMAGE_ASPECT_STENCIL_BIT,
846 ISL_AUX_USAGE_NONE, &stencil);
847 } else {
848 memset(&stencil, 0, sizeof(stencil));
849 }
850
851 for (unsigned r = 0; r < rangeCount; r++) {
852 if (pRanges[r].aspectMask == 0)
853 continue;
854
855 bool clear_depth = pRanges[r].aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
856 bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
857
858 unsigned base_layer = pRanges[r].baseArrayLayer;
859 unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
860
861 for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
862 const unsigned level = pRanges[r].baseMipLevel + i;
863 const unsigned level_width = anv_minify(image->extent.width, level);
864 const unsigned level_height = anv_minify(image->extent.height, level);
865
866 if (image->type == VK_IMAGE_TYPE_3D)
867 layer_count = anv_minify(image->extent.depth, level);
868
869 blorp_clear_depth_stencil(&batch, &depth, &stencil,
870 level, base_layer, layer_count,
871 0, 0, level_width, level_height,
872 clear_depth, pDepthStencil->depth,
873 clear_stencil ? 0xff : 0,
874 pDepthStencil->stencil);
875 }
876 }
877
878 blorp_batch_finish(&batch);
879 }
880
881 VkResult
882 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
883 uint32_t num_entries,
884 uint32_t *state_offset,
885 struct anv_state *bt_state)
886 {
887 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
888 state_offset);
889 if (bt_state->map == NULL) {
890 /* We ran out of space. Grab a new binding table block. */
891 VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
892 if (result != VK_SUCCESS)
893 return result;
894
895 /* Re-emit state base addresses so we get the new surface state base
896 * address before we start emitting binding tables etc.
897 */
898 anv_cmd_buffer_emit_state_base_address(cmd_buffer);
899
900 *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
901 state_offset);
902 assert(bt_state->map != NULL);
903 }
904
905 return VK_SUCCESS;
906 }
907
908 static VkResult
909 binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
910 struct anv_state surface_state,
911 uint32_t *bt_offset)
912 {
913 uint32_t state_offset;
914 struct anv_state bt_state;
915
916 VkResult result =
917 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
918 &bt_state);
919 if (result != VK_SUCCESS)
920 return result;
921
922 uint32_t *bt_map = bt_state.map;
923 bt_map[0] = surface_state.offset + state_offset;
924
925 *bt_offset = bt_state.offset;
926 return VK_SUCCESS;
927 }
928
929 static void
930 clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
931 struct blorp_batch *batch,
932 const VkClearAttachment *attachment,
933 uint32_t rectCount, const VkClearRect *pRects)
934 {
935 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
936 const uint32_t color_att = attachment->colorAttachment;
937 const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
938
939 if (att_idx == VK_ATTACHMENT_UNUSED)
940 return;
941
942 struct anv_render_pass_attachment *pass_att =
943 &cmd_buffer->state.pass->attachments[att_idx];
944 struct anv_attachment_state *att_state =
945 &cmd_buffer->state.attachments[att_idx];
946
947 uint32_t binding_table;
948 VkResult result =
949 binding_table_for_surface_state(cmd_buffer, att_state->color.state,
950 &binding_table);
951 if (result != VK_SUCCESS)
952 return;
953
954 union isl_color_value clear_color =
955 vk_to_isl_color(attachment->clearValue.color);
956
957 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
958 if (subpass->view_mask) {
959 uint32_t view_idx;
960 for_each_bit(view_idx, subpass->view_mask) {
961 for (uint32_t r = 0; r < rectCount; ++r) {
962 const VkOffset2D offset = pRects[r].rect.offset;
963 const VkExtent2D extent = pRects[r].rect.extent;
964 blorp_clear_attachments(batch, binding_table,
965 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
966 view_idx, 1,
967 offset.x, offset.y,
968 offset.x + extent.width,
969 offset.y + extent.height,
970 true, clear_color, false, 0.0f, 0, 0);
971 }
972 }
973 return;
974 }
975
976 for (uint32_t r = 0; r < rectCount; ++r) {
977 const VkOffset2D offset = pRects[r].rect.offset;
978 const VkExtent2D extent = pRects[r].rect.extent;
979 blorp_clear_attachments(batch, binding_table,
980 ISL_FORMAT_UNSUPPORTED, pass_att->samples,
981 pRects[r].baseArrayLayer,
982 pRects[r].layerCount,
983 offset.x, offset.y,
984 offset.x + extent.width, offset.y + extent.height,
985 true, clear_color, false, 0.0f, 0, 0);
986 }
987 }
988
989 static void
990 clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
991 struct blorp_batch *batch,
992 const VkClearAttachment *attachment,
993 uint32_t rectCount, const VkClearRect *pRects)
994 {
995 static const union isl_color_value color_value = { .u32 = { 0, } };
996 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
997 const uint32_t att_idx = subpass->depth_stencil_attachment.attachment;
998
999 if (att_idx == VK_ATTACHMENT_UNUSED)
1000 return;
1001
1002 struct anv_render_pass_attachment *pass_att =
1003 &cmd_buffer->state.pass->attachments[att_idx];
1004
1005 bool clear_depth = attachment->aspectMask & VK_IMAGE_ASPECT_DEPTH_BIT;
1006 bool clear_stencil = attachment->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
1007
1008 enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
1009 if (clear_depth) {
1010 depth_format = anv_get_isl_format(&cmd_buffer->device->info,
1011 pass_att->format,
1012 VK_IMAGE_ASPECT_DEPTH_BIT,
1013 VK_IMAGE_TILING_OPTIMAL);
1014 }
1015
1016 uint32_t binding_table;
1017 VkResult result =
1018 binding_table_for_surface_state(cmd_buffer,
1019 cmd_buffer->state.null_surface_state,
1020 &binding_table);
1021 if (result != VK_SUCCESS)
1022 return;
1023
1024 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1025 if (subpass->view_mask) {
1026 uint32_t view_idx;
1027 for_each_bit(view_idx, subpass->view_mask) {
1028 for (uint32_t r = 0; r < rectCount; ++r) {
1029 const VkOffset2D offset = pRects[r].rect.offset;
1030 const VkExtent2D extent = pRects[r].rect.extent;
1031 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1032 blorp_clear_attachments(batch, binding_table,
1033 depth_format, pass_att->samples,
1034 view_idx, 1,
1035 offset.x, offset.y,
1036 offset.x + extent.width,
1037 offset.y + extent.height,
1038 false, color_value,
1039 clear_depth, value.depth,
1040 clear_stencil ? 0xff : 0, value.stencil);
1041 }
1042 }
1043 return;
1044 }
1045
1046 for (uint32_t r = 0; r < rectCount; ++r) {
1047 const VkOffset2D offset = pRects[r].rect.offset;
1048 const VkExtent2D extent = pRects[r].rect.extent;
1049 VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
1050 blorp_clear_attachments(batch, binding_table,
1051 depth_format, pass_att->samples,
1052 pRects[r].baseArrayLayer,
1053 pRects[r].layerCount,
1054 offset.x, offset.y,
1055 offset.x + extent.width, offset.y + extent.height,
1056 false, color_value,
1057 clear_depth, value.depth,
1058 clear_stencil ? 0xff : 0, value.stencil);
1059 }
1060 }
1061
1062 void anv_CmdClearAttachments(
1063 VkCommandBuffer commandBuffer,
1064 uint32_t attachmentCount,
1065 const VkClearAttachment* pAttachments,
1066 uint32_t rectCount,
1067 const VkClearRect* pRects)
1068 {
1069 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1070
1071 /* Because this gets called within a render pass, we tell blorp not to
1072 * trash our depth and stencil buffers.
1073 */
1074 struct blorp_batch batch;
1075 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1076 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1077
1078 for (uint32_t a = 0; a < attachmentCount; ++a) {
1079 if (pAttachments[a].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1080 assert(pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
1081 clear_color_attachment(cmd_buffer, &batch,
1082 &pAttachments[a],
1083 rectCount, pRects);
1084 } else {
1085 clear_depth_stencil_attachment(cmd_buffer, &batch,
1086 &pAttachments[a],
1087 rectCount, pRects);
1088 }
1089 }
1090
1091 blorp_batch_finish(&batch);
1092 }
1093
1094 enum subpass_stage {
1095 SUBPASS_STAGE_LOAD,
1096 SUBPASS_STAGE_DRAW,
1097 SUBPASS_STAGE_RESOLVE,
1098 };
1099
1100 static bool
1101 subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
1102 {
1103 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1104 uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1105
1106 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1107 uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1108 if (a == VK_ATTACHMENT_UNUSED)
1109 continue;
1110
1111 assert(a < cmd_state->pass->attachment_count);
1112 if (cmd_state->attachments[a].pending_clear_aspects) {
1113 return true;
1114 }
1115 }
1116
1117 if (ds != VK_ATTACHMENT_UNUSED) {
1118 assert(ds < cmd_state->pass->attachment_count);
1119 if (cmd_state->attachments[ds].pending_clear_aspects)
1120 return true;
1121 }
1122
1123 return false;
1124 }
1125
1126 void
1127 anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer)
1128 {
1129 const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
1130 const VkRect2D render_area = cmd_buffer->state.render_area;
1131
1132
1133 if (!subpass_needs_clear(cmd_buffer))
1134 return;
1135
1136 /* Because this gets called within a render pass, we tell blorp not to
1137 * trash our depth and stencil buffers.
1138 */
1139 struct blorp_batch batch;
1140 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1141 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
1142
1143 VkClearRect clear_rect = {
1144 .rect = cmd_buffer->state.render_area,
1145 .baseArrayLayer = 0,
1146 .layerCount = cmd_buffer->state.framebuffer->layers,
1147 };
1148
1149 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1150 for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
1151 const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
1152 if (a == VK_ATTACHMENT_UNUSED)
1153 continue;
1154
1155 assert(a < cmd_state->pass->attachment_count);
1156 struct anv_attachment_state *att_state = &cmd_state->attachments[a];
1157
1158 if (!att_state->pending_clear_aspects)
1159 continue;
1160
1161 assert(att_state->pending_clear_aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1162
1163 struct anv_image_view *iview = fb->attachments[a];
1164 const struct anv_image *image = iview->image;
1165 struct blorp_surf surf;
1166 get_blorp_surf_for_anv_image(cmd_buffer->device,
1167 image, VK_IMAGE_ASPECT_COLOR_BIT,
1168 att_state->aux_usage, &surf);
1169
1170 if (att_state->fast_clear) {
1171 surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
1172
1173 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1174 *
1175 * "After Render target fast clear, pipe-control with color cache
1176 * write-flush must be issued before sending any DRAW commands on
1177 * that render target."
1178 *
1179 * This comment is a bit cryptic and doesn't really tell you what's
1180 * going or what's really needed. It appears that fast clear ops are
1181 * not properly synchronized with other drawing. This means that we
1182 * cannot have a fast clear operation in the pipe at the same time as
1183 * other regular drawing operations. We need to use a PIPE_CONTROL
1184 * to ensure that the contents of the previous draw hit the render
1185 * target before we resolve and then use a second PIPE_CONTROL after
1186 * the resolve to ensure that it is completed before any additional
1187 * drawing occurs.
1188 */
1189 cmd_buffer->state.pending_pipe_bits |=
1190 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1191
1192 assert(image->n_planes == 1);
1193 blorp_fast_clear(&batch, &surf, iview->planes[0].isl.format,
1194 iview->planes[0].isl.base_level,
1195 iview->planes[0].isl.base_array_layer, fb->layers,
1196 render_area.offset.x, render_area.offset.y,
1197 render_area.offset.x + render_area.extent.width,
1198 render_area.offset.y + render_area.extent.height);
1199
1200 cmd_buffer->state.pending_pipe_bits |=
1201 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1202 } else {
1203 assert(image->n_planes == 1);
1204 blorp_clear(&batch, &surf, iview->planes[0].isl.format,
1205 anv_swizzle_for_render(iview->planes[0].isl.swizzle),
1206 iview->planes[0].isl.base_level,
1207 iview->planes[0].isl.base_array_layer, fb->layers,
1208 render_area.offset.x, render_area.offset.y,
1209 render_area.offset.x + render_area.extent.width,
1210 render_area.offset.y + render_area.extent.height,
1211 vk_to_isl_color(att_state->clear_value.color), NULL);
1212 }
1213
1214 att_state->pending_clear_aspects = 0;
1215 }
1216
1217 const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
1218 assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
1219
1220 if (ds != VK_ATTACHMENT_UNUSED &&
1221 cmd_state->attachments[ds].pending_clear_aspects) {
1222
1223 VkClearAttachment clear_att = {
1224 .aspectMask = cmd_state->attachments[ds].pending_clear_aspects,
1225 .clearValue = cmd_state->attachments[ds].clear_value,
1226 };
1227
1228
1229 const uint8_t gen = cmd_buffer->device->info.gen;
1230 bool clear_with_hiz = gen >= 8 && cmd_state->attachments[ds].aux_usage ==
1231 ISL_AUX_USAGE_HIZ;
1232 const struct anv_image_view *iview = fb->attachments[ds];
1233
1234 if (clear_with_hiz) {
1235 const bool clear_depth = clear_att.aspectMask &
1236 VK_IMAGE_ASPECT_DEPTH_BIT;
1237 const bool clear_stencil = clear_att.aspectMask &
1238 VK_IMAGE_ASPECT_STENCIL_BIT;
1239
1240 /* Check against restrictions for depth buffer clearing. A great GPU
1241 * performance benefit isn't expected when using the HZ sequence for
1242 * stencil-only clears. Therefore, we don't emit a HZ op sequence for
1243 * a stencil clear in addition to using the BLORP-fallback for depth.
1244 */
1245 if (clear_depth) {
1246 if (!blorp_can_hiz_clear_depth(gen, iview->planes[0].isl.format,
1247 iview->image->samples,
1248 render_area.offset.x,
1249 render_area.offset.y,
1250 render_area.offset.x +
1251 render_area.extent.width,
1252 render_area.offset.y +
1253 render_area.extent.height)) {
1254 clear_with_hiz = false;
1255 } else if (clear_att.clearValue.depthStencil.depth !=
1256 ANV_HZ_FC_VAL) {
1257 /* Don't enable fast depth clears for any color not equal to
1258 * ANV_HZ_FC_VAL.
1259 */
1260 clear_with_hiz = false;
1261 } else if (gen == 8 &&
1262 anv_can_sample_with_hiz(&cmd_buffer->device->info,
1263 iview->image)) {
1264 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
1265 * fast-cleared portion of a HiZ buffer. Testing has revealed
1266 * that Gen8 only supports returning 0.0f. Gens prior to gen8 do
1267 * not support this feature at all.
1268 */
1269 clear_with_hiz = false;
1270 }
1271 }
1272
1273 if (clear_with_hiz) {
1274 blorp_gen8_hiz_clear_attachments(&batch, iview->image->samples,
1275 render_area.offset.x,
1276 render_area.offset.y,
1277 render_area.offset.x +
1278 render_area.extent.width,
1279 render_area.offset.y +
1280 render_area.extent.height,
1281 clear_depth, clear_stencil,
1282 clear_att.clearValue.
1283 depthStencil.stencil);
1284
1285 /* From the SKL PRM, Depth Buffer Clear:
1286 *
1287 * Depth Buffer Clear Workaround
1288 * Depth buffer clear pass using any of the methods (WM_STATE,
1289 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
1290 * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
1291 * “set” before starting to render. DepthStall and DepthFlush are
1292 * not needed between consecutive depth clear passes nor is it
1293 * required if the depth-clear pass was done with “full_surf_clear”
1294 * bit set in the 3DSTATE_WM_HZ_OP.
1295 */
1296 if (clear_depth) {
1297 cmd_buffer->state.pending_pipe_bits |=
1298 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
1299 }
1300 }
1301 }
1302
1303 if (!clear_with_hiz) {
1304 clear_depth_stencil_attachment(cmd_buffer, &batch,
1305 &clear_att, 1, &clear_rect);
1306 }
1307
1308 cmd_state->attachments[ds].pending_clear_aspects = 0;
1309 }
1310
1311 blorp_batch_finish(&batch);
1312 }
1313
1314 static void
1315 resolve_surface(struct blorp_batch *batch,
1316 struct blorp_surf *src_surf,
1317 uint32_t src_level, uint32_t src_layer,
1318 struct blorp_surf *dst_surf,
1319 uint32_t dst_level, uint32_t dst_layer,
1320 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1321 uint32_t width, uint32_t height)
1322 {
1323 blorp_blit(batch,
1324 src_surf, src_level, src_layer,
1325 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1326 dst_surf, dst_level, dst_layer,
1327 ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
1328 src_x, src_y, src_x + width, src_y + height,
1329 dst_x, dst_y, dst_x + width, dst_y + height,
1330 0x2600 /* GL_NEAREST */, false, false);
1331 }
1332
1333 static void
1334 resolve_image(struct anv_device *device,
1335 struct blorp_batch *batch,
1336 const struct anv_image *src_image,
1337 uint32_t src_level, uint32_t src_layer,
1338 const struct anv_image *dst_image,
1339 uint32_t dst_level, uint32_t dst_layer,
1340 VkImageAspectFlags aspect_mask,
1341 uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
1342 uint32_t width, uint32_t height)
1343 {
1344 assert(src_image->type == VK_IMAGE_TYPE_2D);
1345 assert(src_image->samples > 1);
1346 assert(dst_image->type == VK_IMAGE_TYPE_2D);
1347 assert(dst_image->samples == 1);
1348 assert(src_image->n_planes == dst_image->n_planes);
1349
1350 uint32_t aspect_bit;
1351
1352 anv_foreach_image_aspect_bit(aspect_bit, src_image, aspect_mask) {
1353 struct blorp_surf src_surf, dst_surf;
1354 get_blorp_surf_for_anv_image(device, src_image, 1UL << aspect_bit,
1355 ANV_AUX_USAGE_DEFAULT, &src_surf);
1356 get_blorp_surf_for_anv_image(device, dst_image, 1UL << aspect_bit,
1357 ANV_AUX_USAGE_DEFAULT, &dst_surf);
1358
1359 assert(!src_image->format->can_ycbcr);
1360 assert(!dst_image->format->can_ycbcr);
1361
1362 resolve_surface(batch,
1363 &src_surf, src_level, src_layer,
1364 &dst_surf, dst_level, dst_layer,
1365 src_x, src_y, dst_x, dst_y, width, height);
1366 }
1367 }
1368
1369 void anv_CmdResolveImage(
1370 VkCommandBuffer commandBuffer,
1371 VkImage srcImage,
1372 VkImageLayout srcImageLayout,
1373 VkImage dstImage,
1374 VkImageLayout dstImageLayout,
1375 uint32_t regionCount,
1376 const VkImageResolve* pRegions)
1377 {
1378 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1379 ANV_FROM_HANDLE(anv_image, src_image, srcImage);
1380 ANV_FROM_HANDLE(anv_image, dst_image, dstImage);
1381
1382 struct blorp_batch batch;
1383 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1384
1385 for (uint32_t r = 0; r < regionCount; r++) {
1386 assert(pRegions[r].srcSubresource.aspectMask ==
1387 pRegions[r].dstSubresource.aspectMask);
1388 assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
1389 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
1390
1391 const uint32_t layer_count =
1392 anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
1393
1394 VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask,
1395 dst_mask = pRegions[r].dstSubresource.aspectMask;
1396
1397 assert(anv_image_aspects_compatible(src_mask, dst_mask));
1398
1399 for (uint32_t layer = 0; layer < layer_count; layer++) {
1400 resolve_image(cmd_buffer->device, &batch,
1401 src_image,
1402 pRegions[r].srcSubresource.mipLevel,
1403 pRegions[r].srcSubresource.baseArrayLayer + layer,
1404 dst_image,
1405 pRegions[r].dstSubresource.mipLevel,
1406 pRegions[r].dstSubresource.baseArrayLayer + layer,
1407 pRegions[r].dstSubresource.aspectMask,
1408 pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
1409 pRegions[r].dstOffset.x, pRegions[r].dstOffset.y,
1410 pRegions[r].extent.width, pRegions[r].extent.height);
1411 }
1412 }
1413
1414 blorp_batch_finish(&batch);
1415 }
1416
1417 static enum isl_aux_usage
1418 fast_clear_aux_usage(const struct anv_image *image,
1419 VkImageAspectFlagBits aspect)
1420 {
1421 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1422 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
1423 return ISL_AUX_USAGE_CCS_D;
1424 else
1425 return image->planes[plane].aux_usage;
1426 }
1427
1428 void
1429 anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
1430 const struct anv_image *image,
1431 VkImageAspectFlagBits aspect,
1432 const uint32_t base_level, const uint32_t level_count,
1433 const uint32_t base_layer, uint32_t layer_count)
1434 {
1435 assert(image->type == VK_IMAGE_TYPE_3D || image->extent.depth == 1);
1436
1437 if (image->type == VK_IMAGE_TYPE_3D) {
1438 assert(base_layer == 0);
1439 assert(layer_count == anv_minify(image->extent.depth, base_level));
1440 }
1441
1442 struct blorp_batch batch;
1443 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1444
1445 struct blorp_surf surf;
1446 get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
1447 fast_clear_aux_usage(image, aspect),
1448 &surf);
1449
1450 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1451 *
1452 * "After Render target fast clear, pipe-control with color cache
1453 * write-flush must be issued before sending any DRAW commands on
1454 * that render target."
1455 *
1456 * This comment is a bit cryptic and doesn't really tell you what's going
1457 * or what's really needed. It appears that fast clear ops are not
1458 * properly synchronized with other drawing. This means that we cannot
1459 * have a fast clear operation in the pipe at the same time as other
1460 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1461 * that the contents of the previous draw hit the render target before we
1462 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1463 * that it is completed before any additional drawing occurs.
1464 */
1465 cmd_buffer->state.pending_pipe_bits |=
1466 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1467
1468 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1469 uint32_t width_div = image->format->planes[plane].denominator_scales[0];
1470 uint32_t height_div = image->format->planes[plane].denominator_scales[1];
1471
1472 for (uint32_t l = 0; l < level_count; l++) {
1473 const uint32_t level = base_level + l;
1474
1475 const VkExtent3D extent = {
1476 .width = anv_minify(image->extent.width, level),
1477 .height = anv_minify(image->extent.height, level),
1478 .depth = anv_minify(image->extent.depth, level),
1479 };
1480
1481 if (image->type == VK_IMAGE_TYPE_3D)
1482 layer_count = extent.depth;
1483
1484 assert(level < anv_image_aux_levels(image, aspect));
1485 assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level));
1486 blorp_fast_clear(&batch, &surf, surf.surf->format,
1487 level, base_layer, layer_count,
1488 0, 0,
1489 extent.width / width_div,
1490 extent.height / height_div);
1491 }
1492
1493 cmd_buffer->state.pending_pipe_bits |=
1494 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
1495 }
1496
1497 void
1498 anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer)
1499 {
1500 struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
1501 struct anv_subpass *subpass = cmd_buffer->state.subpass;
1502
1503 if (subpass->has_resolve) {
1504 struct blorp_batch batch;
1505 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1506
1507 /* We are about to do some MSAA resolves. We need to flush so that the
1508 * result of writes to the MSAA color attachments show up in the sampler
1509 * when we blit to the single-sampled resolve target.
1510 */
1511 cmd_buffer->state.pending_pipe_bits |=
1512 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
1513 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
1514
1515 for (uint32_t i = 0; i < subpass->color_count; ++i) {
1516 uint32_t src_att = subpass->color_attachments[i].attachment;
1517 uint32_t dst_att = subpass->resolve_attachments[i].attachment;
1518
1519 if (dst_att == VK_ATTACHMENT_UNUSED)
1520 continue;
1521
1522 assert(src_att < cmd_buffer->state.pass->attachment_count);
1523 assert(dst_att < cmd_buffer->state.pass->attachment_count);
1524
1525 if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
1526 /* From the Vulkan 1.0 spec:
1527 *
1528 * If the first use of an attachment in a render pass is as a
1529 * resolve attachment, then the loadOp is effectively ignored
1530 * as the resolve is guaranteed to overwrite all pixels in the
1531 * render area.
1532 */
1533 cmd_buffer->state.attachments[dst_att].pending_clear_aspects = 0;
1534 }
1535
1536 struct anv_image_view *src_iview = fb->attachments[src_att];
1537 struct anv_image_view *dst_iview = fb->attachments[dst_att];
1538
1539 enum isl_aux_usage src_aux_usage =
1540 cmd_buffer->state.attachments[src_att].aux_usage;
1541 enum isl_aux_usage dst_aux_usage =
1542 cmd_buffer->state.attachments[dst_att].aux_usage;
1543
1544 const VkRect2D render_area = cmd_buffer->state.render_area;
1545
1546 assert(src_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
1547 dst_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT);
1548
1549 struct blorp_surf src_surf, dst_surf;
1550 get_blorp_surf_for_anv_image(cmd_buffer->device, src_iview->image,
1551 VK_IMAGE_ASPECT_COLOR_BIT,
1552 src_aux_usage, &src_surf);
1553 get_blorp_surf_for_anv_image(cmd_buffer->device, dst_iview->image,
1554 VK_IMAGE_ASPECT_COLOR_BIT,
1555 dst_aux_usage, &dst_surf);
1556
1557 assert(!src_iview->image->format->can_ycbcr);
1558 assert(!dst_iview->image->format->can_ycbcr);
1559
1560 resolve_surface(&batch,
1561 &src_surf,
1562 src_iview->planes[0].isl.base_level,
1563 src_iview->planes[0].isl.base_array_layer,
1564 &dst_surf,
1565 dst_iview->planes[0].isl.base_level,
1566 dst_iview->planes[0].isl.base_array_layer,
1567 render_area.offset.x, render_area.offset.y,
1568 render_area.offset.x, render_area.offset.y,
1569 render_area.extent.width, render_area.extent.height);
1570 }
1571
1572 blorp_batch_finish(&batch);
1573 }
1574 }
1575
1576 void
1577 anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
1578 const struct anv_image *image,
1579 uint32_t base_level, uint32_t level_count,
1580 uint32_t base_layer, uint32_t layer_count)
1581 {
1582 struct blorp_batch batch;
1583 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1584
1585 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT && image->n_planes == 1);
1586
1587 struct blorp_surf surf;
1588 get_blorp_surf_for_anv_image(cmd_buffer->device,
1589 image, VK_IMAGE_ASPECT_COLOR_BIT,
1590 ISL_AUX_USAGE_NONE, &surf);
1591
1592 struct blorp_surf shadow_surf = {
1593 .surf = &image->planes[0].shadow_surface.isl,
1594 .addr = {
1595 .buffer = image->planes[0].bo,
1596 .offset = image->planes[0].bo_offset +
1597 image->planes[0].shadow_surface.offset,
1598 },
1599 };
1600
1601 for (uint32_t l = 0; l < level_count; l++) {
1602 const uint32_t level = base_level + l;
1603
1604 const VkExtent3D extent = {
1605 .width = anv_minify(image->extent.width, level),
1606 .height = anv_minify(image->extent.height, level),
1607 .depth = anv_minify(image->extent.depth, level),
1608 };
1609
1610 if (image->type == VK_IMAGE_TYPE_3D)
1611 layer_count = extent.depth;
1612
1613 for (uint32_t a = 0; a < layer_count; a++) {
1614 const uint32_t layer = base_layer + a;
1615
1616 blorp_copy(&batch, &surf, level, layer,
1617 &shadow_surf, level, layer,
1618 0, 0, 0, 0, extent.width, extent.height);
1619 }
1620 }
1621
1622 blorp_batch_finish(&batch);
1623 }
1624
1625 void
1626 anv_gen8_hiz_op_resolve(struct anv_cmd_buffer *cmd_buffer,
1627 const struct anv_image *image,
1628 enum blorp_hiz_op op)
1629 {
1630 assert(image);
1631
1632 assert(anv_image_aspect_to_plane(image->aspects,
1633 VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
1634
1635 /* Don't resolve depth buffers without an auxiliary HiZ buffer and
1636 * don't perform such a resolve on gens that don't support it.
1637 */
1638 if (cmd_buffer->device->info.gen < 8 ||
1639 image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
1640 return;
1641
1642 assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
1643 op == BLORP_HIZ_OP_DEPTH_RESOLVE);
1644
1645 struct blorp_batch batch;
1646 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
1647
1648 struct blorp_surf surf;
1649 get_blorp_surf_for_anv_image(cmd_buffer->device,
1650 image, VK_IMAGE_ASPECT_DEPTH_BIT,
1651 ISL_AUX_USAGE_NONE, &surf);
1652
1653 /* Manually add the aux HiZ surf */
1654 surf.aux_surf = &image->planes[0].aux_surface.isl,
1655 surf.aux_addr = (struct blorp_address) {
1656 .buffer = image->planes[0].bo,
1657 .offset = image->planes[0].bo_offset +
1658 image->planes[0].aux_surface.offset,
1659 };
1660 surf.aux_usage = ISL_AUX_USAGE_HIZ;
1661
1662 surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
1663
1664 blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
1665 blorp_batch_finish(&batch);
1666 }
1667
1668 void
1669 anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
1670 const struct anv_state surface_state,
1671 const struct anv_image * const image,
1672 VkImageAspectFlagBits aspect,
1673 const uint8_t level, const uint32_t layer_count,
1674 const enum blorp_fast_clear_op op)
1675 {
1676 assert(cmd_buffer && image);
1677
1678 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1679
1680 /* The resolved subresource range must have a CCS buffer. */
1681 assert(level < anv_image_aux_levels(image, aspect));
1682 assert(layer_count <= anv_image_aux_layers(image, aspect, level));
1683 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV && image->samples == 1);
1684
1685 /* Create a binding table for this surface state. */
1686 uint32_t binding_table;
1687 VkResult result =
1688 binding_table_for_surface_state(cmd_buffer, surface_state,
1689 &binding_table);
1690 if (result != VK_SUCCESS)
1691 return;
1692
1693 struct blorp_batch batch;
1694 blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
1695 BLORP_BATCH_PREDICATE_ENABLE);
1696
1697 struct blorp_surf surf;
1698 get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
1699 fast_clear_aux_usage(image, aspect),
1700 &surf);
1701
1702 blorp_ccs_resolve_attachment(&batch, binding_table, &surf, level,
1703 layer_count,
1704 image->planes[plane].surface.isl.format,
1705 op);
1706
1707 blorp_batch_finish(&batch);
1708 }