2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "anv_private.h"
27 lookup_blorp_shader(struct blorp_batch
*batch
,
28 const void *key
, uint32_t key_size
,
29 uint32_t *kernel_out
, void *prog_data_out
)
31 struct blorp_context
*blorp
= batch
->blorp
;
32 struct anv_device
*device
= blorp
->driver_ctx
;
34 /* The default cache must be a real cache */
35 assert(device
->default_pipeline_cache
.cache
);
37 struct anv_shader_bin
*bin
=
38 anv_pipeline_cache_search(&device
->default_pipeline_cache
, key
, key_size
);
42 /* The cache already has a reference and it's not going anywhere so there
43 * is no need to hold a second reference.
45 anv_shader_bin_unref(device
, bin
);
47 *kernel_out
= bin
->kernel
.offset
;
48 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
54 upload_blorp_shader(struct blorp_batch
*batch
,
55 const void *key
, uint32_t key_size
,
56 const void *kernel
, uint32_t kernel_size
,
57 const struct brw_stage_prog_data
*prog_data
,
58 uint32_t prog_data_size
,
59 uint32_t *kernel_out
, void *prog_data_out
)
61 struct blorp_context
*blorp
= batch
->blorp
;
62 struct anv_device
*device
= blorp
->driver_ctx
;
64 /* The blorp cache must be a real cache */
65 assert(device
->default_pipeline_cache
.cache
);
67 struct anv_pipeline_bind_map bind_map
= {
72 struct anv_shader_bin
*bin
=
73 anv_pipeline_cache_upload_kernel(&device
->default_pipeline_cache
,
74 key
, key_size
, kernel
, kernel_size
,
76 prog_data
, prog_data_size
, &bind_map
);
81 /* The cache already has a reference and it's not going anywhere so there
82 * is no need to hold a second reference.
84 anv_shader_bin_unref(device
, bin
);
86 *kernel_out
= bin
->kernel
.offset
;
87 *(const struct brw_stage_prog_data
**)prog_data_out
= bin
->prog_data
;
93 anv_device_init_blorp(struct anv_device
*device
)
95 blorp_init(&device
->blorp
, device
, &device
->isl_dev
);
96 device
->blorp
.compiler
= device
->instance
->physicalDevice
.compiler
;
97 device
->blorp
.lookup_shader
= lookup_blorp_shader
;
98 device
->blorp
.upload_shader
= upload_blorp_shader
;
99 switch (device
->info
.gen
) {
101 if (device
->info
.is_haswell
) {
102 device
->blorp
.exec
= gen75_blorp_exec
;
104 device
->blorp
.exec
= gen7_blorp_exec
;
108 device
->blorp
.exec
= gen8_blorp_exec
;
111 device
->blorp
.exec
= gen9_blorp_exec
;
114 device
->blorp
.exec
= gen10_blorp_exec
;
117 device
->blorp
.exec
= gen11_blorp_exec
;
120 unreachable("Unknown hardware generation");
125 anv_device_finish_blorp(struct anv_device
*device
)
127 blorp_finish(&device
->blorp
);
131 get_blorp_surf_for_anv_buffer(struct anv_device
*device
,
132 struct anv_buffer
*buffer
, uint64_t offset
,
133 uint32_t width
, uint32_t height
,
134 uint32_t row_pitch
, enum isl_format format
,
135 struct blorp_surf
*blorp_surf
,
136 struct isl_surf
*isl_surf
)
138 const struct isl_format_layout
*fmtl
=
139 isl_format_get_layout(format
);
142 /* ASTC is the only format which doesn't support linear layouts.
143 * Create an equivalently sized surface with ISL to get around this.
145 if (fmtl
->txc
== ISL_TXC_ASTC
) {
146 /* Use an equivalently sized format */
147 format
= ISL_FORMAT_R32G32B32A32_UINT
;
148 assert(fmtl
->bpb
== isl_format_get_layout(format
)->bpb
);
150 /* Shrink the dimensions for the new format */
151 width
= DIV_ROUND_UP(width
, fmtl
->bw
);
152 height
= DIV_ROUND_UP(height
, fmtl
->bh
);
155 *blorp_surf
= (struct blorp_surf
) {
158 .buffer
= buffer
->address
.bo
,
159 .offset
= buffer
->address
.offset
+ offset
,
160 .mocs
= anv_mocs_for_bo(device
, buffer
->address
.bo
),
164 ok
= isl_surf_init(&device
->isl_dev
, isl_surf
,
165 .dim
= ISL_SURF_DIM_2D
,
173 .row_pitch_B
= row_pitch
,
174 .usage
= ISL_SURF_USAGE_TEXTURE_BIT
|
175 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
176 .tiling_flags
= ISL_TILING_LINEAR_BIT
);
180 /* Pick something high enough that it won't be used in core and low enough it
181 * will never map to an extension.
183 #define ANV_IMAGE_LAYOUT_EXPLICIT_AUX (VkImageLayout)10000000
185 static struct blorp_address
186 anv_to_blorp_address(struct anv_address addr
)
188 return (struct blorp_address
) {
190 .offset
= addr
.offset
,
195 get_blorp_surf_for_anv_image(const struct anv_device
*device
,
196 const struct anv_image
*image
,
197 VkImageAspectFlags aspect
,
198 VkImageLayout layout
,
199 enum isl_aux_usage aux_usage
,
200 struct blorp_surf
*blorp_surf
)
202 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
204 if (layout
!= ANV_IMAGE_LAYOUT_EXPLICIT_AUX
)
205 aux_usage
= anv_layout_to_aux_usage(&device
->info
, image
, aspect
, layout
);
207 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
;
208 *blorp_surf
= (struct blorp_surf
) {
209 .surf
= &surface
->isl
,
211 .buffer
= image
->planes
[plane
].address
.bo
,
212 .offset
= image
->planes
[plane
].address
.offset
+ surface
->offset
,
213 .mocs
= anv_mocs_for_bo(device
, image
->planes
[plane
].address
.bo
),
217 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
218 const struct anv_surface
*aux_surface
= &image
->planes
[plane
].aux_surface
;
219 blorp_surf
->aux_surf
= &aux_surface
->isl
,
220 blorp_surf
->aux_addr
= (struct blorp_address
) {
221 .buffer
= image
->planes
[plane
].address
.bo
,
222 .offset
= image
->planes
[plane
].address
.offset
+ aux_surface
->offset
,
223 .mocs
= anv_mocs_for_bo(device
, image
->planes
[plane
].address
.bo
),
225 blorp_surf
->aux_usage
= aux_usage
;
227 /* If we're doing a partial resolve, then we need the indirect clear
228 * color. If we are doing a fast clear and want to store/update the
229 * clear color, we also pass the address to blorp, otherwise it will only
230 * stomp the CCS to a particular value and won't care about format or
233 if (aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
234 const struct anv_address clear_color_addr
=
235 anv_image_get_clear_color_addr(device
, image
, aspect
);
236 blorp_surf
->clear_color_addr
= anv_to_blorp_address(clear_color_addr
);
237 } else if (aspect
& VK_IMAGE_ASPECT_DEPTH_BIT
238 && device
->info
.gen
>= 10) {
239 /* Vulkan always clears to 1.0. On gen < 10, we set that directly in
240 * the state packet. For gen >= 10, must provide the clear value in a
241 * buffer. We have a single global buffer that stores the 1.0 value.
243 const struct anv_address clear_color_addr
= (struct anv_address
) {
244 .bo
= (struct anv_bo
*)&device
->hiz_clear_bo
246 blorp_surf
->clear_color_addr
= anv_to_blorp_address(clear_color_addr
);
251 void anv_CmdCopyImage(
252 VkCommandBuffer commandBuffer
,
254 VkImageLayout srcImageLayout
,
256 VkImageLayout dstImageLayout
,
257 uint32_t regionCount
,
258 const VkImageCopy
* pRegions
)
260 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
261 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
262 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
264 struct blorp_batch batch
;
265 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
267 for (unsigned r
= 0; r
< regionCount
; r
++) {
268 VkOffset3D srcOffset
=
269 anv_sanitize_image_offset(src_image
->type
, pRegions
[r
].srcOffset
);
270 VkOffset3D dstOffset
=
271 anv_sanitize_image_offset(dst_image
->type
, pRegions
[r
].dstOffset
);
273 anv_sanitize_image_extent(src_image
->type
, pRegions
[r
].extent
);
275 const uint32_t dst_level
= pRegions
[r
].dstSubresource
.mipLevel
;
276 unsigned dst_base_layer
, layer_count
;
277 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
278 dst_base_layer
= pRegions
[r
].dstOffset
.z
;
279 layer_count
= pRegions
[r
].extent
.depth
;
281 dst_base_layer
= pRegions
[r
].dstSubresource
.baseArrayLayer
;
283 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
);
286 const uint32_t src_level
= pRegions
[r
].srcSubresource
.mipLevel
;
287 unsigned src_base_layer
;
288 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
289 src_base_layer
= pRegions
[r
].srcOffset
.z
;
291 src_base_layer
= pRegions
[r
].srcSubresource
.baseArrayLayer
;
292 assert(layer_count
==
293 anv_get_layerCount(src_image
, &pRegions
[r
].srcSubresource
));
296 VkImageAspectFlags src_mask
= pRegions
[r
].srcSubresource
.aspectMask
,
297 dst_mask
= pRegions
[r
].dstSubresource
.aspectMask
;
299 assert(anv_image_aspects_compatible(src_mask
, dst_mask
));
301 if (util_bitcount(src_mask
) > 1) {
303 anv_foreach_image_aspect_bit(aspect_bit
, src_image
, src_mask
) {
304 struct blorp_surf src_surf
, dst_surf
;
305 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
306 src_image
, 1UL << aspect_bit
,
307 srcImageLayout
, ISL_AUX_USAGE_NONE
,
309 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
310 dst_image
, 1UL << aspect_bit
,
311 dstImageLayout
, ISL_AUX_USAGE_NONE
,
313 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
315 dst_surf
.aux_usage
, dst_level
,
316 dst_base_layer
, layer_count
);
318 for (unsigned i
= 0; i
< layer_count
; i
++) {
319 blorp_copy(&batch
, &src_surf
, src_level
, src_base_layer
+ i
,
320 &dst_surf
, dst_level
, dst_base_layer
+ i
,
321 srcOffset
.x
, srcOffset
.y
,
322 dstOffset
.x
, dstOffset
.y
,
323 extent
.width
, extent
.height
);
327 struct blorp_surf src_surf
, dst_surf
;
328 get_blorp_surf_for_anv_image(cmd_buffer
->device
, src_image
, src_mask
,
329 srcImageLayout
, ISL_AUX_USAGE_NONE
,
331 get_blorp_surf_for_anv_image(cmd_buffer
->device
, dst_image
, dst_mask
,
332 dstImageLayout
, ISL_AUX_USAGE_NONE
,
334 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
, dst_mask
,
335 dst_surf
.aux_usage
, dst_level
,
336 dst_base_layer
, layer_count
);
338 for (unsigned i
= 0; i
< layer_count
; i
++) {
339 blorp_copy(&batch
, &src_surf
, src_level
, src_base_layer
+ i
,
340 &dst_surf
, dst_level
, dst_base_layer
+ i
,
341 srcOffset
.x
, srcOffset
.y
,
342 dstOffset
.x
, dstOffset
.y
,
343 extent
.width
, extent
.height
);
348 blorp_batch_finish(&batch
);
352 copy_buffer_to_image(struct anv_cmd_buffer
*cmd_buffer
,
353 struct anv_buffer
*anv_buffer
,
354 struct anv_image
*anv_image
,
355 VkImageLayout image_layout
,
356 uint32_t regionCount
,
357 const VkBufferImageCopy
* pRegions
,
358 bool buffer_to_image
)
360 struct blorp_batch batch
;
361 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
364 struct blorp_surf surf
;
367 } image
, buffer
, *src
, *dst
;
370 buffer
.offset
= (VkOffset3D
) { 0, 0, 0 };
372 if (buffer_to_image
) {
380 for (unsigned r
= 0; r
< regionCount
; r
++) {
381 const VkImageAspectFlags aspect
= pRegions
[r
].imageSubresource
.aspectMask
;
383 get_blorp_surf_for_anv_image(cmd_buffer
->device
, anv_image
, aspect
,
384 image_layout
, ISL_AUX_USAGE_NONE
,
387 anv_sanitize_image_offset(anv_image
->type
, pRegions
[r
].imageOffset
);
388 image
.level
= pRegions
[r
].imageSubresource
.mipLevel
;
391 anv_sanitize_image_extent(anv_image
->type
, pRegions
[r
].imageExtent
);
392 if (anv_image
->type
!= VK_IMAGE_TYPE_3D
) {
393 image
.offset
.z
= pRegions
[r
].imageSubresource
.baseArrayLayer
;
395 anv_get_layerCount(anv_image
, &pRegions
[r
].imageSubresource
);
398 const enum isl_format buffer_format
=
399 anv_get_isl_format(&cmd_buffer
->device
->info
, anv_image
->vk_format
,
400 aspect
, VK_IMAGE_TILING_LINEAR
);
402 const VkExtent3D bufferImageExtent
= {
403 .width
= pRegions
[r
].bufferRowLength
?
404 pRegions
[r
].bufferRowLength
: extent
.width
,
405 .height
= pRegions
[r
].bufferImageHeight
?
406 pRegions
[r
].bufferImageHeight
: extent
.height
,
409 const struct isl_format_layout
*buffer_fmtl
=
410 isl_format_get_layout(buffer_format
);
412 const uint32_t buffer_row_pitch
=
413 DIV_ROUND_UP(bufferImageExtent
.width
, buffer_fmtl
->bw
) *
414 (buffer_fmtl
->bpb
/ 8);
416 const uint32_t buffer_layer_stride
=
417 DIV_ROUND_UP(bufferImageExtent
.height
, buffer_fmtl
->bh
) *
420 struct isl_surf buffer_isl_surf
;
421 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
422 anv_buffer
, pRegions
[r
].bufferOffset
,
423 extent
.width
, extent
.height
,
424 buffer_row_pitch
, buffer_format
,
425 &buffer
.surf
, &buffer_isl_surf
);
428 anv_cmd_buffer_mark_image_written(cmd_buffer
, anv_image
,
429 aspect
, dst
->surf
.aux_usage
,
431 dst
->offset
.z
, extent
.depth
);
434 for (unsigned z
= 0; z
< extent
.depth
; z
++) {
435 blorp_copy(&batch
, &src
->surf
, src
->level
, src
->offset
.z
,
436 &dst
->surf
, dst
->level
, dst
->offset
.z
,
437 src
->offset
.x
, src
->offset
.y
, dst
->offset
.x
, dst
->offset
.y
,
438 extent
.width
, extent
.height
);
441 buffer
.surf
.addr
.offset
+= buffer_layer_stride
;
445 blorp_batch_finish(&batch
);
448 void anv_CmdCopyBufferToImage(
449 VkCommandBuffer commandBuffer
,
452 VkImageLayout dstImageLayout
,
453 uint32_t regionCount
,
454 const VkBufferImageCopy
* pRegions
)
456 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
457 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
458 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
460 copy_buffer_to_image(cmd_buffer
, src_buffer
, dst_image
, dstImageLayout
,
461 regionCount
, pRegions
, true);
464 void anv_CmdCopyImageToBuffer(
465 VkCommandBuffer commandBuffer
,
467 VkImageLayout srcImageLayout
,
469 uint32_t regionCount
,
470 const VkBufferImageCopy
* pRegions
)
472 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
473 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
474 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
476 copy_buffer_to_image(cmd_buffer
, dst_buffer
, src_image
, srcImageLayout
,
477 regionCount
, pRegions
, false);
481 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
485 unsigned tmp
= *src0
;
492 unsigned tmp
= *dst0
;
501 void anv_CmdBlitImage(
502 VkCommandBuffer commandBuffer
,
504 VkImageLayout srcImageLayout
,
506 VkImageLayout dstImageLayout
,
507 uint32_t regionCount
,
508 const VkImageBlit
* pRegions
,
512 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
513 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
514 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
516 struct blorp_surf src
, dst
;
518 enum blorp_filter blorp_filter
;
520 case VK_FILTER_NEAREST
:
521 blorp_filter
= BLORP_FILTER_NEAREST
;
523 case VK_FILTER_LINEAR
:
524 blorp_filter
= BLORP_FILTER_BILINEAR
;
527 unreachable("Invalid filter");
530 struct blorp_batch batch
;
531 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
533 for (unsigned r
= 0; r
< regionCount
; r
++) {
534 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
535 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
537 assert(anv_image_aspects_compatible(src_res
->aspectMask
,
538 dst_res
->aspectMask
));
541 anv_foreach_image_aspect_bit(aspect_bit
, src_image
, src_res
->aspectMask
) {
542 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
543 src_image
, 1U << aspect_bit
,
544 srcImageLayout
, ISL_AUX_USAGE_NONE
, &src
);
545 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
546 dst_image
, 1U << aspect_bit
,
547 dstImageLayout
, ISL_AUX_USAGE_NONE
, &dst
);
549 struct anv_format_plane src_format
=
550 anv_get_format_plane(&cmd_buffer
->device
->info
, src_image
->vk_format
,
551 1U << aspect_bit
, src_image
->tiling
);
552 struct anv_format_plane dst_format
=
553 anv_get_format_plane(&cmd_buffer
->device
->info
, dst_image
->vk_format
,
554 1U << aspect_bit
, dst_image
->tiling
);
556 unsigned dst_start
, dst_end
;
557 if (dst_image
->type
== VK_IMAGE_TYPE_3D
) {
558 assert(dst_res
->baseArrayLayer
== 0);
559 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
560 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
562 dst_start
= dst_res
->baseArrayLayer
;
563 dst_end
= dst_start
+ anv_get_layerCount(dst_image
, dst_res
);
566 unsigned src_start
, src_end
;
567 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
568 assert(src_res
->baseArrayLayer
== 0);
569 src_start
= pRegions
[r
].srcOffsets
[0].z
;
570 src_end
= pRegions
[r
].srcOffsets
[1].z
;
572 src_start
= src_res
->baseArrayLayer
;
573 src_end
= src_start
+ anv_get_layerCount(src_image
, src_res
);
576 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
577 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
578 (float)(dst_end
+ 1 - dst_start
);
585 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
586 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
587 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
588 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
589 bool flip_x
= flip_coords(&src_x0
, &src_x1
, &dst_x0
, &dst_x1
);
591 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
592 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
593 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
594 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
595 bool flip_y
= flip_coords(&src_y0
, &src_y1
, &dst_y0
, &dst_y1
);
597 const unsigned num_layers
= dst_end
- dst_start
;
598 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
602 dst_start
, num_layers
);
604 for (unsigned i
= 0; i
< num_layers
; i
++) {
605 unsigned dst_z
= dst_start
+ i
;
606 unsigned src_z
= src_start
+ i
* src_z_step
;
608 blorp_blit(&batch
, &src
, src_res
->mipLevel
, src_z
,
609 src_format
.isl_format
, src_format
.swizzle
,
610 &dst
, dst_res
->mipLevel
, dst_z
,
611 dst_format
.isl_format
, dst_format
.swizzle
,
612 src_x0
, src_y0
, src_x1
, src_y1
,
613 dst_x0
, dst_y0
, dst_x1
, dst_y1
,
614 blorp_filter
, flip_x
, flip_y
);
619 blorp_batch_finish(&batch
);
622 static enum isl_format
623 isl_format_for_size(unsigned size_B
)
626 case 4: return ISL_FORMAT_R32_UINT
;
627 case 8: return ISL_FORMAT_R32G32_UINT
;
628 case 16: return ISL_FORMAT_R32G32B32A32_UINT
;
630 unreachable("Not a power-of-two format size");
635 * Returns the greatest common divisor of a and b that is a power of two.
638 gcd_pow2_u64(uint64_t a
, uint64_t b
)
640 assert(a
> 0 || b
> 0);
642 unsigned a_log2
= ffsll(a
) - 1;
643 unsigned b_log2
= ffsll(b
) - 1;
645 /* If either a or b is 0, then a_log2 or b_log2 till be UINT_MAX in which
646 * case, the MIN2() will take the other one. If both are 0 then we will
647 * hit the assert above.
649 return 1 << MIN2(a_log2
, b_log2
);
652 /* This is maximum possible width/height our HW can handle */
653 #define MAX_SURFACE_DIM (1ull << 14)
655 void anv_CmdCopyBuffer(
656 VkCommandBuffer commandBuffer
,
659 uint32_t regionCount
,
660 const VkBufferCopy
* pRegions
)
662 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
663 ANV_FROM_HANDLE(anv_buffer
, src_buffer
, srcBuffer
);
664 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
666 struct blorp_batch batch
;
667 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
669 for (unsigned r
= 0; r
< regionCount
; r
++) {
670 struct blorp_address src
= {
671 .buffer
= src_buffer
->address
.bo
,
672 .offset
= src_buffer
->address
.offset
+ pRegions
[r
].srcOffset
,
673 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, src_buffer
->address
.bo
),
675 struct blorp_address dst
= {
676 .buffer
= dst_buffer
->address
.bo
,
677 .offset
= dst_buffer
->address
.offset
+ pRegions
[r
].dstOffset
,
678 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, dst_buffer
->address
.bo
),
681 blorp_buffer_copy(&batch
, src
, dst
, pRegions
[r
].size
);
684 blorp_batch_finish(&batch
);
687 void anv_CmdUpdateBuffer(
688 VkCommandBuffer commandBuffer
,
690 VkDeviceSize dstOffset
,
691 VkDeviceSize dataSize
,
694 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
695 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
697 struct blorp_batch batch
;
698 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
700 /* We can't quite grab a full block because the state stream needs a
701 * little data at the top to build its linked list.
703 const uint32_t max_update_size
=
704 cmd_buffer
->device
->dynamic_state_pool
.block_size
- 64;
706 assert(max_update_size
< MAX_SURFACE_DIM
* 4);
708 /* We're about to read data that was written from the CPU. Flush the
709 * texture cache so we don't get anything stale.
711 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
714 const uint32_t copy_size
= MIN2(dataSize
, max_update_size
);
716 struct anv_state tmp_data
=
717 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, copy_size
, 64);
719 memcpy(tmp_data
.map
, pData
, copy_size
);
721 anv_state_flush(cmd_buffer
->device
, tmp_data
);
723 struct blorp_address src
= {
724 .buffer
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
725 .offset
= tmp_data
.offset
,
726 .mocs
= cmd_buffer
->device
->default_mocs
,
728 struct blorp_address dst
= {
729 .buffer
= dst_buffer
->address
.bo
,
730 .offset
= dst_buffer
->address
.offset
+ dstOffset
,
731 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
, dst_buffer
->address
.bo
),
734 blorp_buffer_copy(&batch
, src
, dst
, copy_size
);
736 dataSize
-= copy_size
;
737 dstOffset
+= copy_size
;
738 pData
= (void *)pData
+ copy_size
;
741 blorp_batch_finish(&batch
);
744 void anv_CmdFillBuffer(
745 VkCommandBuffer commandBuffer
,
747 VkDeviceSize dstOffset
,
748 VkDeviceSize fillSize
,
751 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
752 ANV_FROM_HANDLE(anv_buffer
, dst_buffer
, dstBuffer
);
753 struct blorp_surf surf
;
754 struct isl_surf isl_surf
;
756 struct blorp_batch batch
;
757 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
759 fillSize
= anv_buffer_get_range(dst_buffer
, dstOffset
, fillSize
);
761 /* From the Vulkan spec:
763 * "size is the number of bytes to fill, and must be either a multiple
764 * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
765 * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
766 * buffer is not a multiple of 4, then the nearest smaller multiple is
771 /* First, we compute the biggest format that can be used with the
772 * given offsets and size.
775 bs
= gcd_pow2_u64(bs
, dstOffset
);
776 bs
= gcd_pow2_u64(bs
, fillSize
);
777 enum isl_format isl_format
= isl_format_for_size(bs
);
779 union isl_color_value color
= {
780 .u32
= { data
, data
, data
, data
},
783 const uint64_t max_fill_size
= MAX_SURFACE_DIM
* MAX_SURFACE_DIM
* bs
;
784 while (fillSize
>= max_fill_size
) {
785 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
786 dst_buffer
, dstOffset
,
787 MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
788 MAX_SURFACE_DIM
* bs
, isl_format
,
791 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
792 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, MAX_SURFACE_DIM
,
794 fillSize
-= max_fill_size
;
795 dstOffset
+= max_fill_size
;
798 uint64_t height
= fillSize
/ (MAX_SURFACE_DIM
* bs
);
799 assert(height
< MAX_SURFACE_DIM
);
801 const uint64_t rect_fill_size
= height
* MAX_SURFACE_DIM
* bs
;
802 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
803 dst_buffer
, dstOffset
,
804 MAX_SURFACE_DIM
, height
,
805 MAX_SURFACE_DIM
* bs
, isl_format
,
808 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
809 0, 0, 1, 0, 0, MAX_SURFACE_DIM
, height
,
811 fillSize
-= rect_fill_size
;
812 dstOffset
+= rect_fill_size
;
816 const uint32_t width
= fillSize
/ bs
;
817 get_blorp_surf_for_anv_buffer(cmd_buffer
->device
,
818 dst_buffer
, dstOffset
,
820 width
* bs
, isl_format
,
823 blorp_clear(&batch
, &surf
, isl_format
, ISL_SWIZZLE_IDENTITY
,
824 0, 0, 1, 0, 0, width
, 1,
828 blorp_batch_finish(&batch
);
831 void anv_CmdClearColorImage(
832 VkCommandBuffer commandBuffer
,
834 VkImageLayout imageLayout
,
835 const VkClearColorValue
* pColor
,
837 const VkImageSubresourceRange
* pRanges
)
839 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
840 ANV_FROM_HANDLE(anv_image
, image
, _image
);
842 static const bool color_write_disable
[4] = { false, false, false, false };
844 struct blorp_batch batch
;
845 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
848 for (unsigned r
= 0; r
< rangeCount
; r
++) {
849 if (pRanges
[r
].aspectMask
== 0)
852 assert(pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
854 struct blorp_surf surf
;
855 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
856 image
, pRanges
[r
].aspectMask
,
857 imageLayout
, ISL_AUX_USAGE_NONE
, &surf
);
859 struct anv_format_plane src_format
=
860 anv_get_format_plane(&cmd_buffer
->device
->info
, image
->vk_format
,
861 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
863 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
864 unsigned layer_count
= anv_get_layerCount(image
, &pRanges
[r
]);
866 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
867 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
868 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
869 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
871 if (image
->type
== VK_IMAGE_TYPE_3D
) {
873 layer_count
= anv_minify(image
->extent
.depth
, level
);
876 anv_cmd_buffer_mark_image_written(cmd_buffer
, image
,
877 pRanges
[r
].aspectMask
,
878 surf
.aux_usage
, level
,
879 base_layer
, layer_count
);
881 blorp_clear(&batch
, &surf
,
882 src_format
.isl_format
, src_format
.swizzle
,
883 level
, base_layer
, layer_count
,
884 0, 0, level_width
, level_height
,
885 vk_to_isl_color(*pColor
), color_write_disable
);
889 blorp_batch_finish(&batch
);
892 void anv_CmdClearDepthStencilImage(
893 VkCommandBuffer commandBuffer
,
895 VkImageLayout imageLayout
,
896 const VkClearDepthStencilValue
* pDepthStencil
,
898 const VkImageSubresourceRange
* pRanges
)
900 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
901 ANV_FROM_HANDLE(anv_image
, image
, image_h
);
903 struct blorp_batch batch
;
904 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
906 struct blorp_surf depth
, stencil
;
907 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
908 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
909 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
910 imageLayout
, ISL_AUX_USAGE_NONE
, &depth
);
912 memset(&depth
, 0, sizeof(depth
));
915 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
916 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
917 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
918 imageLayout
, ISL_AUX_USAGE_NONE
, &stencil
);
920 memset(&stencil
, 0, sizeof(stencil
));
923 for (unsigned r
= 0; r
< rangeCount
; r
++) {
924 if (pRanges
[r
].aspectMask
== 0)
927 bool clear_depth
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
928 bool clear_stencil
= pRanges
[r
].aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
930 unsigned base_layer
= pRanges
[r
].baseArrayLayer
;
931 unsigned layer_count
= anv_get_layerCount(image
, &pRanges
[r
]);
933 for (unsigned i
= 0; i
< anv_get_levelCount(image
, &pRanges
[r
]); i
++) {
934 const unsigned level
= pRanges
[r
].baseMipLevel
+ i
;
935 const unsigned level_width
= anv_minify(image
->extent
.width
, level
);
936 const unsigned level_height
= anv_minify(image
->extent
.height
, level
);
938 if (image
->type
== VK_IMAGE_TYPE_3D
)
939 layer_count
= anv_minify(image
->extent
.depth
, level
);
941 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
942 level
, base_layer
, layer_count
,
943 0, 0, level_width
, level_height
,
944 clear_depth
, pDepthStencil
->depth
,
945 clear_stencil
? 0xff : 0,
946 pDepthStencil
->stencil
);
950 blorp_batch_finish(&batch
);
954 anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
955 uint32_t num_entries
,
956 uint32_t *state_offset
,
957 struct anv_state
*bt_state
)
959 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
961 if (bt_state
->map
== NULL
) {
962 /* We ran out of space. Grab a new binding table block. */
963 VkResult result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
964 if (result
!= VK_SUCCESS
)
967 /* Re-emit state base addresses so we get the new surface state base
968 * address before we start emitting binding tables etc.
970 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
972 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
, num_entries
,
974 assert(bt_state
->map
!= NULL
);
981 binding_table_for_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
982 struct anv_state surface_state
,
985 uint32_t state_offset
;
986 struct anv_state bt_state
;
989 anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer
, 1, &state_offset
,
991 if (result
!= VK_SUCCESS
)
994 uint32_t *bt_map
= bt_state
.map
;
995 bt_map
[0] = surface_state
.offset
+ state_offset
;
997 *bt_offset
= bt_state
.offset
;
1002 clear_color_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1003 struct blorp_batch
*batch
,
1004 const VkClearAttachment
*attachment
,
1005 uint32_t rectCount
, const VkClearRect
*pRects
)
1007 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1008 const uint32_t color_att
= attachment
->colorAttachment
;
1009 const uint32_t att_idx
= subpass
->color_attachments
[color_att
].attachment
;
1011 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1014 struct anv_render_pass_attachment
*pass_att
=
1015 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
1016 struct anv_attachment_state
*att_state
=
1017 &cmd_buffer
->state
.attachments
[att_idx
];
1019 uint32_t binding_table
;
1021 binding_table_for_surface_state(cmd_buffer
, att_state
->color
.state
,
1023 if (result
!= VK_SUCCESS
)
1026 union isl_color_value clear_color
=
1027 vk_to_isl_color(attachment
->clearValue
.color
);
1029 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1030 if (subpass
->view_mask
) {
1032 for_each_bit(view_idx
, subpass
->view_mask
) {
1033 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1034 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1035 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1036 blorp_clear_attachments(batch
, binding_table
,
1037 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
1040 offset
.x
+ extent
.width
,
1041 offset
.y
+ extent
.height
,
1042 true, clear_color
, false, 0.0f
, 0, 0);
1048 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1049 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1050 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1051 assert(pRects
[r
].layerCount
!= VK_REMAINING_ARRAY_LAYERS
);
1052 blorp_clear_attachments(batch
, binding_table
,
1053 ISL_FORMAT_UNSUPPORTED
, pass_att
->samples
,
1054 pRects
[r
].baseArrayLayer
,
1055 pRects
[r
].layerCount
,
1057 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1058 true, clear_color
, false, 0.0f
, 0, 0);
1063 clear_depth_stencil_attachment(struct anv_cmd_buffer
*cmd_buffer
,
1064 struct blorp_batch
*batch
,
1065 const VkClearAttachment
*attachment
,
1066 uint32_t rectCount
, const VkClearRect
*pRects
)
1068 static const union isl_color_value color_value
= { .u32
= { 0, } };
1069 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1070 const uint32_t att_idx
= subpass
->depth_stencil_attachment
->attachment
;
1072 if (att_idx
== VK_ATTACHMENT_UNUSED
)
1075 struct anv_render_pass_attachment
*pass_att
=
1076 &cmd_buffer
->state
.pass
->attachments
[att_idx
];
1078 bool clear_depth
= attachment
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
;
1079 bool clear_stencil
= attachment
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
;
1081 enum isl_format depth_format
= ISL_FORMAT_UNSUPPORTED
;
1083 depth_format
= anv_get_isl_format(&cmd_buffer
->device
->info
,
1085 VK_IMAGE_ASPECT_DEPTH_BIT
,
1086 VK_IMAGE_TILING_OPTIMAL
);
1089 uint32_t binding_table
;
1091 binding_table_for_surface_state(cmd_buffer
,
1092 cmd_buffer
->state
.null_surface_state
,
1094 if (result
!= VK_SUCCESS
)
1097 /* If multiview is enabled we ignore baseArrayLayer and layerCount */
1098 if (subpass
->view_mask
) {
1100 for_each_bit(view_idx
, subpass
->view_mask
) {
1101 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1102 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1103 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1104 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1105 blorp_clear_attachments(batch
, binding_table
,
1106 depth_format
, pass_att
->samples
,
1109 offset
.x
+ extent
.width
,
1110 offset
.y
+ extent
.height
,
1112 clear_depth
, value
.depth
,
1113 clear_stencil
? 0xff : 0, value
.stencil
);
1119 for (uint32_t r
= 0; r
< rectCount
; ++r
) {
1120 const VkOffset2D offset
= pRects
[r
].rect
.offset
;
1121 const VkExtent2D extent
= pRects
[r
].rect
.extent
;
1122 VkClearDepthStencilValue value
= attachment
->clearValue
.depthStencil
;
1123 assert(pRects
[r
].layerCount
!= VK_REMAINING_ARRAY_LAYERS
);
1124 blorp_clear_attachments(batch
, binding_table
,
1125 depth_format
, pass_att
->samples
,
1126 pRects
[r
].baseArrayLayer
,
1127 pRects
[r
].layerCount
,
1129 offset
.x
+ extent
.width
, offset
.y
+ extent
.height
,
1131 clear_depth
, value
.depth
,
1132 clear_stencil
? 0xff : 0, value
.stencil
);
1136 void anv_CmdClearAttachments(
1137 VkCommandBuffer commandBuffer
,
1138 uint32_t attachmentCount
,
1139 const VkClearAttachment
* pAttachments
,
1141 const VkClearRect
* pRects
)
1143 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1145 /* Because this gets called within a render pass, we tell blorp not to
1146 * trash our depth and stencil buffers.
1148 struct blorp_batch batch
;
1149 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1150 BLORP_BATCH_NO_EMIT_DEPTH_STENCIL
);
1152 for (uint32_t a
= 0; a
< attachmentCount
; ++a
) {
1153 if (pAttachments
[a
].aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1154 assert(pAttachments
[a
].aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
1155 clear_color_attachment(cmd_buffer
, &batch
,
1159 clear_depth_stencil_attachment(cmd_buffer
, &batch
,
1165 blorp_batch_finish(&batch
);
1168 enum subpass_stage
{
1171 SUBPASS_STAGE_RESOLVE
,
1175 anv_image_msaa_resolve(struct anv_cmd_buffer
*cmd_buffer
,
1176 const struct anv_image
*src_image
,
1177 enum isl_aux_usage src_aux_usage
,
1178 uint32_t src_level
, uint32_t src_base_layer
,
1179 const struct anv_image
*dst_image
,
1180 enum isl_aux_usage dst_aux_usage
,
1181 uint32_t dst_level
, uint32_t dst_base_layer
,
1182 VkImageAspectFlagBits aspect
,
1183 uint32_t src_x
, uint32_t src_y
,
1184 uint32_t dst_x
, uint32_t dst_y
,
1185 uint32_t width
, uint32_t height
,
1186 uint32_t layer_count
,
1187 enum blorp_filter filter
)
1189 struct blorp_batch batch
;
1190 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1192 assert(src_image
->type
== VK_IMAGE_TYPE_2D
);
1193 assert(src_image
->samples
> 1);
1194 assert(dst_image
->type
== VK_IMAGE_TYPE_2D
);
1195 assert(dst_image
->samples
== 1);
1196 assert(src_image
->n_planes
== dst_image
->n_planes
);
1197 assert(!src_image
->format
->can_ycbcr
);
1198 assert(!dst_image
->format
->can_ycbcr
);
1200 struct blorp_surf src_surf
, dst_surf
;
1201 get_blorp_surf_for_anv_image(cmd_buffer
->device
, src_image
, aspect
,
1202 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1203 src_aux_usage
, &src_surf
);
1204 if (src_aux_usage
== ISL_AUX_USAGE_MCS
) {
1205 src_surf
.clear_color_addr
= anv_to_blorp_address(
1206 anv_image_get_clear_color_addr(cmd_buffer
->device
, src_image
,
1207 VK_IMAGE_ASPECT_COLOR_BIT
));
1209 get_blorp_surf_for_anv_image(cmd_buffer
->device
, dst_image
, aspect
,
1210 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1211 dst_aux_usage
, &dst_surf
);
1212 anv_cmd_buffer_mark_image_written(cmd_buffer
, dst_image
,
1213 aspect
, dst_aux_usage
,
1214 dst_level
, dst_base_layer
, layer_count
);
1216 if (filter
== BLORP_FILTER_NONE
) {
1217 /* If no explicit filter is provided, then it's implied by the type of
1220 if ((src_surf
.surf
->usage
& ISL_SURF_USAGE_DEPTH_BIT
) ||
1221 (src_surf
.surf
->usage
& ISL_SURF_USAGE_STENCIL_BIT
) ||
1222 isl_format_has_int_channel(src_surf
.surf
->format
)) {
1223 filter
= BLORP_FILTER_SAMPLE_0
;
1225 filter
= BLORP_FILTER_AVERAGE
;
1229 for (uint32_t l
= 0; l
< layer_count
; l
++) {
1231 &src_surf
, src_level
, src_base_layer
+ l
,
1232 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1233 &dst_surf
, dst_level
, dst_base_layer
+ l
,
1234 ISL_FORMAT_UNSUPPORTED
, ISL_SWIZZLE_IDENTITY
,
1235 src_x
, src_y
, src_x
+ width
, src_y
+ height
,
1236 dst_x
, dst_y
, dst_x
+ width
, dst_y
+ height
,
1237 filter
, false, false);
1240 blorp_batch_finish(&batch
);
1243 void anv_CmdResolveImage(
1244 VkCommandBuffer commandBuffer
,
1246 VkImageLayout srcImageLayout
,
1248 VkImageLayout dstImageLayout
,
1249 uint32_t regionCount
,
1250 const VkImageResolve
* pRegions
)
1252 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1253 ANV_FROM_HANDLE(anv_image
, src_image
, srcImage
);
1254 ANV_FROM_HANDLE(anv_image
, dst_image
, dstImage
);
1256 assert(!src_image
->format
->can_ycbcr
);
1258 for (uint32_t r
= 0; r
< regionCount
; r
++) {
1259 assert(pRegions
[r
].srcSubresource
.aspectMask
==
1260 pRegions
[r
].dstSubresource
.aspectMask
);
1261 assert(anv_get_layerCount(src_image
, &pRegions
[r
].srcSubresource
) ==
1262 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
));
1264 const uint32_t layer_count
=
1265 anv_get_layerCount(dst_image
, &pRegions
[r
].dstSubresource
);
1267 VkImageAspectFlags src_mask
= pRegions
[r
].srcSubresource
.aspectMask
;
1268 VkImageAspectFlags dst_mask
= pRegions
[r
].dstSubresource
.aspectMask
;
1270 assert(anv_image_aspects_compatible(src_mask
, dst_mask
));
1272 uint32_t aspect_bit
;
1273 anv_foreach_image_aspect_bit(aspect_bit
, src_image
,
1274 pRegions
[r
].srcSubresource
.aspectMask
) {
1275 enum isl_aux_usage src_aux_usage
=
1276 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_image
,
1277 (1 << aspect_bit
), srcImageLayout
);
1278 enum isl_aux_usage dst_aux_usage
=
1279 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_image
,
1280 (1 << aspect_bit
), dstImageLayout
);
1282 anv_image_msaa_resolve(cmd_buffer
,
1283 src_image
, src_aux_usage
,
1284 pRegions
[r
].srcSubresource
.mipLevel
,
1285 pRegions
[r
].srcSubresource
.baseArrayLayer
,
1286 dst_image
, dst_aux_usage
,
1287 pRegions
[r
].dstSubresource
.mipLevel
,
1288 pRegions
[r
].dstSubresource
.baseArrayLayer
,
1290 pRegions
[r
].srcOffset
.x
,
1291 pRegions
[r
].srcOffset
.y
,
1292 pRegions
[r
].dstOffset
.x
,
1293 pRegions
[r
].dstOffset
.y
,
1294 pRegions
[r
].extent
.width
,
1295 pRegions
[r
].extent
.height
,
1296 layer_count
, BLORP_FILTER_NONE
);
1301 static enum isl_aux_usage
1302 fast_clear_aux_usage(const struct anv_image
*image
,
1303 VkImageAspectFlagBits aspect
)
1305 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1306 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
1307 return ISL_AUX_USAGE_CCS_D
;
1309 return image
->planes
[plane
].aux_usage
;
1313 anv_image_copy_to_shadow(struct anv_cmd_buffer
*cmd_buffer
,
1314 const struct anv_image
*image
,
1315 uint32_t base_level
, uint32_t level_count
,
1316 uint32_t base_layer
, uint32_t layer_count
)
1318 struct blorp_batch batch
;
1319 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1321 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
&& image
->n_planes
== 1);
1323 struct blorp_surf surf
;
1324 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1325 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
1326 VK_IMAGE_LAYOUT_GENERAL
,
1327 ISL_AUX_USAGE_NONE
, &surf
);
1328 assert(surf
.aux_usage
== ISL_AUX_USAGE_NONE
);
1330 struct blorp_surf shadow_surf
= {
1331 .surf
= &image
->planes
[0].shadow_surface
.isl
,
1333 .buffer
= image
->planes
[0].address
.bo
,
1334 .offset
= image
->planes
[0].address
.offset
+
1335 image
->planes
[0].shadow_surface
.offset
,
1336 .mocs
= anv_mocs_for_bo(cmd_buffer
->device
,
1337 image
->planes
[0].address
.bo
),
1341 for (uint32_t l
= 0; l
< level_count
; l
++) {
1342 const uint32_t level
= base_level
+ l
;
1344 const VkExtent3D extent
= {
1345 .width
= anv_minify(image
->extent
.width
, level
),
1346 .height
= anv_minify(image
->extent
.height
, level
),
1347 .depth
= anv_minify(image
->extent
.depth
, level
),
1350 if (image
->type
== VK_IMAGE_TYPE_3D
)
1351 layer_count
= extent
.depth
;
1353 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1354 const uint32_t layer
= base_layer
+ a
;
1356 blorp_copy(&batch
, &surf
, level
, layer
,
1357 &shadow_surf
, level
, layer
,
1358 0, 0, 0, 0, extent
.width
, extent
.height
);
1362 blorp_batch_finish(&batch
);
1366 anv_image_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
1367 const struct anv_image
*image
,
1368 VkImageAspectFlagBits aspect
,
1369 enum isl_aux_usage aux_usage
,
1370 enum isl_format format
, struct isl_swizzle swizzle
,
1371 uint32_t level
, uint32_t base_layer
, uint32_t layer_count
,
1372 VkRect2D area
, union isl_color_value clear_color
)
1374 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1376 /* We don't support planar images with multisampling yet */
1377 assert(image
->n_planes
== 1);
1379 struct blorp_batch batch
;
1380 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1382 struct blorp_surf surf
;
1383 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1384 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1386 anv_cmd_buffer_mark_image_written(cmd_buffer
, image
, aspect
, aux_usage
,
1387 level
, base_layer
, layer_count
);
1389 blorp_clear(&batch
, &surf
, format
, anv_swizzle_for_render(swizzle
),
1390 level
, base_layer
, layer_count
,
1391 area
.offset
.x
, area
.offset
.y
,
1392 area
.offset
.x
+ area
.extent
.width
,
1393 area
.offset
.y
+ area
.extent
.height
,
1396 blorp_batch_finish(&batch
);
1400 anv_image_clear_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
,
1401 const struct anv_image
*image
,
1402 VkImageAspectFlags aspects
,
1403 enum isl_aux_usage depth_aux_usage
,
1405 uint32_t base_layer
, uint32_t layer_count
,
1407 float depth_value
, uint8_t stencil_value
)
1409 assert(image
->aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1410 VK_IMAGE_ASPECT_STENCIL_BIT
));
1412 struct blorp_batch batch
;
1413 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1415 struct blorp_surf depth
= {};
1416 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1417 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1418 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1419 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1420 depth_aux_usage
, &depth
);
1421 depth
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1424 struct blorp_surf stencil
= {};
1425 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1426 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1427 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
1428 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1429 ISL_AUX_USAGE_NONE
, &stencil
);
1432 blorp_clear_depth_stencil(&batch
, &depth
, &stencil
,
1433 level
, base_layer
, layer_count
,
1434 area
.offset
.x
, area
.offset
.y
,
1435 area
.offset
.x
+ area
.extent
.width
,
1436 area
.offset
.y
+ area
.extent
.height
,
1437 aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
,
1439 (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) ? 0xff : 0,
1442 blorp_batch_finish(&batch
);
1446 anv_image_hiz_op(struct anv_cmd_buffer
*cmd_buffer
,
1447 const struct anv_image
*image
,
1448 VkImageAspectFlagBits aspect
, uint32_t level
,
1449 uint32_t base_layer
, uint32_t layer_count
,
1450 enum isl_aux_op hiz_op
)
1452 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
1453 assert(base_layer
+ layer_count
<= anv_image_aux_layers(image
, aspect
, level
));
1454 assert(anv_image_aspect_to_plane(image
->aspects
,
1455 VK_IMAGE_ASPECT_DEPTH_BIT
) == 0);
1457 struct blorp_batch batch
;
1458 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1460 struct blorp_surf surf
;
1461 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1462 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1463 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1464 ISL_AUX_USAGE_HIZ
, &surf
);
1465 surf
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1467 blorp_hiz_op(&batch
, &surf
, level
, base_layer
, layer_count
, hiz_op
);
1469 blorp_batch_finish(&batch
);
1473 anv_image_hiz_clear(struct anv_cmd_buffer
*cmd_buffer
,
1474 const struct anv_image
*image
,
1475 VkImageAspectFlags aspects
,
1477 uint32_t base_layer
, uint32_t layer_count
,
1478 VkRect2D area
, uint8_t stencil_value
)
1480 assert(image
->aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1481 VK_IMAGE_ASPECT_STENCIL_BIT
));
1483 struct blorp_batch batch
;
1484 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
, 0);
1486 struct blorp_surf depth
= {};
1487 if (aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1488 assert(base_layer
+ layer_count
<=
1489 anv_image_aux_layers(image
, VK_IMAGE_ASPECT_DEPTH_BIT
, level
));
1490 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1491 image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
1492 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1493 ISL_AUX_USAGE_HIZ
, &depth
);
1494 depth
.clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1497 struct blorp_surf stencil
= {};
1498 if (aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1499 get_blorp_surf_for_anv_image(cmd_buffer
->device
,
1500 image
, VK_IMAGE_ASPECT_STENCIL_BIT
,
1501 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1502 ISL_AUX_USAGE_NONE
, &stencil
);
1505 /* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
1507 * "The following is required when performing a depth buffer clear with
1508 * using the WM_STATE or 3DSTATE_WM:
1510 * * If other rendering operations have preceded this clear, a
1511 * PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
1512 * enabled must be issued before the rectangle primitive used for
1513 * the depth buffer clear operation.
1516 * Even though the PRM only says that this is required if using 3DSTATE_WM
1517 * and a 3DPRIMITIVE, the GPU appears to also need this to avoid occasional
1518 * hangs when doing a clear with WM_HZ_OP.
1520 cmd_buffer
->state
.pending_pipe_bits
|=
1521 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
| ANV_PIPE_DEPTH_STALL_BIT
;
1523 blorp_hiz_clear_depth_stencil(&batch
, &depth
, &stencil
,
1524 level
, base_layer
, layer_count
,
1525 area
.offset
.x
, area
.offset
.y
,
1526 area
.offset
.x
+ area
.extent
.width
,
1527 area
.offset
.y
+ area
.extent
.height
,
1528 aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
,
1530 aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
,
1533 blorp_batch_finish(&batch
);
1535 /* From the SKL PRM, Depth Buffer Clear:
1537 * "Depth Buffer Clear Workaround
1539 * Depth buffer clear pass using any of the methods (WM_STATE,
1540 * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
1541 * command with DEPTH_STALL bit and Depth FLUSH bits “set” before
1542 * starting to render. DepthStall and DepthFlush are not needed between
1543 * consecutive depth clear passes nor is it required if the depth-clear
1544 * pass was done with “full_surf_clear” bit set in the
1545 * 3DSTATE_WM_HZ_OP."
1547 * Even though the PRM provides a bunch of conditions under which this is
1548 * supposedly unnecessary, we choose to perform the flush unconditionally
1551 cmd_buffer
->state
.pending_pipe_bits
|=
1552 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
| ANV_PIPE_DEPTH_STALL_BIT
;
1556 anv_image_mcs_op(struct anv_cmd_buffer
*cmd_buffer
,
1557 const struct anv_image
*image
,
1558 enum isl_format format
,
1559 VkImageAspectFlagBits aspect
,
1560 uint32_t base_layer
, uint32_t layer_count
,
1561 enum isl_aux_op mcs_op
, union isl_color_value
*clear_value
,
1564 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1565 assert(image
->samples
> 1);
1566 assert(base_layer
+ layer_count
<= anv_image_aux_layers(image
, aspect
, 0));
1568 /* Multisampling with multi-planar formats is not supported */
1569 assert(image
->n_planes
== 1);
1571 struct blorp_batch batch
;
1572 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1573 predicate
? BLORP_BATCH_PREDICATE_ENABLE
: 0);
1575 struct blorp_surf surf
;
1576 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1577 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1578 ISL_AUX_USAGE_MCS
, &surf
);
1580 /* Blorp will store the clear color for us if we provide the clear color
1581 * address and we are doing a fast clear. So we save the clear value into
1582 * the blorp surface. However, in some situations we want to do a fast clear
1583 * without changing the clear value stored in the state buffer. For those
1584 * cases, we set the clear color address pointer to NULL, so blorp will not
1585 * try to store a garbage color.
1587 if (mcs_op
== ISL_AUX_OP_FAST_CLEAR
) {
1589 surf
.clear_color
= *clear_value
;
1591 surf
.clear_color_addr
.buffer
= NULL
;
1594 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1596 * "After Render target fast clear, pipe-control with color cache
1597 * write-flush must be issued before sending any DRAW commands on
1598 * that render target."
1600 * This comment is a bit cryptic and doesn't really tell you what's going
1601 * or what's really needed. It appears that fast clear ops are not
1602 * properly synchronized with other drawing. This means that we cannot
1603 * have a fast clear operation in the pipe at the same time as other
1604 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1605 * that the contents of the previous draw hit the render target before we
1606 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1607 * that it is completed before any additional drawing occurs.
1609 cmd_buffer
->state
.pending_pipe_bits
|=
1610 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1613 case ISL_AUX_OP_FAST_CLEAR
:
1614 blorp_fast_clear(&batch
, &surf
, format
,
1615 0, base_layer
, layer_count
,
1616 0, 0, image
->extent
.width
, image
->extent
.height
);
1618 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1619 blorp_mcs_partial_resolve(&batch
, &surf
, format
,
1620 base_layer
, layer_count
);
1622 case ISL_AUX_OP_FULL_RESOLVE
:
1623 case ISL_AUX_OP_AMBIGUATE
:
1625 unreachable("Unsupported MCS operation");
1628 cmd_buffer
->state
.pending_pipe_bits
|=
1629 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1631 blorp_batch_finish(&batch
);
1635 anv_image_ccs_op(struct anv_cmd_buffer
*cmd_buffer
,
1636 const struct anv_image
*image
,
1637 enum isl_format format
,
1638 VkImageAspectFlagBits aspect
, uint32_t level
,
1639 uint32_t base_layer
, uint32_t layer_count
,
1640 enum isl_aux_op ccs_op
, union isl_color_value
*clear_value
,
1643 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1644 assert(image
->samples
== 1);
1645 assert(level
< anv_image_aux_levels(image
, aspect
));
1646 /* Multi-LOD YcBcR is not allowed */
1647 assert(image
->n_planes
== 1 || level
== 0);
1648 assert(base_layer
+ layer_count
<=
1649 anv_image_aux_layers(image
, aspect
, level
));
1651 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1652 uint32_t width_div
= image
->format
->planes
[plane
].denominator_scales
[0];
1653 uint32_t height_div
= image
->format
->planes
[plane
].denominator_scales
[1];
1654 uint32_t level_width
= anv_minify(image
->extent
.width
, level
) / width_div
;
1655 uint32_t level_height
= anv_minify(image
->extent
.height
, level
) / height_div
;
1657 struct blorp_batch batch
;
1658 blorp_batch_init(&cmd_buffer
->device
->blorp
, &batch
, cmd_buffer
,
1659 predicate
? BLORP_BATCH_PREDICATE_ENABLE
: 0);
1661 struct blorp_surf surf
;
1662 get_blorp_surf_for_anv_image(cmd_buffer
->device
, image
, aspect
,
1663 ANV_IMAGE_LAYOUT_EXPLICIT_AUX
,
1664 fast_clear_aux_usage(image
, aspect
),
1667 /* Blorp will store the clear color for us if we provide the clear color
1668 * address and we are doing a fast clear. So we save the clear value into
1669 * the blorp surface. However, in some situations we want to do a fast clear
1670 * without changing the clear value stored in the state buffer. For those
1671 * cases, we set the clear color address pointer to NULL, so blorp will not
1672 * try to store a garbage color.
1674 if (ccs_op
== ISL_AUX_OP_FAST_CLEAR
) {
1676 surf
.clear_color
= *clear_value
;
1678 surf
.clear_color_addr
.buffer
= NULL
;
1681 /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
1683 * "After Render target fast clear, pipe-control with color cache
1684 * write-flush must be issued before sending any DRAW commands on
1685 * that render target."
1687 * This comment is a bit cryptic and doesn't really tell you what's going
1688 * or what's really needed. It appears that fast clear ops are not
1689 * properly synchronized with other drawing. This means that we cannot
1690 * have a fast clear operation in the pipe at the same time as other
1691 * regular drawing operations. We need to use a PIPE_CONTROL to ensure
1692 * that the contents of the previous draw hit the render target before we
1693 * resolve and then use a second PIPE_CONTROL after the resolve to ensure
1694 * that it is completed before any additional drawing occurs.
1696 cmd_buffer
->state
.pending_pipe_bits
|=
1697 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1700 case ISL_AUX_OP_FAST_CLEAR
:
1701 blorp_fast_clear(&batch
, &surf
, format
,
1702 level
, base_layer
, layer_count
,
1703 0, 0, level_width
, level_height
);
1705 case ISL_AUX_OP_FULL_RESOLVE
:
1706 case ISL_AUX_OP_PARTIAL_RESOLVE
:
1707 blorp_ccs_resolve(&batch
, &surf
, level
, base_layer
, layer_count
,
1710 case ISL_AUX_OP_AMBIGUATE
:
1711 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1712 const uint32_t layer
= base_layer
+ a
;
1713 blorp_ccs_ambiguate(&batch
, &surf
, level
, layer
);
1717 unreachable("Unsupported CCS operation");
1720 cmd_buffer
->state
.pending_pipe_bits
|=
1721 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1723 blorp_batch_finish(&batch
);