2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include "anv_private.h"
32 #include "vk_format_info.h"
34 /** \file anv_cmd_buffer.c
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state
= {
57 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
62 .stencil_compare_mask
= {
66 .stencil_write_mask
= {
70 .stencil_reference
= {
77 anv_dynamic_state_copy(struct anv_dynamic_state
*dest
,
78 const struct anv_dynamic_state
*src
,
81 if (copy_mask
& (1 << VK_DYNAMIC_STATE_VIEWPORT
)) {
82 dest
->viewport
.count
= src
->viewport
.count
;
83 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
87 if (copy_mask
& (1 << VK_DYNAMIC_STATE_SCISSOR
)) {
88 dest
->scissor
.count
= src
->scissor
.count
;
89 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
93 if (copy_mask
& (1 << VK_DYNAMIC_STATE_LINE_WIDTH
))
94 dest
->line_width
= src
->line_width
;
96 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BIAS
))
97 dest
->depth_bias
= src
->depth_bias
;
99 if (copy_mask
& (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS
))
100 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
102 if (copy_mask
& (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS
))
103 dest
->depth_bounds
= src
->depth_bounds
;
105 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
))
106 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
108 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
))
109 dest
->stencil_write_mask
= src
->stencil_write_mask
;
111 if (copy_mask
& (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE
))
112 dest
->stencil_reference
= src
->stencil_reference
;
116 anv_cmd_state_reset(struct anv_cmd_buffer
*cmd_buffer
)
118 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
120 memset(&state
->descriptors
, 0, sizeof(state
->descriptors
));
121 memset(&state
->push_constants
, 0, sizeof(state
->push_constants
));
122 memset(state
->binding_tables
, 0, sizeof(state
->binding_tables
));
123 memset(state
->samplers
, 0, sizeof(state
->samplers
));
125 /* 0 isn't a valid config. This ensures that we always configure L3$. */
126 cmd_buffer
->state
.current_l3_config
= 0;
130 state
->pending_pipe_bits
= 0;
131 state
->descriptors_dirty
= 0;
132 state
->push_constants_dirty
= 0;
133 state
->pipeline
= NULL
;
134 state
->push_constant_stages
= 0;
135 state
->restart_index
= UINT32_MAX
;
136 state
->dynamic
= default_dynamic_state
;
137 state
->need_query_wa
= true;
139 if (state
->attachments
!= NULL
) {
140 anv_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
141 state
->attachments
= NULL
;
144 state
->gen7
.index_buffer
= NULL
;
148 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
151 anv_cmd_state_setup_attachments(struct anv_cmd_buffer
*cmd_buffer
,
152 const VkRenderPassBeginInfo
*info
)
154 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
155 ANV_FROM_HANDLE(anv_render_pass
, pass
, info
->renderPass
);
157 anv_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
159 if (pass
->attachment_count
== 0) {
160 state
->attachments
= NULL
;
164 state
->attachments
= anv_alloc(&cmd_buffer
->pool
->alloc
,
165 pass
->attachment_count
*
166 sizeof(state
->attachments
[0]),
167 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
168 if (state
->attachments
== NULL
) {
169 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
173 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
174 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
175 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
176 VkImageAspectFlags clear_aspects
= 0;
178 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
179 /* color attachment */
180 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
181 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
184 /* depthstencil attachment */
185 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
186 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
187 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
189 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
190 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
191 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
195 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
197 assert(info
->clearValueCount
> i
);
198 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
204 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer
*cmd_buffer
,
205 gl_shader_stage stage
, uint32_t size
)
207 struct anv_push_constants
**ptr
= &cmd_buffer
->state
.push_constants
[stage
];
210 *ptr
= anv_alloc(&cmd_buffer
->pool
->alloc
, size
, 8,
211 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
213 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
214 } else if ((*ptr
)->size
< size
) {
215 *ptr
= anv_realloc(&cmd_buffer
->pool
->alloc
, *ptr
, size
, 8,
216 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
218 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
225 #define anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, field) \
226 anv_cmd_buffer_ensure_push_constants_size(cmd_buffer, stage, \
227 (offsetof(struct anv_push_constants, field) + \
228 sizeof(cmd_buffer->state.push_constants[0]->field)))
230 static VkResult
anv_create_cmd_buffer(
231 struct anv_device
* device
,
232 struct anv_cmd_pool
* pool
,
233 VkCommandBufferLevel level
,
234 VkCommandBuffer
* pCommandBuffer
)
236 struct anv_cmd_buffer
*cmd_buffer
;
239 cmd_buffer
= anv_alloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
240 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
241 if (cmd_buffer
== NULL
)
242 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
244 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
245 cmd_buffer
->device
= device
;
246 cmd_buffer
->pool
= pool
;
247 cmd_buffer
->level
= level
;
248 cmd_buffer
->state
.attachments
= NULL
;
250 result
= anv_cmd_buffer_init_batch_bo_chain(cmd_buffer
);
251 if (result
!= VK_SUCCESS
)
254 anv_state_stream_init(&cmd_buffer
->surface_state_stream
,
255 &device
->surface_state_block_pool
);
256 anv_state_stream_init(&cmd_buffer
->dynamic_state_stream
,
257 &device
->dynamic_state_block_pool
);
260 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
262 /* Init the pool_link so we can safefly call list_del when we destroy
265 list_inithead(&cmd_buffer
->pool_link
);
268 *pCommandBuffer
= anv_cmd_buffer_to_handle(cmd_buffer
);
273 anv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
278 VkResult
anv_AllocateCommandBuffers(
280 const VkCommandBufferAllocateInfo
* pAllocateInfo
,
281 VkCommandBuffer
* pCommandBuffers
)
283 ANV_FROM_HANDLE(anv_device
, device
, _device
);
284 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
286 VkResult result
= VK_SUCCESS
;
289 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
290 result
= anv_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
291 &pCommandBuffers
[i
]);
292 if (result
!= VK_SUCCESS
)
296 if (result
!= VK_SUCCESS
)
297 anv_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
,
304 anv_cmd_buffer_destroy(struct anv_cmd_buffer
*cmd_buffer
)
306 list_del(&cmd_buffer
->pool_link
);
308 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer
);
310 anv_state_stream_finish(&cmd_buffer
->surface_state_stream
);
311 anv_state_stream_finish(&cmd_buffer
->dynamic_state_stream
);
313 anv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
314 anv_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
317 void anv_FreeCommandBuffers(
319 VkCommandPool commandPool
,
320 uint32_t commandBufferCount
,
321 const VkCommandBuffer
* pCommandBuffers
)
323 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
324 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
326 anv_cmd_buffer_destroy(cmd_buffer
);
330 VkResult
anv_ResetCommandBuffer(
331 VkCommandBuffer commandBuffer
,
332 VkCommandBufferResetFlags flags
)
334 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
336 cmd_buffer
->usage_flags
= 0;
337 cmd_buffer
->state
.current_pipeline
= UINT32_MAX
;
338 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer
);
339 anv_cmd_state_reset(cmd_buffer
);
341 anv_state_stream_finish(&cmd_buffer
->surface_state_stream
);
342 anv_state_stream_init(&cmd_buffer
->surface_state_stream
,
343 &cmd_buffer
->device
->surface_state_block_pool
);
345 anv_state_stream_finish(&cmd_buffer
->dynamic_state_stream
);
346 anv_state_stream_init(&cmd_buffer
->dynamic_state_stream
,
347 &cmd_buffer
->device
->dynamic_state_block_pool
);
353 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer
*cmd_buffer
)
355 switch (cmd_buffer
->device
->info
.gen
) {
357 if (cmd_buffer
->device
->info
.is_haswell
)
358 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer
);
360 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer
);
362 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer
);
364 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer
);
366 unreachable("unsupported gen\n");
370 VkResult
anv_BeginCommandBuffer(
371 VkCommandBuffer commandBuffer
,
372 const VkCommandBufferBeginInfo
* pBeginInfo
)
374 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
376 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
377 * command buffer's state. Otherwise, we must *reset* its state. In both
380 * From the Vulkan 1.0 spec:
382 * If a command buffer is in the executable state and the command buffer
383 * was allocated from a command pool with the
384 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
385 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
386 * as if vkResetCommandBuffer had been called with
387 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
388 * the command buffer in the recording state.
390 anv_ResetCommandBuffer(commandBuffer
, /*flags*/ 0);
392 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
394 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
395 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
397 anv_cmd_buffer_emit_state_base_address(cmd_buffer
);
399 if (cmd_buffer
->usage_flags
&
400 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
401 cmd_buffer
->state
.framebuffer
=
402 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
403 cmd_buffer
->state
.pass
=
404 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
406 struct anv_subpass
*subpass
=
407 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
409 anv_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
415 VkResult
anv_EndCommandBuffer(
416 VkCommandBuffer commandBuffer
)
418 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
419 struct anv_device
*device
= cmd_buffer
->device
;
421 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
423 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
424 /* The algorithm used to compute the validate list is not threadsafe as
425 * it uses the bo->index field. We have to lock the device around it.
426 * Fortunately, the chances for contention here are probably very low.
428 pthread_mutex_lock(&device
->mutex
);
429 anv_cmd_buffer_prepare_execbuf(cmd_buffer
);
430 pthread_mutex_unlock(&device
->mutex
);
436 void anv_CmdBindPipeline(
437 VkCommandBuffer commandBuffer
,
438 VkPipelineBindPoint pipelineBindPoint
,
439 VkPipeline _pipeline
)
441 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
442 ANV_FROM_HANDLE(anv_pipeline
, pipeline
, _pipeline
);
444 switch (pipelineBindPoint
) {
445 case VK_PIPELINE_BIND_POINT_COMPUTE
:
446 cmd_buffer
->state
.compute_pipeline
= pipeline
;
447 cmd_buffer
->state
.compute_dirty
|= ANV_CMD_DIRTY_PIPELINE
;
448 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
449 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
452 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
453 cmd_buffer
->state
.pipeline
= pipeline
;
454 cmd_buffer
->state
.vb_dirty
|= pipeline
->vb_used
;
455 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
456 cmd_buffer
->state
.push_constants_dirty
|= pipeline
->active_stages
;
457 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
459 /* Apply the dynamic state from the pipeline */
460 cmd_buffer
->state
.dirty
|= pipeline
->dynamic_state_mask
;
461 anv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
,
462 &pipeline
->dynamic_state
,
463 pipeline
->dynamic_state_mask
);
467 assert(!"invalid bind point");
472 void anv_CmdSetViewport(
473 VkCommandBuffer commandBuffer
,
474 uint32_t firstViewport
,
475 uint32_t viewportCount
,
476 const VkViewport
* pViewports
)
478 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
480 const uint32_t total_count
= firstViewport
+ viewportCount
;
481 if (cmd_buffer
->state
.dynamic
.viewport
.count
< total_count
)
482 cmd_buffer
->state
.dynamic
.viewport
.count
= total_count
;
484 memcpy(cmd_buffer
->state
.dynamic
.viewport
.viewports
+ firstViewport
,
485 pViewports
, viewportCount
* sizeof(*pViewports
));
487 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
;
490 void anv_CmdSetScissor(
491 VkCommandBuffer commandBuffer
,
492 uint32_t firstScissor
,
493 uint32_t scissorCount
,
494 const VkRect2D
* pScissors
)
496 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
498 const uint32_t total_count
= firstScissor
+ scissorCount
;
499 if (cmd_buffer
->state
.dynamic
.scissor
.count
< total_count
)
500 cmd_buffer
->state
.dynamic
.scissor
.count
= total_count
;
502 memcpy(cmd_buffer
->state
.dynamic
.scissor
.scissors
+ firstScissor
,
503 pScissors
, scissorCount
* sizeof(*pScissors
));
505 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_SCISSOR
;
508 void anv_CmdSetLineWidth(
509 VkCommandBuffer commandBuffer
,
512 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
514 cmd_buffer
->state
.dynamic
.line_width
= lineWidth
;
515 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
518 void anv_CmdSetDepthBias(
519 VkCommandBuffer commandBuffer
,
520 float depthBiasConstantFactor
,
521 float depthBiasClamp
,
522 float depthBiasSlopeFactor
)
524 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
526 cmd_buffer
->state
.dynamic
.depth_bias
.bias
= depthBiasConstantFactor
;
527 cmd_buffer
->state
.dynamic
.depth_bias
.clamp
= depthBiasClamp
;
528 cmd_buffer
->state
.dynamic
.depth_bias
.slope
= depthBiasSlopeFactor
;
530 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS
;
533 void anv_CmdSetBlendConstants(
534 VkCommandBuffer commandBuffer
,
535 const float blendConstants
[4])
537 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
539 memcpy(cmd_buffer
->state
.dynamic
.blend_constants
,
540 blendConstants
, sizeof(float) * 4);
542 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS
;
545 void anv_CmdSetDepthBounds(
546 VkCommandBuffer commandBuffer
,
547 float minDepthBounds
,
548 float maxDepthBounds
)
550 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
552 cmd_buffer
->state
.dynamic
.depth_bounds
.min
= minDepthBounds
;
553 cmd_buffer
->state
.dynamic
.depth_bounds
.max
= maxDepthBounds
;
555 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS
;
558 void anv_CmdSetStencilCompareMask(
559 VkCommandBuffer commandBuffer
,
560 VkStencilFaceFlags faceMask
,
561 uint32_t compareMask
)
563 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
565 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
566 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
567 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
568 cmd_buffer
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
570 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
573 void anv_CmdSetStencilWriteMask(
574 VkCommandBuffer commandBuffer
,
575 VkStencilFaceFlags faceMask
,
578 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
580 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
581 cmd_buffer
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
582 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
583 cmd_buffer
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
585 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
588 void anv_CmdSetStencilReference(
589 VkCommandBuffer commandBuffer
,
590 VkStencilFaceFlags faceMask
,
593 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
595 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
596 cmd_buffer
->state
.dynamic
.stencil_reference
.front
= reference
;
597 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
598 cmd_buffer
->state
.dynamic
.stencil_reference
.back
= reference
;
600 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
603 void anv_CmdBindDescriptorSets(
604 VkCommandBuffer commandBuffer
,
605 VkPipelineBindPoint pipelineBindPoint
,
606 VkPipelineLayout _layout
,
608 uint32_t descriptorSetCount
,
609 const VkDescriptorSet
* pDescriptorSets
,
610 uint32_t dynamicOffsetCount
,
611 const uint32_t* pDynamicOffsets
)
613 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
614 ANV_FROM_HANDLE(anv_pipeline_layout
, layout
, _layout
);
615 struct anv_descriptor_set_layout
*set_layout
;
617 assert(firstSet
+ descriptorSetCount
< MAX_SETS
);
619 uint32_t dynamic_slot
= 0;
620 for (uint32_t i
= 0; i
< descriptorSetCount
; i
++) {
621 ANV_FROM_HANDLE(anv_descriptor_set
, set
, pDescriptorSets
[i
]);
622 set_layout
= layout
->set
[firstSet
+ i
].layout
;
624 if (cmd_buffer
->state
.descriptors
[firstSet
+ i
] != set
) {
625 cmd_buffer
->state
.descriptors
[firstSet
+ i
] = set
;
626 cmd_buffer
->state
.descriptors_dirty
|= set_layout
->shader_stages
;
629 if (set_layout
->dynamic_offset_count
> 0) {
630 anv_foreach_stage(s
, set_layout
->shader_stages
) {
631 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, s
, dynamic
);
633 struct anv_push_constants
*push
=
634 cmd_buffer
->state
.push_constants
[s
];
636 unsigned d
= layout
->set
[firstSet
+ i
].dynamic_offset_start
;
637 const uint32_t *offsets
= pDynamicOffsets
+ dynamic_slot
;
638 struct anv_descriptor
*desc
= set
->descriptors
;
640 for (unsigned b
= 0; b
< set_layout
->binding_count
; b
++) {
641 if (set_layout
->binding
[b
].dynamic_offset_index
< 0)
644 unsigned array_size
= set_layout
->binding
[b
].array_size
;
645 for (unsigned j
= 0; j
< array_size
; j
++) {
647 if (desc
->buffer_view
)
648 range
= desc
->buffer_view
->range
;
649 push
->dynamic
[d
].offset
= *(offsets
++);
650 push
->dynamic
[d
].range
= range
;
656 cmd_buffer
->state
.push_constants_dirty
|= set_layout
->shader_stages
;
661 void anv_CmdBindVertexBuffers(
662 VkCommandBuffer commandBuffer
,
663 uint32_t firstBinding
,
664 uint32_t bindingCount
,
665 const VkBuffer
* pBuffers
,
666 const VkDeviceSize
* pOffsets
)
668 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
669 struct anv_vertex_binding
*vb
= cmd_buffer
->state
.vertex_bindings
;
671 /* We have to defer setting up vertex buffer since we need the buffer
672 * stride from the pipeline. */
674 assert(firstBinding
+ bindingCount
< MAX_VBS
);
675 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
676 vb
[firstBinding
+ i
].buffer
= anv_buffer_from_handle(pBuffers
[i
]);
677 vb
[firstBinding
+ i
].offset
= pOffsets
[i
];
678 cmd_buffer
->state
.vb_dirty
|= 1 << (firstBinding
+ i
);
683 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
684 struct anv_state state
, struct anv_bo
*bo
, uint32_t offset
)
686 /* The address goes in SURFACE_STATE dword 1 for gens < 8 and dwords 8 and
687 * 9 for gen8+. We only write the first dword for gen8+ here and rely on
688 * the initial state to set the high bits to 0. */
690 const uint32_t dword
= cmd_buffer
->device
->info
.gen
< 8 ? 1 : 8;
692 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
693 state
.offset
+ dword
* 4, bo
, offset
);
697 anv_isl_format_for_descriptor_type(VkDescriptorType type
)
700 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
701 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
702 return ISL_FORMAT_R32G32B32A32_FLOAT
;
704 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
705 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
706 return ISL_FORMAT_RAW
;
709 unreachable("Invalid descriptor type");
713 static struct anv_state
714 anv_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer
*cmd_buffer
,
715 struct anv_framebuffer
*fb
)
717 switch (cmd_buffer
->device
->info
.gen
) {
719 if (cmd_buffer
->device
->info
.is_haswell
) {
720 return gen75_cmd_buffer_alloc_null_surface_state(cmd_buffer
, fb
);
722 return gen7_cmd_buffer_alloc_null_surface_state(cmd_buffer
, fb
);
725 return gen8_cmd_buffer_alloc_null_surface_state(cmd_buffer
, fb
);
727 return gen9_cmd_buffer_alloc_null_surface_state(cmd_buffer
, fb
);
729 unreachable("Invalid hardware generation");
734 anv_cmd_buffer_emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
735 gl_shader_stage stage
,
736 struct anv_state
*bt_state
)
738 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
739 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
740 struct anv_pipeline_bind_map
*map
;
741 uint32_t bias
, state_offset
;
744 case MESA_SHADER_COMPUTE
:
745 map
= &cmd_buffer
->state
.compute_pipeline
->bindings
[stage
];
749 map
= &cmd_buffer
->state
.pipeline
->bindings
[stage
];
754 if (bias
+ map
->surface_count
== 0) {
755 *bt_state
= (struct anv_state
) { 0, };
759 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
760 bias
+ map
->surface_count
,
762 uint32_t *bt_map
= bt_state
->map
;
764 if (bt_state
->map
== NULL
)
765 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
767 if (stage
== MESA_SHADER_COMPUTE
&&
768 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
769 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
770 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
772 struct anv_state surface_state
;
774 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
776 const enum isl_format format
=
777 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
778 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
779 format
, bo_offset
, 12, 1);
781 bt_map
[0] = surface_state
.offset
+ state_offset
;
782 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
785 if (map
->surface_count
== 0)
788 if (map
->image_count
> 0) {
790 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
791 if (result
!= VK_SUCCESS
)
794 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
798 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
799 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
801 struct anv_state surface_state
;
805 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
806 /* Color attachment binding */
807 assert(stage
== MESA_SHADER_FRAGMENT
);
808 if (binding
->offset
< subpass
->color_count
) {
809 const struct anv_image_view
*iview
=
810 fb
->attachments
[subpass
->color_attachments
[binding
->offset
]];
812 assert(iview
->color_rt_surface_state
.alloc_size
);
813 surface_state
= iview
->color_rt_surface_state
;
814 add_surface_state_reloc(cmd_buffer
, iview
->color_rt_surface_state
,
815 iview
->bo
, iview
->offset
);
817 /* Null render target */
818 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
820 anv_cmd_buffer_alloc_null_surface_state(cmd_buffer
, fb
);
823 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
827 struct anv_descriptor_set
*set
=
828 cmd_buffer
->state
.descriptors
[binding
->set
];
829 struct anv_descriptor
*desc
= &set
->descriptors
[binding
->offset
];
831 switch (desc
->type
) {
832 case VK_DESCRIPTOR_TYPE_SAMPLER
:
833 /* Nothing for us to do here */
836 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
837 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
838 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
839 surface_state
= desc
->image_view
->sampler_surface_state
;
840 assert(surface_state
.alloc_size
);
841 bo
= desc
->image_view
->bo
;
842 bo_offset
= desc
->image_view
->offset
;
845 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
846 surface_state
= desc
->image_view
->storage_surface_state
;
847 assert(surface_state
.alloc_size
);
848 bo
= desc
->image_view
->bo
;
849 bo_offset
= desc
->image_view
->offset
;
851 struct brw_image_param
*image_param
=
852 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
854 *image_param
= desc
->image_view
->storage_image_param
;
855 image_param
->surface_idx
= bias
+ s
;
859 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
860 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
861 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
862 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
863 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
864 surface_state
= desc
->buffer_view
->surface_state
;
865 assert(surface_state
.alloc_size
);
866 bo
= desc
->buffer_view
->bo
;
867 bo_offset
= desc
->buffer_view
->offset
;
870 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
871 surface_state
= desc
->buffer_view
->storage_surface_state
;
872 assert(surface_state
.alloc_size
);
873 bo
= desc
->buffer_view
->bo
;
874 bo_offset
= desc
->buffer_view
->offset
;
876 struct brw_image_param
*image_param
=
877 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
879 *image_param
= desc
->buffer_view
->storage_image_param
;
880 image_param
->surface_idx
= bias
+ s
;
884 assert(!"Invalid descriptor type");
888 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
889 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
891 assert(image
== map
->image_count
);
894 if (!cmd_buffer
->device
->info
.has_llc
)
895 anv_state_clflush(*bt_state
);
901 anv_cmd_buffer_emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
902 gl_shader_stage stage
, struct anv_state
*state
)
904 struct anv_pipeline_bind_map
*map
;
906 if (stage
== MESA_SHADER_COMPUTE
)
907 map
= &cmd_buffer
->state
.compute_pipeline
->bindings
[stage
];
909 map
= &cmd_buffer
->state
.pipeline
->bindings
[stage
];
911 if (map
->sampler_count
== 0) {
912 *state
= (struct anv_state
) { 0, };
916 uint32_t size
= map
->sampler_count
* 16;
917 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
919 if (state
->map
== NULL
)
920 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
922 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
923 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
924 struct anv_descriptor_set
*set
=
925 cmd_buffer
->state
.descriptors
[binding
->set
];
926 struct anv_descriptor
*desc
= &set
->descriptors
[binding
->offset
];
928 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
929 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
932 struct anv_sampler
*sampler
= desc
->sampler
;
934 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
935 * happens to be zero.
940 memcpy(state
->map
+ (s
* 16),
941 sampler
->state
, sizeof(sampler
->state
));
944 if (!cmd_buffer
->device
->info
.has_llc
)
945 anv_state_clflush(*state
);
951 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
952 const void *data
, uint32_t size
, uint32_t alignment
)
954 struct anv_state state
;
956 state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, alignment
);
957 memcpy(state
.map
, data
, size
);
959 if (!cmd_buffer
->device
->info
.has_llc
)
960 anv_state_clflush(state
);
962 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state
.map
, size
));
968 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer
*cmd_buffer
,
969 uint32_t *a
, uint32_t *b
,
970 uint32_t dwords
, uint32_t alignment
)
972 struct anv_state state
;
975 state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
976 dwords
* 4, alignment
);
978 for (uint32_t i
= 0; i
< dwords
; i
++)
981 if (!cmd_buffer
->device
->info
.has_llc
)
982 anv_state_clflush(state
);
984 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p
, dwords
* 4));
990 * @brief Setup the command buffer for recording commands inside the given
993 * This does not record all commands needed for starting the subpass.
994 * Starting the subpass may require additional commands.
996 * Note that vkCmdBeginRenderPass, vkCmdNextSubpass, and vkBeginCommandBuffer
997 * with VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT, all setup the
998 * command buffer for recording commands for some subpass. But only the first
999 * two, vkCmdBeginRenderPass and vkCmdNextSubpass, can start a subpass.
1002 anv_cmd_buffer_set_subpass(struct anv_cmd_buffer
*cmd_buffer
,
1003 struct anv_subpass
*subpass
)
1005 switch (cmd_buffer
->device
->info
.gen
) {
1007 if (cmd_buffer
->device
->info
.is_haswell
) {
1008 gen75_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1010 gen7_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1014 gen8_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1017 gen9_cmd_buffer_set_subpass(cmd_buffer
, subpass
);
1020 unreachable("unsupported gen\n");
1025 anv_cmd_buffer_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
1026 gl_shader_stage stage
)
1028 struct anv_push_constants
*data
=
1029 cmd_buffer
->state
.push_constants
[stage
];
1030 const struct brw_stage_prog_data
*prog_data
=
1031 cmd_buffer
->state
.pipeline
->prog_data
[stage
];
1033 /* If we don't actually have any push constants, bail. */
1034 if (data
== NULL
|| prog_data
->nr_params
== 0)
1035 return (struct anv_state
) { .offset
= 0 };
1037 struct anv_state state
=
1038 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
1039 prog_data
->nr_params
* sizeof(float),
1040 32 /* bottom 5 bits MBZ */);
1042 /* Walk through the param array and fill the buffer with data */
1043 uint32_t *u32_map
= state
.map
;
1044 for (unsigned i
= 0; i
< prog_data
->nr_params
; i
++) {
1045 uint32_t offset
= (uintptr_t)prog_data
->param
[i
];
1046 u32_map
[i
] = *(uint32_t *)((uint8_t *)data
+ offset
);
1049 if (!cmd_buffer
->device
->info
.has_llc
)
1050 anv_state_clflush(state
);
1056 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1058 struct anv_push_constants
*data
=
1059 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
1060 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1061 const struct brw_cs_prog_data
*cs_prog_data
= get_cs_prog_data(pipeline
);
1062 const struct brw_stage_prog_data
*prog_data
= &cs_prog_data
->base
;
1064 const unsigned local_id_dwords
= cs_prog_data
->local_invocation_id_regs
* 8;
1065 const unsigned push_constant_data_size
=
1066 (local_id_dwords
+ prog_data
->nr_params
) * 4;
1067 const unsigned reg_aligned_constant_size
= ALIGN(push_constant_data_size
, 32);
1068 const unsigned param_aligned_count
=
1069 reg_aligned_constant_size
/ sizeof(uint32_t);
1071 /* If we don't actually have any push constants, bail. */
1072 if (reg_aligned_constant_size
== 0)
1073 return (struct anv_state
) { .offset
= 0 };
1075 const unsigned threads
= pipeline
->cs_thread_width_max
;
1076 const unsigned total_push_constants_size
=
1077 reg_aligned_constant_size
* threads
;
1078 const unsigned push_constant_alignment
=
1079 cmd_buffer
->device
->info
.gen
< 8 ? 32 : 64;
1080 const unsigned aligned_total_push_constants_size
=
1081 ALIGN(total_push_constants_size
, push_constant_alignment
);
1082 struct anv_state state
=
1083 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
,
1084 aligned_total_push_constants_size
,
1085 push_constant_alignment
);
1087 /* Walk through the param array and fill the buffer with data */
1088 uint32_t *u32_map
= state
.map
;
1090 brw_cs_fill_local_id_payload(cs_prog_data
, u32_map
, threads
,
1091 reg_aligned_constant_size
);
1093 /* Setup uniform data for the first thread */
1094 for (unsigned i
= 0; i
< prog_data
->nr_params
; i
++) {
1095 uint32_t offset
= (uintptr_t)prog_data
->param
[i
];
1096 u32_map
[local_id_dwords
+ i
] = *(uint32_t *)((uint8_t *)data
+ offset
);
1099 /* Copy uniform data from the first thread to every other thread */
1100 const size_t uniform_data_size
= prog_data
->nr_params
* sizeof(uint32_t);
1101 for (unsigned t
= 1; t
< threads
; t
++) {
1102 memcpy(&u32_map
[t
* param_aligned_count
+ local_id_dwords
],
1103 &u32_map
[local_id_dwords
],
1107 if (!cmd_buffer
->device
->info
.has_llc
)
1108 anv_state_clflush(state
);
1113 void anv_CmdPushConstants(
1114 VkCommandBuffer commandBuffer
,
1115 VkPipelineLayout layout
,
1116 VkShaderStageFlags stageFlags
,
1119 const void* pValues
)
1121 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1123 anv_foreach_stage(stage
, stageFlags
) {
1124 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, client_data
);
1126 memcpy(cmd_buffer
->state
.push_constants
[stage
]->client_data
+ offset
,
1130 cmd_buffer
->state
.push_constants_dirty
|= stageFlags
;
1133 void anv_CmdExecuteCommands(
1134 VkCommandBuffer commandBuffer
,
1135 uint32_t commandBufferCount
,
1136 const VkCommandBuffer
* pCmdBuffers
)
1138 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1140 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1142 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1143 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1145 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1147 anv_cmd_buffer_add_secondary(primary
, secondary
);
1151 VkResult
anv_CreateCommandPool(
1153 const VkCommandPoolCreateInfo
* pCreateInfo
,
1154 const VkAllocationCallbacks
* pAllocator
,
1155 VkCommandPool
* pCmdPool
)
1157 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1158 struct anv_cmd_pool
*pool
;
1160 pool
= anv_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
1161 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1163 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1166 pool
->alloc
= *pAllocator
;
1168 pool
->alloc
= device
->alloc
;
1170 list_inithead(&pool
->cmd_buffers
);
1172 *pCmdPool
= anv_cmd_pool_to_handle(pool
);
1177 void anv_DestroyCommandPool(
1179 VkCommandPool commandPool
,
1180 const VkAllocationCallbacks
* pAllocator
)
1182 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1183 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, commandPool
);
1185 anv_ResetCommandPool(_device
, commandPool
, 0);
1187 anv_free2(&device
->alloc
, pAllocator
, pool
);
1190 VkResult
anv_ResetCommandPool(
1192 VkCommandPool commandPool
,
1193 VkCommandPoolResetFlags flags
)
1195 ANV_FROM_HANDLE(anv_cmd_pool
, pool
, commandPool
);
1197 /* FIXME: vkResetCommandPool must not destroy its command buffers. The
1198 * Vulkan 1.0 spec requires that it only reset them:
1200 * Resetting a command pool recycles all of the resources from all of
1201 * the command buffers allocated from the command pool back to the
1202 * command pool. All command buffers that have been allocated from the
1203 * command pool are put in the initial state.
1205 list_for_each_entry_safe(struct anv_cmd_buffer
, cmd_buffer
,
1206 &pool
->cmd_buffers
, pool_link
) {
1207 anv_cmd_buffer_destroy(cmd_buffer
);
1214 * Return NULL if the current subpass has no depthstencil attachment.
1216 const struct anv_image_view
*
1217 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer
*cmd_buffer
)
1219 const struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1220 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
1222 if (subpass
->depth_stencil_attachment
== VK_ATTACHMENT_UNUSED
)
1225 const struct anv_image_view
*iview
=
1226 fb
->attachments
[subpass
->depth_stencil_attachment
];
1228 assert(iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1229 VK_IMAGE_ASPECT_STENCIL_BIT
));