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[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33
34 /** \file anv_cmd_buffer.c
35 *
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
41 */
42
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
45 .viewport = {
46 .count = 0,
47 },
48 .scissor = {
49 .count = 0,
50 },
51 .line_width = 1.0f,
52 .depth_bias = {
53 .bias = 0.0f,
54 .clamp = 0.0f,
55 .slope = 0.0f,
56 },
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
58 .depth_bounds = {
59 .min = 0.0f,
60 .max = 1.0f,
61 },
62 .stencil_compare_mask = {
63 .front = ~0u,
64 .back = ~0u,
65 },
66 .stencil_write_mask = {
67 .front = ~0u,
68 .back = ~0u,
69 },
70 .stencil_reference = {
71 .front = 0u,
72 .back = 0u,
73 },
74 };
75
76 void
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
79 uint32_t copy_mask)
80 {
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
84 src->viewport.count);
85 }
86
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
90 src->scissor.count);
91 }
92
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
113 }
114
115 static void
116 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
117 {
118 struct anv_cmd_state *state = &cmd_buffer->state;
119
120 cmd_buffer->batch.status = VK_SUCCESS;
121
122 memset(&state->descriptors, 0, sizeof(state->descriptors));
123 for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++) {
124 vk_free(&cmd_buffer->pool->alloc, state->push_descriptors[i]);
125 state->push_descriptors[i] = NULL;
126 }
127 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
128 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
129 state->push_constants[i] = NULL;
130 }
131 memset(state->binding_tables, 0, sizeof(state->binding_tables));
132 memset(state->samplers, 0, sizeof(state->samplers));
133
134 /* 0 isn't a valid config. This ensures that we always configure L3$. */
135 cmd_buffer->state.current_l3_config = 0;
136
137 state->dirty = 0;
138 state->vb_dirty = 0;
139 state->pending_pipe_bits = 0;
140 state->descriptors_dirty = 0;
141 state->push_constants_dirty = 0;
142 state->pipeline = NULL;
143 state->framebuffer = NULL;
144 state->pass = NULL;
145 state->subpass = NULL;
146 state->push_constant_stages = 0;
147 state->restart_index = UINT32_MAX;
148 state->dynamic = default_dynamic_state;
149 state->need_query_wa = true;
150 state->pma_fix_enabled = false;
151 state->hiz_enabled = false;
152
153 vk_free(&cmd_buffer->pool->alloc, state->attachments);
154 state->attachments = NULL;
155
156 state->gen7.index_buffer = NULL;
157 }
158
159 VkResult
160 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
161 gl_shader_stage stage, uint32_t size)
162 {
163 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
164
165 if (*ptr == NULL) {
166 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
168 if (*ptr == NULL) {
169 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
170 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
171 }
172 } else if ((*ptr)->size < size) {
173 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
174 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
175 if (*ptr == NULL) {
176 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
177 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
178 }
179 }
180 (*ptr)->size = size;
181
182 return VK_SUCCESS;
183 }
184
185 static VkResult anv_create_cmd_buffer(
186 struct anv_device * device,
187 struct anv_cmd_pool * pool,
188 VkCommandBufferLevel level,
189 VkCommandBuffer* pCommandBuffer)
190 {
191 struct anv_cmd_buffer *cmd_buffer;
192 VkResult result;
193
194 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
195 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
196 if (cmd_buffer == NULL)
197 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
198
199 cmd_buffer->batch.status = VK_SUCCESS;
200
201 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
202 cmd_buffer->state.push_constants[i] = NULL;
203 }
204 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
205 cmd_buffer->device = device;
206 cmd_buffer->pool = pool;
207 cmd_buffer->level = level;
208 cmd_buffer->state.attachments = NULL;
209
210 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
211 if (result != VK_SUCCESS)
212 goto fail;
213
214 anv_state_stream_init(&cmd_buffer->surface_state_stream,
215 &device->surface_state_pool, 4096);
216 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
217 &device->dynamic_state_pool, 16384);
218
219 memset(cmd_buffer->state.push_descriptors, 0,
220 sizeof(cmd_buffer->state.push_descriptors));
221
222 if (pool) {
223 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
224 } else {
225 /* Init the pool_link so we can safefly call list_del when we destroy
226 * the command buffer
227 */
228 list_inithead(&cmd_buffer->pool_link);
229 }
230
231 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
232
233 return VK_SUCCESS;
234
235 fail:
236 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
237
238 return result;
239 }
240
241 VkResult anv_AllocateCommandBuffers(
242 VkDevice _device,
243 const VkCommandBufferAllocateInfo* pAllocateInfo,
244 VkCommandBuffer* pCommandBuffers)
245 {
246 ANV_FROM_HANDLE(anv_device, device, _device);
247 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
248
249 VkResult result = VK_SUCCESS;
250 uint32_t i;
251
252 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
253 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
254 &pCommandBuffers[i]);
255 if (result != VK_SUCCESS)
256 break;
257 }
258
259 if (result != VK_SUCCESS) {
260 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
261 i, pCommandBuffers);
262 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
263 pCommandBuffers[i] = VK_NULL_HANDLE;
264 }
265
266 return result;
267 }
268
269 static void
270 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
271 {
272 list_del(&cmd_buffer->pool_link);
273
274 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
275
276 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
277 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
278
279 anv_cmd_state_reset(cmd_buffer);
280
281 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
282 }
283
284 void anv_FreeCommandBuffers(
285 VkDevice device,
286 VkCommandPool commandPool,
287 uint32_t commandBufferCount,
288 const VkCommandBuffer* pCommandBuffers)
289 {
290 for (uint32_t i = 0; i < commandBufferCount; i++) {
291 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
292
293 if (!cmd_buffer)
294 continue;
295
296 anv_cmd_buffer_destroy(cmd_buffer);
297 }
298 }
299
300 VkResult
301 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
302 {
303 cmd_buffer->usage_flags = 0;
304 cmd_buffer->state.current_pipeline = UINT32_MAX;
305 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
306 anv_cmd_state_reset(cmd_buffer);
307
308 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
309 anv_state_stream_init(&cmd_buffer->surface_state_stream,
310 &cmd_buffer->device->surface_state_pool, 4096);
311
312 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
313 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
314 &cmd_buffer->device->dynamic_state_pool, 16384);
315 return VK_SUCCESS;
316 }
317
318 VkResult anv_ResetCommandBuffer(
319 VkCommandBuffer commandBuffer,
320 VkCommandBufferResetFlags flags)
321 {
322 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
323 return anv_cmd_buffer_reset(cmd_buffer);
324 }
325
326 void
327 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
328 {
329 switch (cmd_buffer->device->info.gen) {
330 case 7:
331 if (cmd_buffer->device->info.is_haswell)
332 return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
333 else
334 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
335 case 8:
336 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
337 case 9:
338 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
339 case 10:
340 return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
341 default:
342 unreachable("unsupported gen\n");
343 }
344 }
345
346 void anv_CmdBindPipeline(
347 VkCommandBuffer commandBuffer,
348 VkPipelineBindPoint pipelineBindPoint,
349 VkPipeline _pipeline)
350 {
351 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
352 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
353
354 switch (pipelineBindPoint) {
355 case VK_PIPELINE_BIND_POINT_COMPUTE:
356 cmd_buffer->state.compute_pipeline = pipeline;
357 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
358 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
359 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
360 break;
361
362 case VK_PIPELINE_BIND_POINT_GRAPHICS:
363 cmd_buffer->state.pipeline = pipeline;
364 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
365 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
366 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
367 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
368
369 /* Apply the dynamic state from the pipeline */
370 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
371 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
372 &pipeline->dynamic_state,
373 pipeline->dynamic_state_mask);
374 break;
375
376 default:
377 assert(!"invalid bind point");
378 break;
379 }
380 }
381
382 void anv_CmdSetViewport(
383 VkCommandBuffer commandBuffer,
384 uint32_t firstViewport,
385 uint32_t viewportCount,
386 const VkViewport* pViewports)
387 {
388 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
389
390 const uint32_t total_count = firstViewport + viewportCount;
391 if (cmd_buffer->state.dynamic.viewport.count < total_count)
392 cmd_buffer->state.dynamic.viewport.count = total_count;
393
394 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
395 pViewports, viewportCount * sizeof(*pViewports));
396
397 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
398 }
399
400 void anv_CmdSetScissor(
401 VkCommandBuffer commandBuffer,
402 uint32_t firstScissor,
403 uint32_t scissorCount,
404 const VkRect2D* pScissors)
405 {
406 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
407
408 const uint32_t total_count = firstScissor + scissorCount;
409 if (cmd_buffer->state.dynamic.scissor.count < total_count)
410 cmd_buffer->state.dynamic.scissor.count = total_count;
411
412 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
413 pScissors, scissorCount * sizeof(*pScissors));
414
415 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
416 }
417
418 void anv_CmdSetLineWidth(
419 VkCommandBuffer commandBuffer,
420 float lineWidth)
421 {
422 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
423
424 cmd_buffer->state.dynamic.line_width = lineWidth;
425 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
426 }
427
428 void anv_CmdSetDepthBias(
429 VkCommandBuffer commandBuffer,
430 float depthBiasConstantFactor,
431 float depthBiasClamp,
432 float depthBiasSlopeFactor)
433 {
434 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
435
436 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
437 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
438 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
439
440 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
441 }
442
443 void anv_CmdSetBlendConstants(
444 VkCommandBuffer commandBuffer,
445 const float blendConstants[4])
446 {
447 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
448
449 memcpy(cmd_buffer->state.dynamic.blend_constants,
450 blendConstants, sizeof(float) * 4);
451
452 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
453 }
454
455 void anv_CmdSetDepthBounds(
456 VkCommandBuffer commandBuffer,
457 float minDepthBounds,
458 float maxDepthBounds)
459 {
460 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
461
462 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
463 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
464
465 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
466 }
467
468 void anv_CmdSetStencilCompareMask(
469 VkCommandBuffer commandBuffer,
470 VkStencilFaceFlags faceMask,
471 uint32_t compareMask)
472 {
473 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
474
475 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
476 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
477 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
478 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
479
480 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
481 }
482
483 void anv_CmdSetStencilWriteMask(
484 VkCommandBuffer commandBuffer,
485 VkStencilFaceFlags faceMask,
486 uint32_t writeMask)
487 {
488 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
489
490 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
491 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
492 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
493 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
494
495 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
496 }
497
498 void anv_CmdSetStencilReference(
499 VkCommandBuffer commandBuffer,
500 VkStencilFaceFlags faceMask,
501 uint32_t reference)
502 {
503 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
504
505 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
506 cmd_buffer->state.dynamic.stencil_reference.front = reference;
507 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
508 cmd_buffer->state.dynamic.stencil_reference.back = reference;
509
510 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
511 }
512
513 void anv_CmdBindDescriptorSets(
514 VkCommandBuffer commandBuffer,
515 VkPipelineBindPoint pipelineBindPoint,
516 VkPipelineLayout _layout,
517 uint32_t firstSet,
518 uint32_t descriptorSetCount,
519 const VkDescriptorSet* pDescriptorSets,
520 uint32_t dynamicOffsetCount,
521 const uint32_t* pDynamicOffsets)
522 {
523 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
524 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
525 struct anv_descriptor_set_layout *set_layout;
526
527 assert(firstSet + descriptorSetCount < MAX_SETS);
528
529 uint32_t dynamic_slot = 0;
530 for (uint32_t i = 0; i < descriptorSetCount; i++) {
531 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
532 set_layout = layout->set[firstSet + i].layout;
533
534 cmd_buffer->state.descriptors[firstSet + i] = set;
535
536 if (set_layout->dynamic_offset_count > 0) {
537 uint32_t dynamic_offset_start =
538 layout->set[firstSet + i].dynamic_offset_start;
539
540 /* Assert that everything is in range */
541 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
542 ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
543 assert(dynamic_slot + set_layout->dynamic_offset_count <=
544 dynamicOffsetCount);
545
546 typed_memcpy(&cmd_buffer->state.dynamic_offsets[dynamic_offset_start],
547 &pDynamicOffsets[dynamic_slot],
548 set_layout->dynamic_offset_count);
549
550 dynamic_slot += set_layout->dynamic_offset_count;
551 }
552
553 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
554 }
555 }
556
557 void anv_CmdBindVertexBuffers(
558 VkCommandBuffer commandBuffer,
559 uint32_t firstBinding,
560 uint32_t bindingCount,
561 const VkBuffer* pBuffers,
562 const VkDeviceSize* pOffsets)
563 {
564 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
565 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
566
567 /* We have to defer setting up vertex buffer since we need the buffer
568 * stride from the pipeline. */
569
570 assert(firstBinding + bindingCount <= MAX_VBS);
571 for (uint32_t i = 0; i < bindingCount; i++) {
572 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
573 vb[firstBinding + i].offset = pOffsets[i];
574 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
575 }
576 }
577
578 enum isl_format
579 anv_isl_format_for_descriptor_type(VkDescriptorType type)
580 {
581 switch (type) {
582 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
583 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
584 return ISL_FORMAT_R32G32B32A32_FLOAT;
585
586 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
587 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
588 return ISL_FORMAT_RAW;
589
590 default:
591 unreachable("Invalid descriptor type");
592 }
593 }
594
595 struct anv_state
596 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
597 const void *data, uint32_t size, uint32_t alignment)
598 {
599 struct anv_state state;
600
601 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
602 memcpy(state.map, data, size);
603
604 anv_state_flush(cmd_buffer->device, state);
605
606 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
607
608 return state;
609 }
610
611 struct anv_state
612 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
613 uint32_t *a, uint32_t *b,
614 uint32_t dwords, uint32_t alignment)
615 {
616 struct anv_state state;
617 uint32_t *p;
618
619 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
620 dwords * 4, alignment);
621 p = state.map;
622 for (uint32_t i = 0; i < dwords; i++)
623 p[i] = a[i] | b[i];
624
625 anv_state_flush(cmd_buffer->device, state);
626
627 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
628
629 return state;
630 }
631
632 struct anv_state
633 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
634 gl_shader_stage stage)
635 {
636 /* If we don't have this stage, bail. */
637 if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
638 return (struct anv_state) { .offset = 0 };
639
640 struct anv_push_constants *data =
641 cmd_buffer->state.push_constants[stage];
642 const struct brw_stage_prog_data *prog_data =
643 cmd_buffer->state.pipeline->shaders[stage]->prog_data;
644
645 /* If we don't actually have any push constants, bail. */
646 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
647 return (struct anv_state) { .offset = 0 };
648
649 struct anv_state state =
650 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
651 prog_data->nr_params * sizeof(float),
652 32 /* bottom 5 bits MBZ */);
653
654 /* Walk through the param array and fill the buffer with data */
655 uint32_t *u32_map = state.map;
656 for (unsigned i = 0; i < prog_data->nr_params; i++) {
657 uint32_t offset = (uintptr_t)prog_data->param[i];
658 u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
659 }
660
661 anv_state_flush(cmd_buffer->device, state);
662
663 return state;
664 }
665
666 struct anv_state
667 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
668 {
669 struct anv_push_constants *data =
670 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
671 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
672 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
673 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
674
675 /* If we don't actually have any push constants, bail. */
676 if (cs_prog_data->push.total.size == 0)
677 return (struct anv_state) { .offset = 0 };
678
679 const unsigned push_constant_alignment =
680 cmd_buffer->device->info.gen < 8 ? 32 : 64;
681 const unsigned aligned_total_push_constants_size =
682 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
683 struct anv_state state =
684 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
685 aligned_total_push_constants_size,
686 push_constant_alignment);
687
688 /* Walk through the param array and fill the buffer with data */
689 uint32_t *u32_map = state.map;
690
691 if (cs_prog_data->push.cross_thread.size > 0) {
692 assert(cs_prog_data->thread_local_id_index < 0 ||
693 cs_prog_data->thread_local_id_index >=
694 cs_prog_data->push.cross_thread.dwords);
695 for (unsigned i = 0;
696 i < cs_prog_data->push.cross_thread.dwords;
697 i++) {
698 uint32_t offset = (uintptr_t)prog_data->param[i];
699 u32_map[i] = *(uint32_t *)((uint8_t *)data + offset);
700 }
701 }
702
703 if (cs_prog_data->push.per_thread.size > 0) {
704 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
705 unsigned dst =
706 8 * (cs_prog_data->push.per_thread.regs * t +
707 cs_prog_data->push.cross_thread.regs);
708 unsigned src = cs_prog_data->push.cross_thread.dwords;
709 for ( ; src < prog_data->nr_params; src++, dst++) {
710 if (src != cs_prog_data->thread_local_id_index) {
711 uint32_t offset = (uintptr_t)prog_data->param[src];
712 u32_map[dst] = *(uint32_t *)((uint8_t *)data + offset);
713 } else {
714 u32_map[dst] = t * cs_prog_data->simd_size;
715 }
716 }
717 }
718 }
719
720 anv_state_flush(cmd_buffer->device, state);
721
722 return state;
723 }
724
725 void anv_CmdPushConstants(
726 VkCommandBuffer commandBuffer,
727 VkPipelineLayout layout,
728 VkShaderStageFlags stageFlags,
729 uint32_t offset,
730 uint32_t size,
731 const void* pValues)
732 {
733 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
734
735 anv_foreach_stage(stage, stageFlags) {
736 VkResult result =
737 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
738 stage, client_data);
739 if (result != VK_SUCCESS)
740 return;
741
742 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
743 pValues, size);
744 }
745
746 cmd_buffer->state.push_constants_dirty |= stageFlags;
747 }
748
749 VkResult anv_CreateCommandPool(
750 VkDevice _device,
751 const VkCommandPoolCreateInfo* pCreateInfo,
752 const VkAllocationCallbacks* pAllocator,
753 VkCommandPool* pCmdPool)
754 {
755 ANV_FROM_HANDLE(anv_device, device, _device);
756 struct anv_cmd_pool *pool;
757
758 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
759 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
760 if (pool == NULL)
761 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
762
763 if (pAllocator)
764 pool->alloc = *pAllocator;
765 else
766 pool->alloc = device->alloc;
767
768 list_inithead(&pool->cmd_buffers);
769
770 *pCmdPool = anv_cmd_pool_to_handle(pool);
771
772 return VK_SUCCESS;
773 }
774
775 void anv_DestroyCommandPool(
776 VkDevice _device,
777 VkCommandPool commandPool,
778 const VkAllocationCallbacks* pAllocator)
779 {
780 ANV_FROM_HANDLE(anv_device, device, _device);
781 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
782
783 if (!pool)
784 return;
785
786 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
787 &pool->cmd_buffers, pool_link) {
788 anv_cmd_buffer_destroy(cmd_buffer);
789 }
790
791 vk_free2(&device->alloc, pAllocator, pool);
792 }
793
794 VkResult anv_ResetCommandPool(
795 VkDevice device,
796 VkCommandPool commandPool,
797 VkCommandPoolResetFlags flags)
798 {
799 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
800
801 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
802 &pool->cmd_buffers, pool_link) {
803 anv_cmd_buffer_reset(cmd_buffer);
804 }
805
806 return VK_SUCCESS;
807 }
808
809 void anv_TrimCommandPoolKHR(
810 VkDevice device,
811 VkCommandPool commandPool,
812 VkCommandPoolTrimFlagsKHR flags)
813 {
814 /* Nothing for us to do here. Our pools stay pretty tidy. */
815 }
816
817 /**
818 * Return NULL if the current subpass has no depthstencil attachment.
819 */
820 const struct anv_image_view *
821 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
822 {
823 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
824 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
825
826 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
827 return NULL;
828
829 const struct anv_image_view *iview =
830 fb->attachments[subpass->depth_stencil_attachment.attachment];
831
832 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
833 VK_IMAGE_ASPECT_STENCIL_BIT));
834
835 return iview;
836 }
837
838 static VkResult
839 anv_cmd_buffer_ensure_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
840 uint32_t set)
841 {
842 struct anv_push_descriptor_set **push_set =
843 &cmd_buffer->state.push_descriptors[set];
844
845 if (*push_set == NULL) {
846 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
847 sizeof(struct anv_push_descriptor_set), 8,
848 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
849 if (*push_set == NULL) {
850 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
851 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
852 }
853 }
854
855 return VK_SUCCESS;
856 }
857
858 void anv_CmdPushDescriptorSetKHR(
859 VkCommandBuffer commandBuffer,
860 VkPipelineBindPoint pipelineBindPoint,
861 VkPipelineLayout _layout,
862 uint32_t _set,
863 uint32_t descriptorWriteCount,
864 const VkWriteDescriptorSet* pDescriptorWrites)
865 {
866 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
867 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
868
869 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS ||
870 pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
871 assert(_set < MAX_SETS);
872
873 const struct anv_descriptor_set_layout *set_layout =
874 layout->set[_set].layout;
875
876 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
877 return;
878 struct anv_push_descriptor_set *push_set =
879 cmd_buffer->state.push_descriptors[_set];
880 struct anv_descriptor_set *set = &push_set->set;
881
882 set->layout = set_layout;
883 set->size = anv_descriptor_set_layout_size(set_layout);
884 set->buffer_count = set_layout->buffer_count;
885 set->buffer_views = push_set->buffer_views;
886
887 /* Go through the user supplied descriptors. */
888 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
889 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
890
891 switch (write->descriptorType) {
892 case VK_DESCRIPTOR_TYPE_SAMPLER:
893 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
894 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
895 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
896 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
897 for (uint32_t j = 0; j < write->descriptorCount; j++) {
898 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
899 write->pImageInfo + j,
900 write->descriptorType,
901 write->dstBinding,
902 write->dstArrayElement + j);
903 }
904 break;
905
906 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
907 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
908 for (uint32_t j = 0; j < write->descriptorCount; j++) {
909 ANV_FROM_HANDLE(anv_buffer_view, bview,
910 write->pTexelBufferView[j]);
911
912 anv_descriptor_set_write_buffer_view(set,
913 write->descriptorType,
914 bview,
915 write->dstBinding,
916 write->dstArrayElement + j);
917 }
918 break;
919
920 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
921 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
922 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
923 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
924 for (uint32_t j = 0; j < write->descriptorCount; j++) {
925 assert(write->pBufferInfo[j].buffer);
926 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
927 assert(buffer);
928
929 anv_descriptor_set_write_buffer(set,
930 cmd_buffer->device,
931 &cmd_buffer->surface_state_stream,
932 write->descriptorType,
933 buffer,
934 write->dstBinding,
935 write->dstArrayElement + j,
936 write->pBufferInfo[j].offset,
937 write->pBufferInfo[j].range);
938 }
939 break;
940
941 default:
942 break;
943 }
944 }
945
946 cmd_buffer->state.descriptors[_set] = set;
947 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
948 }
949
950 void anv_CmdPushDescriptorSetWithTemplateKHR(
951 VkCommandBuffer commandBuffer,
952 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
953 VkPipelineLayout _layout,
954 uint32_t _set,
955 const void* pData)
956 {
957 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
958 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
959 descriptorUpdateTemplate);
960 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
961
962 assert(_set < MAX_PUSH_DESCRIPTORS);
963
964 const struct anv_descriptor_set_layout *set_layout =
965 layout->set[_set].layout;
966
967 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
968 return;
969 struct anv_push_descriptor_set *push_set =
970 cmd_buffer->state.push_descriptors[_set];
971 struct anv_descriptor_set *set = &push_set->set;
972
973 set->layout = set_layout;
974 set->size = anv_descriptor_set_layout_size(set_layout);
975 set->buffer_count = set_layout->buffer_count;
976 set->buffer_views = push_set->buffer_views;
977
978 anv_descriptor_set_write_template(set,
979 cmd_buffer->device,
980 &cmd_buffer->surface_state_stream,
981 template,
982 pData);
983
984 cmd_buffer->state.descriptors[_set] = set;
985 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
986 }