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c0270e128f74cf854d2e2ae1f36dd03900e6490c
[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33
34 /** \file anv_cmd_buffer.c
35 *
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
41 */
42
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
45 .viewport = {
46 .count = 0,
47 },
48 .scissor = {
49 .count = 0,
50 },
51 .line_width = 1.0f,
52 .depth_bias = {
53 .bias = 0.0f,
54 .clamp = 0.0f,
55 .slope = 0.0f,
56 },
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
58 .depth_bounds = {
59 .min = 0.0f,
60 .max = 1.0f,
61 },
62 .stencil_compare_mask = {
63 .front = ~0u,
64 .back = ~0u,
65 },
66 .stencil_write_mask = {
67 .front = ~0u,
68 .back = ~0u,
69 },
70 .stencil_reference = {
71 .front = 0u,
72 .back = 0u,
73 },
74 };
75
76 void
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
79 uint32_t copy_mask)
80 {
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
84 src->viewport.count);
85 }
86
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
90 src->scissor.count);
91 }
92
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
113 }
114
115 static void
116 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
117 {
118 struct anv_cmd_state *state = &cmd_buffer->state;
119
120 cmd_buffer->batch.status = VK_SUCCESS;
121
122 memset(&state->descriptors, 0, sizeof(state->descriptors));
123 for (uint32_t i = 0; i < ARRAY_SIZE(state->push_descriptors); i++) {
124 vk_free(&cmd_buffer->pool->alloc, state->push_descriptors[i]);
125 state->push_descriptors[i] = NULL;
126 }
127 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
128 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
129 state->push_constants[i] = NULL;
130 }
131 memset(state->binding_tables, 0, sizeof(state->binding_tables));
132 memset(state->samplers, 0, sizeof(state->samplers));
133
134 /* 0 isn't a valid config. This ensures that we always configure L3$. */
135 cmd_buffer->state.current_l3_config = 0;
136
137 state->dirty = 0;
138 state->vb_dirty = 0;
139 state->pending_pipe_bits = 0;
140 state->descriptors_dirty = 0;
141 state->push_constants_dirty = 0;
142 state->pipeline = NULL;
143 state->framebuffer = NULL;
144 state->pass = NULL;
145 state->subpass = NULL;
146 state->push_constant_stages = 0;
147 state->restart_index = UINT32_MAX;
148 state->dynamic = default_dynamic_state;
149 state->pma_fix_enabled = false;
150 state->hiz_enabled = false;
151
152 vk_free(&cmd_buffer->pool->alloc, state->attachments);
153 state->attachments = NULL;
154
155 state->gen7.index_buffer = NULL;
156 }
157
158 VkResult
159 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
160 gl_shader_stage stage, uint32_t size)
161 {
162 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
163
164 if (*ptr == NULL) {
165 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
166 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
167 if (*ptr == NULL) {
168 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
169 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
170 }
171 } else if ((*ptr)->size < size) {
172 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
173 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
174 if (*ptr == NULL) {
175 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
176 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
177 }
178 }
179 (*ptr)->size = size;
180
181 return VK_SUCCESS;
182 }
183
184 static VkResult anv_create_cmd_buffer(
185 struct anv_device * device,
186 struct anv_cmd_pool * pool,
187 VkCommandBufferLevel level,
188 VkCommandBuffer* pCommandBuffer)
189 {
190 struct anv_cmd_buffer *cmd_buffer;
191 VkResult result;
192
193 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
194 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
195 if (cmd_buffer == NULL)
196 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
197
198 cmd_buffer->batch.status = VK_SUCCESS;
199
200 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
201 cmd_buffer->state.push_constants[i] = NULL;
202 }
203 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
204 cmd_buffer->device = device;
205 cmd_buffer->pool = pool;
206 cmd_buffer->level = level;
207 cmd_buffer->state.attachments = NULL;
208
209 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
210 if (result != VK_SUCCESS)
211 goto fail;
212
213 anv_state_stream_init(&cmd_buffer->surface_state_stream,
214 &device->surface_state_pool, 4096);
215 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
216 &device->dynamic_state_pool, 16384);
217
218 memset(cmd_buffer->state.push_descriptors, 0,
219 sizeof(cmd_buffer->state.push_descriptors));
220
221 if (pool) {
222 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
223 } else {
224 /* Init the pool_link so we can safefly call list_del when we destroy
225 * the command buffer
226 */
227 list_inithead(&cmd_buffer->pool_link);
228 }
229
230 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
231
232 return VK_SUCCESS;
233
234 fail:
235 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
236
237 return result;
238 }
239
240 VkResult anv_AllocateCommandBuffers(
241 VkDevice _device,
242 const VkCommandBufferAllocateInfo* pAllocateInfo,
243 VkCommandBuffer* pCommandBuffers)
244 {
245 ANV_FROM_HANDLE(anv_device, device, _device);
246 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
247
248 VkResult result = VK_SUCCESS;
249 uint32_t i;
250
251 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
252 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
253 &pCommandBuffers[i]);
254 if (result != VK_SUCCESS)
255 break;
256 }
257
258 if (result != VK_SUCCESS) {
259 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
260 i, pCommandBuffers);
261 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
262 pCommandBuffers[i] = VK_NULL_HANDLE;
263 }
264
265 return result;
266 }
267
268 static void
269 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
270 {
271 list_del(&cmd_buffer->pool_link);
272
273 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
274
275 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
276 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
277
278 anv_cmd_state_reset(cmd_buffer);
279
280 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
281 }
282
283 void anv_FreeCommandBuffers(
284 VkDevice device,
285 VkCommandPool commandPool,
286 uint32_t commandBufferCount,
287 const VkCommandBuffer* pCommandBuffers)
288 {
289 for (uint32_t i = 0; i < commandBufferCount; i++) {
290 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
291
292 if (!cmd_buffer)
293 continue;
294
295 anv_cmd_buffer_destroy(cmd_buffer);
296 }
297 }
298
299 VkResult
300 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
301 {
302 cmd_buffer->usage_flags = 0;
303 cmd_buffer->state.current_pipeline = UINT32_MAX;
304 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
305 anv_cmd_state_reset(cmd_buffer);
306
307 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
308 anv_state_stream_init(&cmd_buffer->surface_state_stream,
309 &cmd_buffer->device->surface_state_pool, 4096);
310
311 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
312 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
313 &cmd_buffer->device->dynamic_state_pool, 16384);
314 return VK_SUCCESS;
315 }
316
317 VkResult anv_ResetCommandBuffer(
318 VkCommandBuffer commandBuffer,
319 VkCommandBufferResetFlags flags)
320 {
321 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
322 return anv_cmd_buffer_reset(cmd_buffer);
323 }
324
325 void
326 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
327 {
328 switch (cmd_buffer->device->info.gen) {
329 case 7:
330 if (cmd_buffer->device->info.is_haswell)
331 return gen75_cmd_buffer_emit_state_base_address(cmd_buffer);
332 else
333 return gen7_cmd_buffer_emit_state_base_address(cmd_buffer);
334 case 8:
335 return gen8_cmd_buffer_emit_state_base_address(cmd_buffer);
336 case 9:
337 return gen9_cmd_buffer_emit_state_base_address(cmd_buffer);
338 case 10:
339 return gen10_cmd_buffer_emit_state_base_address(cmd_buffer);
340 default:
341 unreachable("unsupported gen\n");
342 }
343 }
344
345 void anv_CmdBindPipeline(
346 VkCommandBuffer commandBuffer,
347 VkPipelineBindPoint pipelineBindPoint,
348 VkPipeline _pipeline)
349 {
350 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
351 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
352
353 switch (pipelineBindPoint) {
354 case VK_PIPELINE_BIND_POINT_COMPUTE:
355 cmd_buffer->state.compute_pipeline = pipeline;
356 cmd_buffer->state.compute_dirty |= ANV_CMD_DIRTY_PIPELINE;
357 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
358 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
359 break;
360
361 case VK_PIPELINE_BIND_POINT_GRAPHICS:
362 cmd_buffer->state.pipeline = pipeline;
363 cmd_buffer->state.vb_dirty |= pipeline->vb_used;
364 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_PIPELINE;
365 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
366 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
367
368 /* Apply the dynamic state from the pipeline */
369 cmd_buffer->state.dirty |= pipeline->dynamic_state_mask;
370 anv_dynamic_state_copy(&cmd_buffer->state.dynamic,
371 &pipeline->dynamic_state,
372 pipeline->dynamic_state_mask);
373 break;
374
375 default:
376 assert(!"invalid bind point");
377 break;
378 }
379 }
380
381 void anv_CmdSetViewport(
382 VkCommandBuffer commandBuffer,
383 uint32_t firstViewport,
384 uint32_t viewportCount,
385 const VkViewport* pViewports)
386 {
387 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
388
389 const uint32_t total_count = firstViewport + viewportCount;
390 if (cmd_buffer->state.dynamic.viewport.count < total_count)
391 cmd_buffer->state.dynamic.viewport.count = total_count;
392
393 memcpy(cmd_buffer->state.dynamic.viewport.viewports + firstViewport,
394 pViewports, viewportCount * sizeof(*pViewports));
395
396 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
397 }
398
399 void anv_CmdSetScissor(
400 VkCommandBuffer commandBuffer,
401 uint32_t firstScissor,
402 uint32_t scissorCount,
403 const VkRect2D* pScissors)
404 {
405 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
406
407 const uint32_t total_count = firstScissor + scissorCount;
408 if (cmd_buffer->state.dynamic.scissor.count < total_count)
409 cmd_buffer->state.dynamic.scissor.count = total_count;
410
411 memcpy(cmd_buffer->state.dynamic.scissor.scissors + firstScissor,
412 pScissors, scissorCount * sizeof(*pScissors));
413
414 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
415 }
416
417 void anv_CmdSetLineWidth(
418 VkCommandBuffer commandBuffer,
419 float lineWidth)
420 {
421 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
422
423 cmd_buffer->state.dynamic.line_width = lineWidth;
424 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
425 }
426
427 void anv_CmdSetDepthBias(
428 VkCommandBuffer commandBuffer,
429 float depthBiasConstantFactor,
430 float depthBiasClamp,
431 float depthBiasSlopeFactor)
432 {
433 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
434
435 cmd_buffer->state.dynamic.depth_bias.bias = depthBiasConstantFactor;
436 cmd_buffer->state.dynamic.depth_bias.clamp = depthBiasClamp;
437 cmd_buffer->state.dynamic.depth_bias.slope = depthBiasSlopeFactor;
438
439 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
440 }
441
442 void anv_CmdSetBlendConstants(
443 VkCommandBuffer commandBuffer,
444 const float blendConstants[4])
445 {
446 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
447
448 memcpy(cmd_buffer->state.dynamic.blend_constants,
449 blendConstants, sizeof(float) * 4);
450
451 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
452 }
453
454 void anv_CmdSetDepthBounds(
455 VkCommandBuffer commandBuffer,
456 float minDepthBounds,
457 float maxDepthBounds)
458 {
459 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
460
461 cmd_buffer->state.dynamic.depth_bounds.min = minDepthBounds;
462 cmd_buffer->state.dynamic.depth_bounds.max = maxDepthBounds;
463
464 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
465 }
466
467 void anv_CmdSetStencilCompareMask(
468 VkCommandBuffer commandBuffer,
469 VkStencilFaceFlags faceMask,
470 uint32_t compareMask)
471 {
472 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
473
474 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
475 cmd_buffer->state.dynamic.stencil_compare_mask.front = compareMask;
476 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
477 cmd_buffer->state.dynamic.stencil_compare_mask.back = compareMask;
478
479 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
480 }
481
482 void anv_CmdSetStencilWriteMask(
483 VkCommandBuffer commandBuffer,
484 VkStencilFaceFlags faceMask,
485 uint32_t writeMask)
486 {
487 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
488
489 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
490 cmd_buffer->state.dynamic.stencil_write_mask.front = writeMask;
491 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
492 cmd_buffer->state.dynamic.stencil_write_mask.back = writeMask;
493
494 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
495 }
496
497 void anv_CmdSetStencilReference(
498 VkCommandBuffer commandBuffer,
499 VkStencilFaceFlags faceMask,
500 uint32_t reference)
501 {
502 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
503
504 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
505 cmd_buffer->state.dynamic.stencil_reference.front = reference;
506 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
507 cmd_buffer->state.dynamic.stencil_reference.back = reference;
508
509 cmd_buffer->state.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
510 }
511
512 void anv_CmdBindDescriptorSets(
513 VkCommandBuffer commandBuffer,
514 VkPipelineBindPoint pipelineBindPoint,
515 VkPipelineLayout _layout,
516 uint32_t firstSet,
517 uint32_t descriptorSetCount,
518 const VkDescriptorSet* pDescriptorSets,
519 uint32_t dynamicOffsetCount,
520 const uint32_t* pDynamicOffsets)
521 {
522 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
523 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
524 struct anv_descriptor_set_layout *set_layout;
525
526 assert(firstSet + descriptorSetCount < MAX_SETS);
527
528 uint32_t dynamic_slot = 0;
529 for (uint32_t i = 0; i < descriptorSetCount; i++) {
530 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
531 set_layout = layout->set[firstSet + i].layout;
532
533 cmd_buffer->state.descriptors[firstSet + i] = set;
534
535 if (set_layout->dynamic_offset_count > 0) {
536 uint32_t dynamic_offset_start =
537 layout->set[firstSet + i].dynamic_offset_start;
538
539 /* Assert that everything is in range */
540 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
541 ARRAY_SIZE(cmd_buffer->state.dynamic_offsets));
542 assert(dynamic_slot + set_layout->dynamic_offset_count <=
543 dynamicOffsetCount);
544
545 typed_memcpy(&cmd_buffer->state.dynamic_offsets[dynamic_offset_start],
546 &pDynamicOffsets[dynamic_slot],
547 set_layout->dynamic_offset_count);
548
549 dynamic_slot += set_layout->dynamic_offset_count;
550 }
551
552 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
553 }
554 }
555
556 void anv_CmdBindVertexBuffers(
557 VkCommandBuffer commandBuffer,
558 uint32_t firstBinding,
559 uint32_t bindingCount,
560 const VkBuffer* pBuffers,
561 const VkDeviceSize* pOffsets)
562 {
563 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
564 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
565
566 /* We have to defer setting up vertex buffer since we need the buffer
567 * stride from the pipeline. */
568
569 assert(firstBinding + bindingCount <= MAX_VBS);
570 for (uint32_t i = 0; i < bindingCount; i++) {
571 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
572 vb[firstBinding + i].offset = pOffsets[i];
573 cmd_buffer->state.vb_dirty |= 1 << (firstBinding + i);
574 }
575 }
576
577 enum isl_format
578 anv_isl_format_for_descriptor_type(VkDescriptorType type)
579 {
580 switch (type) {
581 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
582 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
583 return ISL_FORMAT_R32G32B32A32_FLOAT;
584
585 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
586 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
587 return ISL_FORMAT_RAW;
588
589 default:
590 unreachable("Invalid descriptor type");
591 }
592 }
593
594 struct anv_state
595 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
596 const void *data, uint32_t size, uint32_t alignment)
597 {
598 struct anv_state state;
599
600 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
601 memcpy(state.map, data, size);
602
603 anv_state_flush(cmd_buffer->device, state);
604
605 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
606
607 return state;
608 }
609
610 struct anv_state
611 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
612 uint32_t *a, uint32_t *b,
613 uint32_t dwords, uint32_t alignment)
614 {
615 struct anv_state state;
616 uint32_t *p;
617
618 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
619 dwords * 4, alignment);
620 p = state.map;
621 for (uint32_t i = 0; i < dwords; i++)
622 p[i] = a[i] | b[i];
623
624 anv_state_flush(cmd_buffer->device, state);
625
626 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
627
628 return state;
629 }
630
631 static uint32_t
632 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
633 {
634 if (BRW_PARAM_IS_BUILTIN(param)) {
635 switch (param) {
636 case BRW_PARAM_BUILTIN_ZERO:
637 return 0;
638 default:
639 unreachable("Invalid param builtin");
640 }
641 } else {
642 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
643 assert(offset % sizeof(uint32_t) == 0);
644 if (offset < data->size)
645 return *(uint32_t *)((uint8_t *)data + offset);
646 else
647 return 0;
648 }
649 }
650
651 struct anv_state
652 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
653 gl_shader_stage stage)
654 {
655 /* If we don't have this stage, bail. */
656 if (!anv_pipeline_has_stage(cmd_buffer->state.pipeline, stage))
657 return (struct anv_state) { .offset = 0 };
658
659 struct anv_push_constants *data =
660 cmd_buffer->state.push_constants[stage];
661 const struct brw_stage_prog_data *prog_data =
662 cmd_buffer->state.pipeline->shaders[stage]->prog_data;
663
664 /* If we don't actually have any push constants, bail. */
665 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
666 return (struct anv_state) { .offset = 0 };
667
668 struct anv_state state =
669 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
670 prog_data->nr_params * sizeof(float),
671 32 /* bottom 5 bits MBZ */);
672
673 /* Walk through the param array and fill the buffer with data */
674 uint32_t *u32_map = state.map;
675 for (unsigned i = 0; i < prog_data->nr_params; i++)
676 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
677
678 anv_state_flush(cmd_buffer->device, state);
679
680 return state;
681 }
682
683 struct anv_state
684 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
685 {
686 struct anv_push_constants *data =
687 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
688 struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
689 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
690 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
691
692 /* If we don't actually have any push constants, bail. */
693 if (cs_prog_data->push.total.size == 0)
694 return (struct anv_state) { .offset = 0 };
695
696 const unsigned push_constant_alignment =
697 cmd_buffer->device->info.gen < 8 ? 32 : 64;
698 const unsigned aligned_total_push_constants_size =
699 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
700 struct anv_state state =
701 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
702 aligned_total_push_constants_size,
703 push_constant_alignment);
704
705 /* Walk through the param array and fill the buffer with data */
706 uint32_t *u32_map = state.map;
707
708 if (cs_prog_data->push.cross_thread.size > 0) {
709 for (unsigned i = 0;
710 i < cs_prog_data->push.cross_thread.dwords;
711 i++) {
712 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
713 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
714 }
715 }
716
717 if (cs_prog_data->push.per_thread.size > 0) {
718 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
719 unsigned dst =
720 8 * (cs_prog_data->push.per_thread.regs * t +
721 cs_prog_data->push.cross_thread.regs);
722 unsigned src = cs_prog_data->push.cross_thread.dwords;
723 for ( ; src < prog_data->nr_params; src++, dst++) {
724 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
725 u32_map[dst] = t;
726 } else {
727 u32_map[dst] =
728 anv_push_constant_value(data, prog_data->param[src]);
729 }
730 }
731 }
732 }
733
734 anv_state_flush(cmd_buffer->device, state);
735
736 return state;
737 }
738
739 void anv_CmdPushConstants(
740 VkCommandBuffer commandBuffer,
741 VkPipelineLayout layout,
742 VkShaderStageFlags stageFlags,
743 uint32_t offset,
744 uint32_t size,
745 const void* pValues)
746 {
747 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
748
749 anv_foreach_stage(stage, stageFlags) {
750 VkResult result =
751 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
752 stage, client_data);
753 if (result != VK_SUCCESS)
754 return;
755
756 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
757 pValues, size);
758 }
759
760 cmd_buffer->state.push_constants_dirty |= stageFlags;
761 }
762
763 VkResult anv_CreateCommandPool(
764 VkDevice _device,
765 const VkCommandPoolCreateInfo* pCreateInfo,
766 const VkAllocationCallbacks* pAllocator,
767 VkCommandPool* pCmdPool)
768 {
769 ANV_FROM_HANDLE(anv_device, device, _device);
770 struct anv_cmd_pool *pool;
771
772 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
773 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
774 if (pool == NULL)
775 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
776
777 if (pAllocator)
778 pool->alloc = *pAllocator;
779 else
780 pool->alloc = device->alloc;
781
782 list_inithead(&pool->cmd_buffers);
783
784 *pCmdPool = anv_cmd_pool_to_handle(pool);
785
786 return VK_SUCCESS;
787 }
788
789 void anv_DestroyCommandPool(
790 VkDevice _device,
791 VkCommandPool commandPool,
792 const VkAllocationCallbacks* pAllocator)
793 {
794 ANV_FROM_HANDLE(anv_device, device, _device);
795 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
796
797 if (!pool)
798 return;
799
800 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
801 &pool->cmd_buffers, pool_link) {
802 anv_cmd_buffer_destroy(cmd_buffer);
803 }
804
805 vk_free2(&device->alloc, pAllocator, pool);
806 }
807
808 VkResult anv_ResetCommandPool(
809 VkDevice device,
810 VkCommandPool commandPool,
811 VkCommandPoolResetFlags flags)
812 {
813 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
814
815 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
816 &pool->cmd_buffers, pool_link) {
817 anv_cmd_buffer_reset(cmd_buffer);
818 }
819
820 return VK_SUCCESS;
821 }
822
823 void anv_TrimCommandPoolKHR(
824 VkDevice device,
825 VkCommandPool commandPool,
826 VkCommandPoolTrimFlagsKHR flags)
827 {
828 /* Nothing for us to do here. Our pools stay pretty tidy. */
829 }
830
831 /**
832 * Return NULL if the current subpass has no depthstencil attachment.
833 */
834 const struct anv_image_view *
835 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
836 {
837 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
838 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
839
840 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
841 return NULL;
842
843 const struct anv_image_view *iview =
844 fb->attachments[subpass->depth_stencil_attachment.attachment];
845
846 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
847 VK_IMAGE_ASPECT_STENCIL_BIT));
848
849 return iview;
850 }
851
852 static VkResult
853 anv_cmd_buffer_ensure_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
854 uint32_t set)
855 {
856 struct anv_push_descriptor_set **push_set =
857 &cmd_buffer->state.push_descriptors[set];
858
859 if (*push_set == NULL) {
860 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
861 sizeof(struct anv_push_descriptor_set), 8,
862 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
863 if (*push_set == NULL) {
864 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
865 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
866 }
867 }
868
869 return VK_SUCCESS;
870 }
871
872 void anv_CmdPushDescriptorSetKHR(
873 VkCommandBuffer commandBuffer,
874 VkPipelineBindPoint pipelineBindPoint,
875 VkPipelineLayout _layout,
876 uint32_t _set,
877 uint32_t descriptorWriteCount,
878 const VkWriteDescriptorSet* pDescriptorWrites)
879 {
880 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
881 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
882
883 assert(pipelineBindPoint == VK_PIPELINE_BIND_POINT_GRAPHICS ||
884 pipelineBindPoint == VK_PIPELINE_BIND_POINT_COMPUTE);
885 assert(_set < MAX_SETS);
886
887 const struct anv_descriptor_set_layout *set_layout =
888 layout->set[_set].layout;
889
890 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
891 return;
892 struct anv_push_descriptor_set *push_set =
893 cmd_buffer->state.push_descriptors[_set];
894 struct anv_descriptor_set *set = &push_set->set;
895
896 set->layout = set_layout;
897 set->size = anv_descriptor_set_layout_size(set_layout);
898 set->buffer_count = set_layout->buffer_count;
899 set->buffer_views = push_set->buffer_views;
900
901 /* Go through the user supplied descriptors. */
902 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
903 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
904
905 switch (write->descriptorType) {
906 case VK_DESCRIPTOR_TYPE_SAMPLER:
907 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
908 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
909 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
910 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
911 for (uint32_t j = 0; j < write->descriptorCount; j++) {
912 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
913 write->pImageInfo + j,
914 write->descriptorType,
915 write->dstBinding,
916 write->dstArrayElement + j);
917 }
918 break;
919
920 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
921 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
922 for (uint32_t j = 0; j < write->descriptorCount; j++) {
923 ANV_FROM_HANDLE(anv_buffer_view, bview,
924 write->pTexelBufferView[j]);
925
926 anv_descriptor_set_write_buffer_view(set,
927 write->descriptorType,
928 bview,
929 write->dstBinding,
930 write->dstArrayElement + j);
931 }
932 break;
933
934 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
935 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
936 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
937 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
938 for (uint32_t j = 0; j < write->descriptorCount; j++) {
939 assert(write->pBufferInfo[j].buffer);
940 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
941 assert(buffer);
942
943 anv_descriptor_set_write_buffer(set,
944 cmd_buffer->device,
945 &cmd_buffer->surface_state_stream,
946 write->descriptorType,
947 buffer,
948 write->dstBinding,
949 write->dstArrayElement + j,
950 write->pBufferInfo[j].offset,
951 write->pBufferInfo[j].range);
952 }
953 break;
954
955 default:
956 break;
957 }
958 }
959
960 cmd_buffer->state.descriptors[_set] = set;
961 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
962 }
963
964 void anv_CmdPushDescriptorSetWithTemplateKHR(
965 VkCommandBuffer commandBuffer,
966 VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate,
967 VkPipelineLayout _layout,
968 uint32_t _set,
969 const void* pData)
970 {
971 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
972 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
973 descriptorUpdateTemplate);
974 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
975
976 assert(_set < MAX_PUSH_DESCRIPTORS);
977
978 const struct anv_descriptor_set_layout *set_layout =
979 layout->set[_set].layout;
980
981 if (anv_cmd_buffer_ensure_push_descriptor_set(cmd_buffer, _set) != VK_SUCCESS)
982 return;
983 struct anv_push_descriptor_set *push_set =
984 cmd_buffer->state.push_descriptors[_set];
985 struct anv_descriptor_set *set = &push_set->set;
986
987 set->layout = set_layout;
988 set->size = anv_descriptor_set_layout_size(set_layout);
989 set->buffer_count = set_layout->buffer_count;
990 set->buffer_views = push_set->buffer_views;
991
992 anv_descriptor_set_write_template(set,
993 cmd_buffer->device,
994 &cmd_buffer->surface_state_stream,
995 template,
996 pData);
997
998 cmd_buffer->state.descriptors[_set] = set;
999 cmd_buffer->state.descriptors_dirty |= set_layout->shader_stages;
1000 }