anv: Trivially implement VK_KHR_device_group
[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33
34 /** \file anv_cmd_buffer.c
35 *
36 * This file contains all of the stuff for emitting commands into a command
37 * buffer. This includes implementations of most of the vkCmd*
38 * entrypoints. This file is concerned entirely with state emission and
39 * not with the command buffer data structure itself. As far as this file
40 * is concerned, most of anv_cmd_buffer is magic.
41 */
42
43 /* TODO: These are taken from GLES. We should check the Vulkan spec */
44 const struct anv_dynamic_state default_dynamic_state = {
45 .viewport = {
46 .count = 0,
47 },
48 .scissor = {
49 .count = 0,
50 },
51 .line_width = 1.0f,
52 .depth_bias = {
53 .bias = 0.0f,
54 .clamp = 0.0f,
55 .slope = 0.0f,
56 },
57 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
58 .depth_bounds = {
59 .min = 0.0f,
60 .max = 1.0f,
61 },
62 .stencil_compare_mask = {
63 .front = ~0u,
64 .back = ~0u,
65 },
66 .stencil_write_mask = {
67 .front = ~0u,
68 .back = ~0u,
69 },
70 .stencil_reference = {
71 .front = 0u,
72 .back = 0u,
73 },
74 };
75
76 void
77 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
78 const struct anv_dynamic_state *src,
79 uint32_t copy_mask)
80 {
81 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
82 dest->viewport.count = src->viewport.count;
83 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
84 src->viewport.count);
85 }
86
87 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
88 dest->scissor.count = src->scissor.count;
89 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
90 src->scissor.count);
91 }
92
93 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
94 dest->line_width = src->line_width;
95
96 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
97 dest->depth_bias = src->depth_bias;
98
99 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
100 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
101
102 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
103 dest->depth_bounds = src->depth_bounds;
104
105 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
106 dest->stencil_compare_mask = src->stencil_compare_mask;
107
108 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
109 dest->stencil_write_mask = src->stencil_write_mask;
110
111 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
112 dest->stencil_reference = src->stencil_reference;
113 }
114
115 static void
116 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
117 {
118 struct anv_cmd_state *state = &cmd_buffer->state;
119
120 memset(state, 0, sizeof(*state));
121
122 state->current_pipeline = UINT32_MAX;
123 state->restart_index = UINT32_MAX;
124 state->gfx.dynamic = default_dynamic_state;
125 }
126
127 static void
128 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
129 struct anv_cmd_pipeline_state *pipe_state)
130 {
131 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++)
132 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
133 }
134
135 static void
136 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
137 {
138 struct anv_cmd_state *state = &cmd_buffer->state;
139
140 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
141 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
142
143 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
144 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
145
146 vk_free(&cmd_buffer->pool->alloc, state->attachments);
147 }
148
149 static void
150 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
151 {
152 anv_cmd_state_finish(cmd_buffer);
153 anv_cmd_state_init(cmd_buffer);
154 }
155
156 VkResult
157 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
158 gl_shader_stage stage, uint32_t size)
159 {
160 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
161
162 if (*ptr == NULL) {
163 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
164 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
165 if (*ptr == NULL) {
166 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
167 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
168 }
169 } else if ((*ptr)->size < size) {
170 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
172 if (*ptr == NULL) {
173 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
175 }
176 }
177 (*ptr)->size = size;
178
179 return VK_SUCCESS;
180 }
181
182 static VkResult anv_create_cmd_buffer(
183 struct anv_device * device,
184 struct anv_cmd_pool * pool,
185 VkCommandBufferLevel level,
186 VkCommandBuffer* pCommandBuffer)
187 {
188 struct anv_cmd_buffer *cmd_buffer;
189 VkResult result;
190
191 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (cmd_buffer == NULL)
194 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
195
196 cmd_buffer->batch.status = VK_SUCCESS;
197
198 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
199 cmd_buffer->device = device;
200 cmd_buffer->pool = pool;
201 cmd_buffer->level = level;
202
203 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
204 if (result != VK_SUCCESS)
205 goto fail;
206
207 anv_state_stream_init(&cmd_buffer->surface_state_stream,
208 &device->surface_state_pool, 4096);
209 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
210 &device->dynamic_state_pool, 16384);
211
212 anv_cmd_state_init(cmd_buffer);
213
214 if (pool) {
215 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
216 } else {
217 /* Init the pool_link so we can safefly call list_del when we destroy
218 * the command buffer
219 */
220 list_inithead(&cmd_buffer->pool_link);
221 }
222
223 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
224
225 return VK_SUCCESS;
226
227 fail:
228 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
229
230 return result;
231 }
232
233 VkResult anv_AllocateCommandBuffers(
234 VkDevice _device,
235 const VkCommandBufferAllocateInfo* pAllocateInfo,
236 VkCommandBuffer* pCommandBuffers)
237 {
238 ANV_FROM_HANDLE(anv_device, device, _device);
239 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
240
241 VkResult result = VK_SUCCESS;
242 uint32_t i;
243
244 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
245 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
246 &pCommandBuffers[i]);
247 if (result != VK_SUCCESS)
248 break;
249 }
250
251 if (result != VK_SUCCESS) {
252 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
253 i, pCommandBuffers);
254 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
255 pCommandBuffers[i] = VK_NULL_HANDLE;
256 }
257
258 return result;
259 }
260
261 static void
262 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
263 {
264 list_del(&cmd_buffer->pool_link);
265
266 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
267
268 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
269 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
270
271 anv_cmd_state_finish(cmd_buffer);
272
273 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
274 }
275
276 void anv_FreeCommandBuffers(
277 VkDevice device,
278 VkCommandPool commandPool,
279 uint32_t commandBufferCount,
280 const VkCommandBuffer* pCommandBuffers)
281 {
282 for (uint32_t i = 0; i < commandBufferCount; i++) {
283 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
284
285 if (!cmd_buffer)
286 continue;
287
288 anv_cmd_buffer_destroy(cmd_buffer);
289 }
290 }
291
292 VkResult
293 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
294 {
295 cmd_buffer->usage_flags = 0;
296 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
297 anv_cmd_state_reset(cmd_buffer);
298
299 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
300 anv_state_stream_init(&cmd_buffer->surface_state_stream,
301 &cmd_buffer->device->surface_state_pool, 4096);
302
303 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
304 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
305 &cmd_buffer->device->dynamic_state_pool, 16384);
306 return VK_SUCCESS;
307 }
308
309 VkResult anv_ResetCommandBuffer(
310 VkCommandBuffer commandBuffer,
311 VkCommandBufferResetFlags flags)
312 {
313 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
314 return anv_cmd_buffer_reset(cmd_buffer);
315 }
316
317 #define anv_genX_call(devinfo, func, ...) \
318 switch ((devinfo)->gen) { \
319 case 7: \
320 if ((devinfo)->is_haswell) { \
321 gen75_##func(__VA_ARGS__); \
322 } else { \
323 gen7_##func(__VA_ARGS__); \
324 } \
325 break; \
326 case 8: \
327 gen8_##func(__VA_ARGS__); \
328 break; \
329 case 9: \
330 gen9_##func(__VA_ARGS__); \
331 break; \
332 case 10: \
333 gen10_##func(__VA_ARGS__); \
334 break; \
335 default: \
336 assert(!"Unknown hardware generation"); \
337 }
338
339 void
340 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
341 {
342 anv_genX_call(&cmd_buffer->device->info,
343 cmd_buffer_emit_state_base_address,
344 cmd_buffer);
345 }
346
347 void
348 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
349 const struct anv_image *image,
350 VkImageAspectFlagBits aspect,
351 enum isl_aux_usage aux_usage,
352 uint32_t level,
353 uint32_t base_layer,
354 uint32_t layer_count)
355 {
356 anv_genX_call(&cmd_buffer->device->info,
357 cmd_buffer_mark_image_written,
358 cmd_buffer, image, aspect, aux_usage,
359 level, base_layer, layer_count);
360 }
361
362 void anv_CmdBindPipeline(
363 VkCommandBuffer commandBuffer,
364 VkPipelineBindPoint pipelineBindPoint,
365 VkPipeline _pipeline)
366 {
367 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
368 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
369
370 switch (pipelineBindPoint) {
371 case VK_PIPELINE_BIND_POINT_COMPUTE:
372 cmd_buffer->state.compute.base.pipeline = pipeline;
373 cmd_buffer->state.compute.pipeline_dirty = true;
374 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
375 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
376 break;
377
378 case VK_PIPELINE_BIND_POINT_GRAPHICS:
379 cmd_buffer->state.gfx.base.pipeline = pipeline;
380 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
381 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
382 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
383 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
384
385 /* Apply the dynamic state from the pipeline */
386 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
387 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
388 &pipeline->dynamic_state,
389 pipeline->dynamic_state_mask);
390 break;
391
392 default:
393 assert(!"invalid bind point");
394 break;
395 }
396 }
397
398 void anv_CmdSetViewport(
399 VkCommandBuffer commandBuffer,
400 uint32_t firstViewport,
401 uint32_t viewportCount,
402 const VkViewport* pViewports)
403 {
404 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
405
406 const uint32_t total_count = firstViewport + viewportCount;
407 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
408 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
409
410 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
411 pViewports, viewportCount * sizeof(*pViewports));
412
413 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
414 }
415
416 void anv_CmdSetScissor(
417 VkCommandBuffer commandBuffer,
418 uint32_t firstScissor,
419 uint32_t scissorCount,
420 const VkRect2D* pScissors)
421 {
422 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
423
424 const uint32_t total_count = firstScissor + scissorCount;
425 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
426 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
427
428 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
429 pScissors, scissorCount * sizeof(*pScissors));
430
431 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
432 }
433
434 void anv_CmdSetLineWidth(
435 VkCommandBuffer commandBuffer,
436 float lineWidth)
437 {
438 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
439
440 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
441 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
442 }
443
444 void anv_CmdSetDepthBias(
445 VkCommandBuffer commandBuffer,
446 float depthBiasConstantFactor,
447 float depthBiasClamp,
448 float depthBiasSlopeFactor)
449 {
450 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
451
452 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
453 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
454 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
455
456 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
457 }
458
459 void anv_CmdSetBlendConstants(
460 VkCommandBuffer commandBuffer,
461 const float blendConstants[4])
462 {
463 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
464
465 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
466 blendConstants, sizeof(float) * 4);
467
468 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
469 }
470
471 void anv_CmdSetDepthBounds(
472 VkCommandBuffer commandBuffer,
473 float minDepthBounds,
474 float maxDepthBounds)
475 {
476 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
477
478 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
479 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
480
481 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
482 }
483
484 void anv_CmdSetStencilCompareMask(
485 VkCommandBuffer commandBuffer,
486 VkStencilFaceFlags faceMask,
487 uint32_t compareMask)
488 {
489 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
490
491 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
492 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
493 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
494 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
495
496 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
497 }
498
499 void anv_CmdSetStencilWriteMask(
500 VkCommandBuffer commandBuffer,
501 VkStencilFaceFlags faceMask,
502 uint32_t writeMask)
503 {
504 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
505
506 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
507 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
508 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
509 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
510
511 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
512 }
513
514 void anv_CmdSetStencilReference(
515 VkCommandBuffer commandBuffer,
516 VkStencilFaceFlags faceMask,
517 uint32_t reference)
518 {
519 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
520
521 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
522 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
523 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
524 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
525
526 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
527 }
528
529 static void
530 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
531 VkPipelineBindPoint bind_point,
532 struct anv_pipeline_layout *layout,
533 uint32_t set_index,
534 struct anv_descriptor_set *set,
535 uint32_t *dynamic_offset_count,
536 const uint32_t **dynamic_offsets)
537 {
538 struct anv_descriptor_set_layout *set_layout =
539 layout->set[set_index].layout;
540
541 struct anv_cmd_pipeline_state *pipe_state;
542 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
543 pipe_state = &cmd_buffer->state.compute.base;
544 } else {
545 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
546 pipe_state = &cmd_buffer->state.gfx.base;
547 }
548 pipe_state->descriptors[set_index] = set;
549
550 if (dynamic_offsets) {
551 if (set_layout->dynamic_offset_count > 0) {
552 uint32_t dynamic_offset_start =
553 layout->set[set_index].dynamic_offset_start;
554
555 /* Assert that everything is in range */
556 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
557 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
558 ARRAY_SIZE(pipe_state->dynamic_offsets));
559
560 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
561 *dynamic_offsets, set_layout->dynamic_offset_count);
562
563 *dynamic_offsets += set_layout->dynamic_offset_count;
564 *dynamic_offset_count -= set_layout->dynamic_offset_count;
565 }
566 }
567
568 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
569 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
570 } else {
571 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
572 cmd_buffer->state.descriptors_dirty |=
573 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
574 }
575
576 /* Pipeline layout objects are required to live at least while any command
577 * buffers that use them are in recording state. We need to grab a reference
578 * to the pipeline layout being bound here so we can compute correct dynamic
579 * offsets for VK_DESCRIPTOR_TYPE_*_DYNAMIC in dynamic_offset_for_binding()
580 * when we record draw commands that come after this.
581 */
582 pipe_state->layout = layout;
583 }
584
585 void anv_CmdBindDescriptorSets(
586 VkCommandBuffer commandBuffer,
587 VkPipelineBindPoint pipelineBindPoint,
588 VkPipelineLayout _layout,
589 uint32_t firstSet,
590 uint32_t descriptorSetCount,
591 const VkDescriptorSet* pDescriptorSets,
592 uint32_t dynamicOffsetCount,
593 const uint32_t* pDynamicOffsets)
594 {
595 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
596 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
597
598 assert(firstSet + descriptorSetCount < MAX_SETS);
599
600 for (uint32_t i = 0; i < descriptorSetCount; i++) {
601 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
602 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
603 layout, firstSet + i, set,
604 &dynamicOffsetCount,
605 &pDynamicOffsets);
606 }
607 }
608
609 void anv_CmdBindVertexBuffers(
610 VkCommandBuffer commandBuffer,
611 uint32_t firstBinding,
612 uint32_t bindingCount,
613 const VkBuffer* pBuffers,
614 const VkDeviceSize* pOffsets)
615 {
616 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
617 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
618
619 /* We have to defer setting up vertex buffer since we need the buffer
620 * stride from the pipeline. */
621
622 assert(firstBinding + bindingCount <= MAX_VBS);
623 for (uint32_t i = 0; i < bindingCount; i++) {
624 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
625 vb[firstBinding + i].offset = pOffsets[i];
626 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
627 }
628 }
629
630 enum isl_format
631 anv_isl_format_for_descriptor_type(VkDescriptorType type)
632 {
633 switch (type) {
634 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
635 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
636 return ISL_FORMAT_R32G32B32A32_FLOAT;
637
638 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
639 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
640 return ISL_FORMAT_RAW;
641
642 default:
643 unreachable("Invalid descriptor type");
644 }
645 }
646
647 struct anv_state
648 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
649 const void *data, uint32_t size, uint32_t alignment)
650 {
651 struct anv_state state;
652
653 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
654 memcpy(state.map, data, size);
655
656 anv_state_flush(cmd_buffer->device, state);
657
658 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
659
660 return state;
661 }
662
663 struct anv_state
664 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
665 uint32_t *a, uint32_t *b,
666 uint32_t dwords, uint32_t alignment)
667 {
668 struct anv_state state;
669 uint32_t *p;
670
671 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
672 dwords * 4, alignment);
673 p = state.map;
674 for (uint32_t i = 0; i < dwords; i++)
675 p[i] = a[i] | b[i];
676
677 anv_state_flush(cmd_buffer->device, state);
678
679 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
680
681 return state;
682 }
683
684 static uint32_t
685 anv_push_constant_value(struct anv_push_constants *data, uint32_t param)
686 {
687 if (BRW_PARAM_IS_BUILTIN(param)) {
688 switch (param) {
689 case BRW_PARAM_BUILTIN_ZERO:
690 return 0;
691 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
692 return data->base_work_group_id[0];
693 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
694 return data->base_work_group_id[1];
695 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
696 return data->base_work_group_id[2];
697 default:
698 unreachable("Invalid param builtin");
699 }
700 } else {
701 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
702 assert(offset % sizeof(uint32_t) == 0);
703 if (offset < data->size)
704 return *(uint32_t *)((uint8_t *)data + offset);
705 else
706 return 0;
707 }
708 }
709
710 struct anv_state
711 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
712 gl_shader_stage stage)
713 {
714 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
715
716 /* If we don't have this stage, bail. */
717 if (!anv_pipeline_has_stage(pipeline, stage))
718 return (struct anv_state) { .offset = 0 };
719
720 struct anv_push_constants *data =
721 cmd_buffer->state.push_constants[stage];
722 const struct brw_stage_prog_data *prog_data =
723 pipeline->shaders[stage]->prog_data;
724
725 /* If we don't actually have any push constants, bail. */
726 if (data == NULL || prog_data == NULL || prog_data->nr_params == 0)
727 return (struct anv_state) { .offset = 0 };
728
729 struct anv_state state =
730 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
731 prog_data->nr_params * sizeof(float),
732 32 /* bottom 5 bits MBZ */);
733
734 /* Walk through the param array and fill the buffer with data */
735 uint32_t *u32_map = state.map;
736 for (unsigned i = 0; i < prog_data->nr_params; i++)
737 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
738
739 anv_state_flush(cmd_buffer->device, state);
740
741 return state;
742 }
743
744 struct anv_state
745 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
746 {
747 struct anv_push_constants *data =
748 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
749 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
750 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
751 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
752
753 /* If we don't actually have any push constants, bail. */
754 if (cs_prog_data->push.total.size == 0)
755 return (struct anv_state) { .offset = 0 };
756
757 const unsigned push_constant_alignment =
758 cmd_buffer->device->info.gen < 8 ? 32 : 64;
759 const unsigned aligned_total_push_constants_size =
760 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
761 struct anv_state state =
762 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
763 aligned_total_push_constants_size,
764 push_constant_alignment);
765
766 /* Walk through the param array and fill the buffer with data */
767 uint32_t *u32_map = state.map;
768
769 if (cs_prog_data->push.cross_thread.size > 0) {
770 for (unsigned i = 0;
771 i < cs_prog_data->push.cross_thread.dwords;
772 i++) {
773 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
774 u32_map[i] = anv_push_constant_value(data, prog_data->param[i]);
775 }
776 }
777
778 if (cs_prog_data->push.per_thread.size > 0) {
779 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
780 unsigned dst =
781 8 * (cs_prog_data->push.per_thread.regs * t +
782 cs_prog_data->push.cross_thread.regs);
783 unsigned src = cs_prog_data->push.cross_thread.dwords;
784 for ( ; src < prog_data->nr_params; src++, dst++) {
785 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
786 u32_map[dst] = t;
787 } else {
788 u32_map[dst] =
789 anv_push_constant_value(data, prog_data->param[src]);
790 }
791 }
792 }
793 }
794
795 anv_state_flush(cmd_buffer->device, state);
796
797 return state;
798 }
799
800 void anv_CmdPushConstants(
801 VkCommandBuffer commandBuffer,
802 VkPipelineLayout layout,
803 VkShaderStageFlags stageFlags,
804 uint32_t offset,
805 uint32_t size,
806 const void* pValues)
807 {
808 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
809
810 anv_foreach_stage(stage, stageFlags) {
811 VkResult result =
812 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
813 stage, client_data);
814 if (result != VK_SUCCESS)
815 return;
816
817 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
818 pValues, size);
819 }
820
821 cmd_buffer->state.push_constants_dirty |= stageFlags;
822 }
823
824 VkResult anv_CreateCommandPool(
825 VkDevice _device,
826 const VkCommandPoolCreateInfo* pCreateInfo,
827 const VkAllocationCallbacks* pAllocator,
828 VkCommandPool* pCmdPool)
829 {
830 ANV_FROM_HANDLE(anv_device, device, _device);
831 struct anv_cmd_pool *pool;
832
833 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
834 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
835 if (pool == NULL)
836 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
837
838 if (pAllocator)
839 pool->alloc = *pAllocator;
840 else
841 pool->alloc = device->alloc;
842
843 list_inithead(&pool->cmd_buffers);
844
845 *pCmdPool = anv_cmd_pool_to_handle(pool);
846
847 return VK_SUCCESS;
848 }
849
850 void anv_DestroyCommandPool(
851 VkDevice _device,
852 VkCommandPool commandPool,
853 const VkAllocationCallbacks* pAllocator)
854 {
855 ANV_FROM_HANDLE(anv_device, device, _device);
856 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
857
858 if (!pool)
859 return;
860
861 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
862 &pool->cmd_buffers, pool_link) {
863 anv_cmd_buffer_destroy(cmd_buffer);
864 }
865
866 vk_free2(&device->alloc, pAllocator, pool);
867 }
868
869 VkResult anv_ResetCommandPool(
870 VkDevice device,
871 VkCommandPool commandPool,
872 VkCommandPoolResetFlags flags)
873 {
874 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
875
876 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
877 &pool->cmd_buffers, pool_link) {
878 anv_cmd_buffer_reset(cmd_buffer);
879 }
880
881 return VK_SUCCESS;
882 }
883
884 void anv_TrimCommandPool(
885 VkDevice device,
886 VkCommandPool commandPool,
887 VkCommandPoolTrimFlags flags)
888 {
889 /* Nothing for us to do here. Our pools stay pretty tidy. */
890 }
891
892 /**
893 * Return NULL if the current subpass has no depthstencil attachment.
894 */
895 const struct anv_image_view *
896 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
897 {
898 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
899 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
900
901 if (subpass->depth_stencil_attachment.attachment == VK_ATTACHMENT_UNUSED)
902 return NULL;
903
904 const struct anv_image_view *iview =
905 fb->attachments[subpass->depth_stencil_attachment.attachment];
906
907 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
908 VK_IMAGE_ASPECT_STENCIL_BIT));
909
910 return iview;
911 }
912
913 static struct anv_push_descriptor_set *
914 anv_cmd_buffer_get_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
915 VkPipelineBindPoint bind_point,
916 uint32_t set)
917 {
918 struct anv_cmd_pipeline_state *pipe_state;
919 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
920 pipe_state = &cmd_buffer->state.compute.base;
921 } else {
922 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
923 pipe_state = &cmd_buffer->state.gfx.base;
924 }
925
926 struct anv_push_descriptor_set **push_set =
927 &pipe_state->push_descriptors[set];
928
929 if (*push_set == NULL) {
930 *push_set = vk_alloc(&cmd_buffer->pool->alloc,
931 sizeof(struct anv_push_descriptor_set), 8,
932 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
933 if (*push_set == NULL) {
934 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
935 return NULL;
936 }
937 }
938
939 return *push_set;
940 }
941
942 void anv_CmdPushDescriptorSetKHR(
943 VkCommandBuffer commandBuffer,
944 VkPipelineBindPoint pipelineBindPoint,
945 VkPipelineLayout _layout,
946 uint32_t _set,
947 uint32_t descriptorWriteCount,
948 const VkWriteDescriptorSet* pDescriptorWrites)
949 {
950 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
951 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
952
953 assert(_set < MAX_SETS);
954
955 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
956
957 struct anv_push_descriptor_set *push_set =
958 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
959 pipelineBindPoint, _set);
960 if (!push_set)
961 return;
962
963 struct anv_descriptor_set *set = &push_set->set;
964
965 set->layout = set_layout;
966 set->size = anv_descriptor_set_layout_size(set_layout);
967 set->buffer_count = set_layout->buffer_count;
968 set->buffer_views = push_set->buffer_views;
969
970 /* Go through the user supplied descriptors. */
971 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
972 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
973
974 switch (write->descriptorType) {
975 case VK_DESCRIPTOR_TYPE_SAMPLER:
976 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
977 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
978 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
979 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
980 for (uint32_t j = 0; j < write->descriptorCount; j++) {
981 anv_descriptor_set_write_image_view(set, &cmd_buffer->device->info,
982 write->pImageInfo + j,
983 write->descriptorType,
984 write->dstBinding,
985 write->dstArrayElement + j);
986 }
987 break;
988
989 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
990 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
991 for (uint32_t j = 0; j < write->descriptorCount; j++) {
992 ANV_FROM_HANDLE(anv_buffer_view, bview,
993 write->pTexelBufferView[j]);
994
995 anv_descriptor_set_write_buffer_view(set,
996 write->descriptorType,
997 bview,
998 write->dstBinding,
999 write->dstArrayElement + j);
1000 }
1001 break;
1002
1003 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1004 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1005 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1006 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1007 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1008 assert(write->pBufferInfo[j].buffer);
1009 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1010 assert(buffer);
1011
1012 anv_descriptor_set_write_buffer(set,
1013 cmd_buffer->device,
1014 &cmd_buffer->surface_state_stream,
1015 write->descriptorType,
1016 buffer,
1017 write->dstBinding,
1018 write->dstArrayElement + j,
1019 write->pBufferInfo[j].offset,
1020 write->pBufferInfo[j].range);
1021 }
1022 break;
1023
1024 default:
1025 break;
1026 }
1027 }
1028
1029 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1030 layout, _set, set, NULL, NULL);
1031 }
1032
1033 void anv_CmdPushDescriptorSetWithTemplateKHR(
1034 VkCommandBuffer commandBuffer,
1035 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1036 VkPipelineLayout _layout,
1037 uint32_t _set,
1038 const void* pData)
1039 {
1040 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1041 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1042 descriptorUpdateTemplate);
1043 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1044
1045 assert(_set < MAX_PUSH_DESCRIPTORS);
1046
1047 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1048
1049 struct anv_push_descriptor_set *push_set =
1050 anv_cmd_buffer_get_push_descriptor_set(cmd_buffer,
1051 template->bind_point, _set);
1052 if (!push_set)
1053 return;
1054
1055 struct anv_descriptor_set *set = &push_set->set;
1056
1057 set->layout = set_layout;
1058 set->size = anv_descriptor_set_layout_size(set_layout);
1059 set->buffer_count = set_layout->buffer_count;
1060 set->buffer_views = push_set->buffer_views;
1061
1062 anv_descriptor_set_write_template(set,
1063 cmd_buffer->device,
1064 &cmd_buffer->surface_state_stream,
1065 template,
1066 pData);
1067
1068 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1069 layout, _set, set, NULL, NULL);
1070 }
1071
1072 void anv_CmdSetDeviceMask(
1073 VkCommandBuffer commandBuffer,
1074 uint32_t deviceMask)
1075 {
1076 /* No-op */
1077 }