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anv: fix crash when application does not provide push constants
[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33 #include "vk_util.h"
34
35 /** \file anv_cmd_buffer.c
36 *
37 * This file contains all of the stuff for emitting commands into a command
38 * buffer. This includes implementations of most of the vkCmd*
39 * entrypoints. This file is concerned entirely with state emission and
40 * not with the command buffer data structure itself. As far as this file
41 * is concerned, most of anv_cmd_buffer is magic.
42 */
43
44 /* TODO: These are taken from GLES. We should check the Vulkan spec */
45 const struct anv_dynamic_state default_dynamic_state = {
46 .viewport = {
47 .count = 0,
48 },
49 .scissor = {
50 .count = 0,
51 },
52 .line_width = 1.0f,
53 .depth_bias = {
54 .bias = 0.0f,
55 .clamp = 0.0f,
56 .slope = 0.0f,
57 },
58 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
59 .depth_bounds = {
60 .min = 0.0f,
61 .max = 1.0f,
62 },
63 .stencil_compare_mask = {
64 .front = ~0u,
65 .back = ~0u,
66 },
67 .stencil_write_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_reference = {
72 .front = 0u,
73 .back = 0u,
74 },
75 };
76
77 void
78 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
79 const struct anv_dynamic_state *src,
80 uint32_t copy_mask)
81 {
82 if (copy_mask & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
83 dest->viewport.count = src->viewport.count;
84 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
85 src->viewport.count);
86 }
87
88 if (copy_mask & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
89 dest->scissor.count = src->scissor.count;
90 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
91 src->scissor.count);
92 }
93
94 if (copy_mask & (1 << VK_DYNAMIC_STATE_LINE_WIDTH))
95 dest->line_width = src->line_width;
96
97 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BIAS))
98 dest->depth_bias = src->depth_bias;
99
100 if (copy_mask & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
101 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
102
103 if (copy_mask & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS))
104 dest->depth_bounds = src->depth_bounds;
105
106 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK))
107 dest->stencil_compare_mask = src->stencil_compare_mask;
108
109 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_WRITE_MASK))
110 dest->stencil_write_mask = src->stencil_write_mask;
111
112 if (copy_mask & (1 << VK_DYNAMIC_STATE_STENCIL_REFERENCE))
113 dest->stencil_reference = src->stencil_reference;
114 }
115
116 static void
117 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
118 {
119 struct anv_cmd_state *state = &cmd_buffer->state;
120
121 memset(state, 0, sizeof(*state));
122
123 state->current_pipeline = UINT32_MAX;
124 state->restart_index = UINT32_MAX;
125 state->gfx.dynamic = default_dynamic_state;
126 }
127
128 static void
129 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
130 struct anv_cmd_pipeline_state *pipe_state)
131 {
132 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++) {
133 if (pipe_state->push_descriptors[i]) {
134 anv_descriptor_set_layout_unref(cmd_buffer->device,
135 pipe_state->push_descriptors[i]->set.layout);
136 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
137 }
138 }
139 }
140
141 static void
142 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
143 {
144 struct anv_cmd_state *state = &cmd_buffer->state;
145
146 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
147 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
148
149 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
150 vk_free(&cmd_buffer->pool->alloc, state->push_constants[i]);
151
152 vk_free(&cmd_buffer->pool->alloc, state->attachments);
153 }
154
155 static void
156 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
157 {
158 anv_cmd_state_finish(cmd_buffer);
159 anv_cmd_state_init(cmd_buffer);
160 }
161
162 /**
163 * This function updates the size of the push constant buffer we need to emit.
164 * This is called in various parts of the driver to ensure that different
165 * pieces of push constant data get emitted as needed. However, it is important
166 * that we never shrink the size of the buffer. For example, a compute shader
167 * dispatch will always call this for the base group id, which has an
168 * offset in the push constant buffer that is smaller than the offset for
169 * storage image data. If the compute shader has storage images, we will call
170 * this again with a larger size during binding table emission. However,
171 * if we dispatch the compute shader again without dirtying our descriptors,
172 * we would still call this function with a smaller size for the base group
173 * id, and not for the images, which would incorrectly shrink the size of the
174 * push constant data we emit with that dispatch, making us drop the image data.
175 */
176 VkResult
177 anv_cmd_buffer_ensure_push_constants_size(struct anv_cmd_buffer *cmd_buffer,
178 gl_shader_stage stage, uint32_t size)
179 {
180 struct anv_push_constants **ptr = &cmd_buffer->state.push_constants[stage];
181
182 if (*ptr == NULL) {
183 *ptr = vk_alloc(&cmd_buffer->pool->alloc, size, 8,
184 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
185 if (*ptr == NULL) {
186 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
187 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
188 }
189 (*ptr)->size = size;
190 } else if ((*ptr)->size < size) {
191 *ptr = vk_realloc(&cmd_buffer->pool->alloc, *ptr, size, 8,
192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
193 if (*ptr == NULL) {
194 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
195 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
196 }
197 (*ptr)->size = size;
198 }
199
200 return VK_SUCCESS;
201 }
202
203 static VkResult anv_create_cmd_buffer(
204 struct anv_device * device,
205 struct anv_cmd_pool * pool,
206 VkCommandBufferLevel level,
207 VkCommandBuffer* pCommandBuffer)
208 {
209 struct anv_cmd_buffer *cmd_buffer;
210 VkResult result;
211
212 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
213 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
214 if (cmd_buffer == NULL)
215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
216
217 cmd_buffer->batch.status = VK_SUCCESS;
218
219 cmd_buffer->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
220 cmd_buffer->device = device;
221 cmd_buffer->pool = pool;
222 cmd_buffer->level = level;
223
224 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
225 if (result != VK_SUCCESS)
226 goto fail;
227
228 anv_state_stream_init(&cmd_buffer->surface_state_stream,
229 &device->surface_state_pool, 4096);
230 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
231 &device->dynamic_state_pool, 16384);
232
233 anv_cmd_state_init(cmd_buffer);
234
235 if (pool) {
236 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
237 } else {
238 /* Init the pool_link so we can safefly call list_del when we destroy
239 * the command buffer
240 */
241 list_inithead(&cmd_buffer->pool_link);
242 }
243
244 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
245
246 return VK_SUCCESS;
247
248 fail:
249 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
250
251 return result;
252 }
253
254 VkResult anv_AllocateCommandBuffers(
255 VkDevice _device,
256 const VkCommandBufferAllocateInfo* pAllocateInfo,
257 VkCommandBuffer* pCommandBuffers)
258 {
259 ANV_FROM_HANDLE(anv_device, device, _device);
260 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
261
262 VkResult result = VK_SUCCESS;
263 uint32_t i;
264
265 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
266 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
267 &pCommandBuffers[i]);
268 if (result != VK_SUCCESS)
269 break;
270 }
271
272 if (result != VK_SUCCESS) {
273 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
274 i, pCommandBuffers);
275 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
276 pCommandBuffers[i] = VK_NULL_HANDLE;
277 }
278
279 return result;
280 }
281
282 static void
283 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
284 {
285 list_del(&cmd_buffer->pool_link);
286
287 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
288
289 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
290 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
291
292 anv_cmd_state_finish(cmd_buffer);
293
294 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
295 }
296
297 void anv_FreeCommandBuffers(
298 VkDevice device,
299 VkCommandPool commandPool,
300 uint32_t commandBufferCount,
301 const VkCommandBuffer* pCommandBuffers)
302 {
303 for (uint32_t i = 0; i < commandBufferCount; i++) {
304 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
305
306 if (!cmd_buffer)
307 continue;
308
309 anv_cmd_buffer_destroy(cmd_buffer);
310 }
311 }
312
313 VkResult
314 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
315 {
316 cmd_buffer->usage_flags = 0;
317 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
318 anv_cmd_state_reset(cmd_buffer);
319
320 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
321 anv_state_stream_init(&cmd_buffer->surface_state_stream,
322 &cmd_buffer->device->surface_state_pool, 4096);
323
324 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
325 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
326 &cmd_buffer->device->dynamic_state_pool, 16384);
327 return VK_SUCCESS;
328 }
329
330 VkResult anv_ResetCommandBuffer(
331 VkCommandBuffer commandBuffer,
332 VkCommandBufferResetFlags flags)
333 {
334 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
335 return anv_cmd_buffer_reset(cmd_buffer);
336 }
337
338 #define anv_genX_call(devinfo, func, ...) \
339 switch ((devinfo)->gen) { \
340 case 7: \
341 if ((devinfo)->is_haswell) { \
342 gen75_##func(__VA_ARGS__); \
343 } else { \
344 gen7_##func(__VA_ARGS__); \
345 } \
346 break; \
347 case 8: \
348 gen8_##func(__VA_ARGS__); \
349 break; \
350 case 9: \
351 gen9_##func(__VA_ARGS__); \
352 break; \
353 case 10: \
354 gen10_##func(__VA_ARGS__); \
355 break; \
356 case 11: \
357 gen11_##func(__VA_ARGS__); \
358 break; \
359 default: \
360 assert(!"Unknown hardware generation"); \
361 }
362
363 void
364 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
365 {
366 anv_genX_call(&cmd_buffer->device->info,
367 cmd_buffer_emit_state_base_address,
368 cmd_buffer);
369 }
370
371 void
372 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
373 const struct anv_image *image,
374 VkImageAspectFlagBits aspect,
375 enum isl_aux_usage aux_usage,
376 uint32_t level,
377 uint32_t base_layer,
378 uint32_t layer_count)
379 {
380 anv_genX_call(&cmd_buffer->device->info,
381 cmd_buffer_mark_image_written,
382 cmd_buffer, image, aspect, aux_usage,
383 level, base_layer, layer_count);
384 }
385
386 void
387 anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer)
388 {
389 anv_genX_call(&cmd_buffer->device->info,
390 cmd_emit_conditional_render_predicate,
391 cmd_buffer);
392 }
393
394 void anv_CmdBindPipeline(
395 VkCommandBuffer commandBuffer,
396 VkPipelineBindPoint pipelineBindPoint,
397 VkPipeline _pipeline)
398 {
399 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
400 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
401
402 switch (pipelineBindPoint) {
403 case VK_PIPELINE_BIND_POINT_COMPUTE:
404 cmd_buffer->state.compute.base.pipeline = pipeline;
405 cmd_buffer->state.compute.pipeline_dirty = true;
406 cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
407 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
408 break;
409
410 case VK_PIPELINE_BIND_POINT_GRAPHICS:
411 cmd_buffer->state.gfx.base.pipeline = pipeline;
412 cmd_buffer->state.gfx.vb_dirty |= pipeline->vb_used;
413 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
414 cmd_buffer->state.push_constants_dirty |= pipeline->active_stages;
415 cmd_buffer->state.descriptors_dirty |= pipeline->active_stages;
416
417 /* Apply the dynamic state from the pipeline */
418 cmd_buffer->state.gfx.dirty |= pipeline->dynamic_state_mask;
419 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
420 &pipeline->dynamic_state,
421 pipeline->dynamic_state_mask);
422 break;
423
424 default:
425 assert(!"invalid bind point");
426 break;
427 }
428 }
429
430 void anv_CmdSetViewport(
431 VkCommandBuffer commandBuffer,
432 uint32_t firstViewport,
433 uint32_t viewportCount,
434 const VkViewport* pViewports)
435 {
436 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
437
438 const uint32_t total_count = firstViewport + viewportCount;
439 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
440 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
441
442 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
443 pViewports, viewportCount * sizeof(*pViewports));
444
445 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
446 }
447
448 void anv_CmdSetScissor(
449 VkCommandBuffer commandBuffer,
450 uint32_t firstScissor,
451 uint32_t scissorCount,
452 const VkRect2D* pScissors)
453 {
454 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
455
456 const uint32_t total_count = firstScissor + scissorCount;
457 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
458 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
459
460 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
461 pScissors, scissorCount * sizeof(*pScissors));
462
463 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
464 }
465
466 void anv_CmdSetLineWidth(
467 VkCommandBuffer commandBuffer,
468 float lineWidth)
469 {
470 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
471
472 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
473 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
474 }
475
476 void anv_CmdSetDepthBias(
477 VkCommandBuffer commandBuffer,
478 float depthBiasConstantFactor,
479 float depthBiasClamp,
480 float depthBiasSlopeFactor)
481 {
482 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
483
484 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
485 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
486 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
487
488 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
489 }
490
491 void anv_CmdSetBlendConstants(
492 VkCommandBuffer commandBuffer,
493 const float blendConstants[4])
494 {
495 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
496
497 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
498 blendConstants, sizeof(float) * 4);
499
500 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
501 }
502
503 void anv_CmdSetDepthBounds(
504 VkCommandBuffer commandBuffer,
505 float minDepthBounds,
506 float maxDepthBounds)
507 {
508 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
509
510 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
511 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
512
513 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
514 }
515
516 void anv_CmdSetStencilCompareMask(
517 VkCommandBuffer commandBuffer,
518 VkStencilFaceFlags faceMask,
519 uint32_t compareMask)
520 {
521 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
522
523 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
524 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
525 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
526 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
527
528 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
529 }
530
531 void anv_CmdSetStencilWriteMask(
532 VkCommandBuffer commandBuffer,
533 VkStencilFaceFlags faceMask,
534 uint32_t writeMask)
535 {
536 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
537
538 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
539 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
540 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
541 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
542
543 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
544 }
545
546 void anv_CmdSetStencilReference(
547 VkCommandBuffer commandBuffer,
548 VkStencilFaceFlags faceMask,
549 uint32_t reference)
550 {
551 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
552
553 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
554 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
555 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
556 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
557
558 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
559 }
560
561 static void
562 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
563 VkPipelineBindPoint bind_point,
564 struct anv_pipeline_layout *layout,
565 uint32_t set_index,
566 struct anv_descriptor_set *set,
567 uint32_t *dynamic_offset_count,
568 const uint32_t **dynamic_offsets)
569 {
570 struct anv_descriptor_set_layout *set_layout =
571 layout->set[set_index].layout;
572
573 struct anv_cmd_pipeline_state *pipe_state;
574 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
575 pipe_state = &cmd_buffer->state.compute.base;
576 } else {
577 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
578 pipe_state = &cmd_buffer->state.gfx.base;
579 }
580 pipe_state->descriptors[set_index] = set;
581
582 if (dynamic_offsets) {
583 if (set_layout->dynamic_offset_count > 0) {
584 uint32_t dynamic_offset_start =
585 layout->set[set_index].dynamic_offset_start;
586
587 /* Assert that everything is in range */
588 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
589 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
590 ARRAY_SIZE(pipe_state->dynamic_offsets));
591
592 typed_memcpy(&pipe_state->dynamic_offsets[dynamic_offset_start],
593 *dynamic_offsets, set_layout->dynamic_offset_count);
594
595 *dynamic_offsets += set_layout->dynamic_offset_count;
596 *dynamic_offset_count -= set_layout->dynamic_offset_count;
597
598 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
599 cmd_buffer->state.push_constants_dirty |=
600 VK_SHADER_STAGE_COMPUTE_BIT;
601 } else {
602 cmd_buffer->state.push_constants_dirty |=
603 VK_SHADER_STAGE_ALL_GRAPHICS;
604 }
605 }
606 }
607
608 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
609 cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_COMPUTE_BIT;
610 } else {
611 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
612 cmd_buffer->state.descriptors_dirty |=
613 set_layout->shader_stages & VK_SHADER_STAGE_ALL_GRAPHICS;
614 }
615
616 /* Pipeline layout objects are required to live at least while any command
617 * buffers that use them are in recording state. We need to grab a reference
618 * to the pipeline layout being bound here so we can compute correct dynamic
619 * offsets for VK_DESCRIPTOR_TYPE_*_DYNAMIC in dynamic_offset_for_binding()
620 * when we record draw commands that come after this.
621 */
622 pipe_state->layout = layout;
623 }
624
625 void anv_CmdBindDescriptorSets(
626 VkCommandBuffer commandBuffer,
627 VkPipelineBindPoint pipelineBindPoint,
628 VkPipelineLayout _layout,
629 uint32_t firstSet,
630 uint32_t descriptorSetCount,
631 const VkDescriptorSet* pDescriptorSets,
632 uint32_t dynamicOffsetCount,
633 const uint32_t* pDynamicOffsets)
634 {
635 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
636 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
637
638 assert(firstSet + descriptorSetCount <= MAX_SETS);
639
640 for (uint32_t i = 0; i < descriptorSetCount; i++) {
641 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
642 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
643 layout, firstSet + i, set,
644 &dynamicOffsetCount,
645 &pDynamicOffsets);
646 }
647 }
648
649 void anv_CmdBindVertexBuffers(
650 VkCommandBuffer commandBuffer,
651 uint32_t firstBinding,
652 uint32_t bindingCount,
653 const VkBuffer* pBuffers,
654 const VkDeviceSize* pOffsets)
655 {
656 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
657 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
658
659 /* We have to defer setting up vertex buffer since we need the buffer
660 * stride from the pipeline. */
661
662 assert(firstBinding + bindingCount <= MAX_VBS);
663 for (uint32_t i = 0; i < bindingCount; i++) {
664 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
665 vb[firstBinding + i].offset = pOffsets[i];
666 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
667 }
668 }
669
670 void anv_CmdBindTransformFeedbackBuffersEXT(
671 VkCommandBuffer commandBuffer,
672 uint32_t firstBinding,
673 uint32_t bindingCount,
674 const VkBuffer* pBuffers,
675 const VkDeviceSize* pOffsets,
676 const VkDeviceSize* pSizes)
677 {
678 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
679 struct anv_xfb_binding *xfb = cmd_buffer->state.xfb_bindings;
680
681 /* We have to defer setting up vertex buffer since we need the buffer
682 * stride from the pipeline. */
683
684 assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
685 for (uint32_t i = 0; i < bindingCount; i++) {
686 if (pBuffers[i] == VK_NULL_HANDLE) {
687 xfb[firstBinding + i].buffer = NULL;
688 } else {
689 ANV_FROM_HANDLE(anv_buffer, buffer, pBuffers[i]);
690 xfb[firstBinding + i].buffer = buffer;
691 xfb[firstBinding + i].offset = pOffsets[i];
692 xfb[firstBinding + i].size =
693 anv_buffer_get_range(buffer, pOffsets[i],
694 pSizes ? pSizes[i] : VK_WHOLE_SIZE);
695 }
696 }
697 }
698
699 enum isl_format
700 anv_isl_format_for_descriptor_type(VkDescriptorType type)
701 {
702 switch (type) {
703 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
704 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
705 return ISL_FORMAT_R32G32B32A32_FLOAT;
706
707 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
708 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
709 return ISL_FORMAT_RAW;
710
711 default:
712 unreachable("Invalid descriptor type");
713 }
714 }
715
716 struct anv_state
717 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
718 const void *data, uint32_t size, uint32_t alignment)
719 {
720 struct anv_state state;
721
722 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
723 memcpy(state.map, data, size);
724
725 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
726
727 return state;
728 }
729
730 struct anv_state
731 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
732 uint32_t *a, uint32_t *b,
733 uint32_t dwords, uint32_t alignment)
734 {
735 struct anv_state state;
736 uint32_t *p;
737
738 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
739 dwords * 4, alignment);
740 p = state.map;
741 for (uint32_t i = 0; i < dwords; i++)
742 p[i] = a[i] | b[i];
743
744 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
745
746 return state;
747 }
748
749 static uint32_t
750 anv_push_constant_value(const struct anv_cmd_pipeline_state *state,
751 const struct anv_push_constants *data, uint32_t param)
752 {
753 if (BRW_PARAM_IS_BUILTIN(param)) {
754 switch (param) {
755 case BRW_PARAM_BUILTIN_ZERO:
756 return 0;
757 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_X:
758 return data->base_work_group_id[0];
759 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Y:
760 return data->base_work_group_id[1];
761 case BRW_PARAM_BUILTIN_BASE_WORK_GROUP_ID_Z:
762 return data->base_work_group_id[2];
763 default:
764 unreachable("Invalid param builtin");
765 }
766 } else if (ANV_PARAM_IS_PUSH(param)) {
767 uint32_t offset = ANV_PARAM_PUSH_OFFSET(param);
768 assert(offset % sizeof(uint32_t) == 0);
769 if (offset < data->size)
770 return *(uint32_t *)((uint8_t *)data + offset);
771 else
772 return 0;
773 } else if (ANV_PARAM_IS_DYN_OFFSET(param)) {
774 unsigned idx = ANV_PARAM_DYN_OFFSET_IDX(param);
775 assert(idx < MAX_DYNAMIC_BUFFERS);
776 return state->dynamic_offsets[idx];
777 }
778
779 assert(!"Invalid param");
780 return 0;
781 }
782
783 struct anv_state
784 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
785 gl_shader_stage stage)
786 {
787 struct anv_cmd_pipeline_state *pipeline_state = &cmd_buffer->state.gfx.base;
788 struct anv_pipeline *pipeline = cmd_buffer->state.gfx.base.pipeline;
789
790 /* If we don't have this stage, bail. */
791 if (!anv_pipeline_has_stage(pipeline, stage))
792 return (struct anv_state) { .offset = 0 };
793
794 struct anv_push_constants *data =
795 cmd_buffer->state.push_constants[stage];
796 const struct brw_stage_prog_data *prog_data =
797 pipeline->shaders[stage]->prog_data;
798
799 /* If we don't actually have any push constants, bail. */
800 if (prog_data == NULL || prog_data->nr_params == 0 || data == NULL)
801 return (struct anv_state) { .offset = 0 };
802
803 struct anv_state state =
804 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
805 prog_data->nr_params * sizeof(float),
806 32 /* bottom 5 bits MBZ */);
807
808 /* Walk through the param array and fill the buffer with data */
809 uint32_t *u32_map = state.map;
810 for (unsigned i = 0; i < prog_data->nr_params; i++) {
811 u32_map[i] = anv_push_constant_value(pipeline_state, data,
812 prog_data->param[i]);
813 }
814
815 return state;
816 }
817
818 struct anv_state
819 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
820 {
821 struct anv_cmd_pipeline_state *pipeline_state = &cmd_buffer->state.compute.base;
822 struct anv_push_constants *data =
823 cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
824 struct anv_pipeline *pipeline = cmd_buffer->state.compute.base.pipeline;
825 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
826 const struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
827
828 /* If we don't actually have any push constants, bail. */
829 if (cs_prog_data->push.total.size == 0)
830 return (struct anv_state) { .offset = 0 };
831
832 const unsigned push_constant_alignment =
833 cmd_buffer->device->info.gen < 8 ? 32 : 64;
834 const unsigned aligned_total_push_constants_size =
835 ALIGN(cs_prog_data->push.total.size, push_constant_alignment);
836 struct anv_state state =
837 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
838 aligned_total_push_constants_size,
839 push_constant_alignment);
840
841 /* Walk through the param array and fill the buffer with data */
842 uint32_t *u32_map = state.map;
843
844 if (cs_prog_data->push.cross_thread.size > 0) {
845 for (unsigned i = 0;
846 i < cs_prog_data->push.cross_thread.dwords;
847 i++) {
848 assert(prog_data->param[i] != BRW_PARAM_BUILTIN_SUBGROUP_ID);
849 u32_map[i] = anv_push_constant_value(pipeline_state, data,
850 prog_data->param[i]);
851 }
852 }
853
854 if (cs_prog_data->push.per_thread.size > 0) {
855 for (unsigned t = 0; t < cs_prog_data->threads; t++) {
856 unsigned dst =
857 8 * (cs_prog_data->push.per_thread.regs * t +
858 cs_prog_data->push.cross_thread.regs);
859 unsigned src = cs_prog_data->push.cross_thread.dwords;
860 for ( ; src < prog_data->nr_params; src++, dst++) {
861 if (prog_data->param[src] == BRW_PARAM_BUILTIN_SUBGROUP_ID) {
862 u32_map[dst] = t;
863 } else {
864 u32_map[dst] = anv_push_constant_value(pipeline_state, data,
865 prog_data->param[src]);
866 }
867 }
868 }
869 }
870
871 return state;
872 }
873
874 void anv_CmdPushConstants(
875 VkCommandBuffer commandBuffer,
876 VkPipelineLayout layout,
877 VkShaderStageFlags stageFlags,
878 uint32_t offset,
879 uint32_t size,
880 const void* pValues)
881 {
882 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
883
884 anv_foreach_stage(stage, stageFlags) {
885 VkResult result =
886 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer,
887 stage, client_data);
888 if (result != VK_SUCCESS)
889 return;
890
891 memcpy(cmd_buffer->state.push_constants[stage]->client_data + offset,
892 pValues, size);
893 }
894
895 cmd_buffer->state.push_constants_dirty |= stageFlags;
896 }
897
898 VkResult anv_CreateCommandPool(
899 VkDevice _device,
900 const VkCommandPoolCreateInfo* pCreateInfo,
901 const VkAllocationCallbacks* pAllocator,
902 VkCommandPool* pCmdPool)
903 {
904 ANV_FROM_HANDLE(anv_device, device, _device);
905 struct anv_cmd_pool *pool;
906
907 pool = vk_alloc2(&device->alloc, pAllocator, sizeof(*pool), 8,
908 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
909 if (pool == NULL)
910 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
911
912 if (pAllocator)
913 pool->alloc = *pAllocator;
914 else
915 pool->alloc = device->alloc;
916
917 list_inithead(&pool->cmd_buffers);
918
919 *pCmdPool = anv_cmd_pool_to_handle(pool);
920
921 return VK_SUCCESS;
922 }
923
924 void anv_DestroyCommandPool(
925 VkDevice _device,
926 VkCommandPool commandPool,
927 const VkAllocationCallbacks* pAllocator)
928 {
929 ANV_FROM_HANDLE(anv_device, device, _device);
930 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
931
932 if (!pool)
933 return;
934
935 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
936 &pool->cmd_buffers, pool_link) {
937 anv_cmd_buffer_destroy(cmd_buffer);
938 }
939
940 vk_free2(&device->alloc, pAllocator, pool);
941 }
942
943 VkResult anv_ResetCommandPool(
944 VkDevice device,
945 VkCommandPool commandPool,
946 VkCommandPoolResetFlags flags)
947 {
948 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
949
950 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
951 &pool->cmd_buffers, pool_link) {
952 anv_cmd_buffer_reset(cmd_buffer);
953 }
954
955 return VK_SUCCESS;
956 }
957
958 void anv_TrimCommandPool(
959 VkDevice device,
960 VkCommandPool commandPool,
961 VkCommandPoolTrimFlags flags)
962 {
963 /* Nothing for us to do here. Our pools stay pretty tidy. */
964 }
965
966 /**
967 * Return NULL if the current subpass has no depthstencil attachment.
968 */
969 const struct anv_image_view *
970 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
971 {
972 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
973 const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
974
975 if (subpass->depth_stencil_attachment == NULL)
976 return NULL;
977
978 const struct anv_image_view *iview =
979 fb->attachments[subpass->depth_stencil_attachment->attachment];
980
981 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
982 VK_IMAGE_ASPECT_STENCIL_BIT));
983
984 return iview;
985 }
986
987 static struct anv_descriptor_set *
988 anv_cmd_buffer_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
989 VkPipelineBindPoint bind_point,
990 struct anv_descriptor_set_layout *layout,
991 uint32_t _set)
992 {
993 struct anv_cmd_pipeline_state *pipe_state;
994 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
995 pipe_state = &cmd_buffer->state.compute.base;
996 } else {
997 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
998 pipe_state = &cmd_buffer->state.gfx.base;
999 }
1000
1001 struct anv_push_descriptor_set **push_set =
1002 &pipe_state->push_descriptors[_set];
1003
1004 if (*push_set == NULL) {
1005 *push_set = vk_zalloc(&cmd_buffer->pool->alloc,
1006 sizeof(struct anv_push_descriptor_set), 8,
1007 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1008 if (*push_set == NULL) {
1009 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
1010 return NULL;
1011 }
1012 }
1013
1014 struct anv_descriptor_set *set = &(*push_set)->set;
1015
1016 if (set->layout != layout) {
1017 if (set->layout)
1018 anv_descriptor_set_layout_unref(cmd_buffer->device, set->layout);
1019 anv_descriptor_set_layout_ref(layout);
1020 set->layout = layout;
1021 }
1022 set->size = anv_descriptor_set_layout_size(layout);
1023 set->buffer_view_count = layout->buffer_view_count;
1024 set->buffer_views = (*push_set)->buffer_views;
1025
1026 if (layout->descriptor_buffer_size &&
1027 ((*push_set)->set_used_on_gpu ||
1028 set->desc_mem.alloc_size < layout->descriptor_buffer_size)) {
1029 /* The previous buffer is either actively used by some GPU command (so
1030 * we can't modify it) or is too small. Allocate a new one.
1031 */
1032 struct anv_state desc_mem =
1033 anv_state_stream_alloc(&cmd_buffer->dynamic_state_stream,
1034 layout->descriptor_buffer_size, 32);
1035 if (set->desc_mem.alloc_size) {
1036 /* TODO: Do we really need to copy all the time? */
1037 memcpy(desc_mem.map, set->desc_mem.map,
1038 MIN2(desc_mem.alloc_size, set->desc_mem.alloc_size));
1039 }
1040 set->desc_mem = desc_mem;
1041
1042 struct anv_address addr = {
1043 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
1044 .offset = set->desc_mem.offset,
1045 };
1046
1047 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1048 set->desc_surface_state =
1049 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1050 isl_dev->ss.size, isl_dev->ss.align);
1051 anv_fill_buffer_surface_state(cmd_buffer->device,
1052 set->desc_surface_state,
1053 ISL_FORMAT_R32G32B32A32_FLOAT,
1054 addr, layout->descriptor_buffer_size, 1);
1055 }
1056
1057 return set;
1058 }
1059
1060 void anv_CmdPushDescriptorSetKHR(
1061 VkCommandBuffer commandBuffer,
1062 VkPipelineBindPoint pipelineBindPoint,
1063 VkPipelineLayout _layout,
1064 uint32_t _set,
1065 uint32_t descriptorWriteCount,
1066 const VkWriteDescriptorSet* pDescriptorWrites)
1067 {
1068 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1069 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1070
1071 assert(_set < MAX_SETS);
1072
1073 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1074
1075 struct anv_descriptor_set *set =
1076 anv_cmd_buffer_push_descriptor_set(cmd_buffer, pipelineBindPoint,
1077 set_layout, _set);
1078 if (!set)
1079 return;
1080
1081 /* Go through the user supplied descriptors. */
1082 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
1083 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
1084
1085 switch (write->descriptorType) {
1086 case VK_DESCRIPTOR_TYPE_SAMPLER:
1087 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
1088 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
1089 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
1090 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
1091 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1092 anv_descriptor_set_write_image_view(cmd_buffer->device, set,
1093 write->pImageInfo + j,
1094 write->descriptorType,
1095 write->dstBinding,
1096 write->dstArrayElement + j);
1097 }
1098 break;
1099
1100 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
1101 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
1102 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1103 ANV_FROM_HANDLE(anv_buffer_view, bview,
1104 write->pTexelBufferView[j]);
1105
1106 anv_descriptor_set_write_buffer_view(cmd_buffer->device, set,
1107 write->descriptorType,
1108 bview,
1109 write->dstBinding,
1110 write->dstArrayElement + j);
1111 }
1112 break;
1113
1114 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1115 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1116 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1117 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1118 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1119 assert(write->pBufferInfo[j].buffer);
1120 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1121 assert(buffer);
1122
1123 anv_descriptor_set_write_buffer(cmd_buffer->device, set,
1124 &cmd_buffer->surface_state_stream,
1125 write->descriptorType,
1126 buffer,
1127 write->dstBinding,
1128 write->dstArrayElement + j,
1129 write->pBufferInfo[j].offset,
1130 write->pBufferInfo[j].range);
1131 }
1132 break;
1133
1134 case VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT: {
1135 const VkWriteDescriptorSetInlineUniformBlockEXT *inline_write =
1136 vk_find_struct_const(write->pNext,
1137 WRITE_DESCRIPTOR_SET_INLINE_UNIFORM_BLOCK_EXT);
1138 assert(inline_write->dataSize == write->descriptorCount);
1139 anv_descriptor_set_write_inline_uniform_data(cmd_buffer->device, set,
1140 write->dstBinding,
1141 inline_write->pData,
1142 write->dstArrayElement,
1143 inline_write->dataSize);
1144 break;
1145 }
1146
1147 default:
1148 break;
1149 }
1150 }
1151
1152 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1153 layout, _set, set, NULL, NULL);
1154 }
1155
1156 void anv_CmdPushDescriptorSetWithTemplateKHR(
1157 VkCommandBuffer commandBuffer,
1158 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1159 VkPipelineLayout _layout,
1160 uint32_t _set,
1161 const void* pData)
1162 {
1163 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1164 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1165 descriptorUpdateTemplate);
1166 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1167
1168 assert(_set < MAX_PUSH_DESCRIPTORS);
1169
1170 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1171
1172 struct anv_descriptor_set *set =
1173 anv_cmd_buffer_push_descriptor_set(cmd_buffer, template->bind_point,
1174 set_layout, _set);
1175 if (!set)
1176 return;
1177
1178 anv_descriptor_set_write_template(cmd_buffer->device, set,
1179 &cmd_buffer->surface_state_stream,
1180 template,
1181 pData);
1182
1183 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1184 layout, _set, set, NULL, NULL);
1185 }
1186
1187 void anv_CmdSetDeviceMask(
1188 VkCommandBuffer commandBuffer,
1189 uint32_t deviceMask)
1190 {
1191 /* No-op */
1192 }