projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
anv: add support for dynamic cull mode and winding order
[mesa.git] / src / intel / vulkan / anv_cmd_buffer.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31
32 #include "vk_format_info.h"
33 #include "vk_util.h"
34
35 /** \file anv_cmd_buffer.c
36 *
37 * This file contains all of the stuff for emitting commands into a command
38 * buffer. This includes implementations of most of the vkCmd*
39 * entrypoints. This file is concerned entirely with state emission and
40 * not with the command buffer data structure itself. As far as this file
41 * is concerned, most of anv_cmd_buffer is magic.
42 */
43
44 /* TODO: These are taken from GLES. We should check the Vulkan spec */
45 const struct anv_dynamic_state default_dynamic_state = {
46 .viewport = {
47 .count = 0,
48 },
49 .scissor = {
50 .count = 0,
51 },
52 .line_width = 1.0f,
53 .depth_bias = {
54 .bias = 0.0f,
55 .clamp = 0.0f,
56 .slope = 0.0f,
57 },
58 .blend_constants = { 0.0f, 0.0f, 0.0f, 0.0f },
59 .depth_bounds = {
60 .min = 0.0f,
61 .max = 1.0f,
62 },
63 .stencil_compare_mask = {
64 .front = ~0u,
65 .back = ~0u,
66 },
67 .stencil_write_mask = {
68 .front = ~0u,
69 .back = ~0u,
70 },
71 .stencil_reference = {
72 .front = 0u,
73 .back = 0u,
74 },
75 .line_stipple = {
76 .factor = 0u,
77 .pattern = 0u,
78 },
79 .cull_mode = 0,
80 .front_face = 0,
81 };
82
83 /**
84 * Copy the dynamic state from src to dest based on the copy_mask.
85 *
86 * Avoid copying states that have not changed, except for VIEWPORT, SCISSOR and
87 * BLEND_CONSTANTS (always copy them if they are in the copy_mask).
88 *
89 * Returns a mask of the states which changed.
90 */
91 anv_cmd_dirty_mask_t
92 anv_dynamic_state_copy(struct anv_dynamic_state *dest,
93 const struct anv_dynamic_state *src,
94 anv_cmd_dirty_mask_t copy_mask)
95 {
96 anv_cmd_dirty_mask_t changed = 0;
97
98 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_VIEWPORT) {
99 dest->viewport.count = src->viewport.count;
100 typed_memcpy(dest->viewport.viewports, src->viewport.viewports,
101 src->viewport.count);
102 changed |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
103 }
104
105 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_SCISSOR) {
106 dest->scissor.count = src->scissor.count;
107 typed_memcpy(dest->scissor.scissors, src->scissor.scissors,
108 src->scissor.count);
109 changed |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
110 }
111
112 if (copy_mask & ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS) {
113 typed_memcpy(dest->blend_constants, src->blend_constants, 4);
114 changed |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
115 }
116
117 #define ANV_CMP_COPY(field, flag) \
118 if (copy_mask & flag) { \
119 if (dest->field != src->field) { \
120 dest->field = src->field; \
121 changed |= flag; \
122 } \
123 }
124
125 ANV_CMP_COPY(line_width, ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH);
126
127 ANV_CMP_COPY(depth_bias.bias, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
128 ANV_CMP_COPY(depth_bias.clamp, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
129 ANV_CMP_COPY(depth_bias.slope, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS);
130
131 ANV_CMP_COPY(depth_bounds.min, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS);
132 ANV_CMP_COPY(depth_bounds.max, ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS);
133
134 ANV_CMP_COPY(stencil_compare_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK);
135 ANV_CMP_COPY(stencil_compare_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK);
136
137 ANV_CMP_COPY(stencil_write_mask.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
138 ANV_CMP_COPY(stencil_write_mask.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK);
139
140 ANV_CMP_COPY(stencil_reference.front, ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE);
141 ANV_CMP_COPY(stencil_reference.back, ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE);
142
143 ANV_CMP_COPY(line_stipple.factor, ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE);
144 ANV_CMP_COPY(line_stipple.pattern, ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE);
145
146 ANV_CMP_COPY(cull_mode, ANV_CMD_DIRTY_DYNAMIC_CULL_MODE);
147 ANV_CMP_COPY(front_face, ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE);
148
149 #undef ANV_CMP_COPY
150
151 return changed;
152 }
153
154 static void
155 anv_cmd_state_init(struct anv_cmd_buffer *cmd_buffer)
156 {
157 struct anv_cmd_state *state = &cmd_buffer->state;
158
159 memset(state, 0, sizeof(*state));
160
161 state->current_pipeline = UINT32_MAX;
162 state->restart_index = UINT32_MAX;
163 state->gfx.dynamic = default_dynamic_state;
164 }
165
166 static void
167 anv_cmd_pipeline_state_finish(struct anv_cmd_buffer *cmd_buffer,
168 struct anv_cmd_pipeline_state *pipe_state)
169 {
170 for (uint32_t i = 0; i < ARRAY_SIZE(pipe_state->push_descriptors); i++) {
171 if (pipe_state->push_descriptors[i]) {
172 anv_descriptor_set_layout_unref(cmd_buffer->device,
173 pipe_state->push_descriptors[i]->set.layout);
174 vk_free(&cmd_buffer->pool->alloc, pipe_state->push_descriptors[i]);
175 }
176 }
177 }
178
179 static void
180 anv_cmd_state_finish(struct anv_cmd_buffer *cmd_buffer)
181 {
182 struct anv_cmd_state *state = &cmd_buffer->state;
183
184 anv_cmd_pipeline_state_finish(cmd_buffer, &state->gfx.base);
185 anv_cmd_pipeline_state_finish(cmd_buffer, &state->compute.base);
186
187 vk_free(&cmd_buffer->pool->alloc, state->attachments);
188 }
189
190 static void
191 anv_cmd_state_reset(struct anv_cmd_buffer *cmd_buffer)
192 {
193 anv_cmd_state_finish(cmd_buffer);
194 anv_cmd_state_init(cmd_buffer);
195 }
196
197 static VkResult anv_create_cmd_buffer(
198 struct anv_device * device,
199 struct anv_cmd_pool * pool,
200 VkCommandBufferLevel level,
201 VkCommandBuffer* pCommandBuffer)
202 {
203 struct anv_cmd_buffer *cmd_buffer;
204 VkResult result;
205
206 cmd_buffer = vk_alloc(&pool->alloc, sizeof(*cmd_buffer), 8,
207 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
208 if (cmd_buffer == NULL)
209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
210
211 vk_object_base_init(&device->vk, &cmd_buffer->base,
212 VK_OBJECT_TYPE_COMMAND_BUFFER);
213
214 cmd_buffer->batch.status = VK_SUCCESS;
215
216 cmd_buffer->device = device;
217 cmd_buffer->pool = pool;
218 cmd_buffer->level = level;
219
220 result = anv_cmd_buffer_init_batch_bo_chain(cmd_buffer);
221 if (result != VK_SUCCESS)
222 goto fail;
223
224 anv_state_stream_init(&cmd_buffer->surface_state_stream,
225 &device->surface_state_pool, 4096);
226 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
227 &device->dynamic_state_pool, 16384);
228
229 anv_cmd_state_init(cmd_buffer);
230
231 if (pool) {
232 list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);
233 } else {
234 /* Init the pool_link so we can safefly call list_del when we destroy
235 * the command buffer
236 */
237 list_inithead(&cmd_buffer->pool_link);
238 }
239
240 *pCommandBuffer = anv_cmd_buffer_to_handle(cmd_buffer);
241
242 return VK_SUCCESS;
243
244 fail:
245 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
246
247 return result;
248 }
249
250 VkResult anv_AllocateCommandBuffers(
251 VkDevice _device,
252 const VkCommandBufferAllocateInfo* pAllocateInfo,
253 VkCommandBuffer* pCommandBuffers)
254 {
255 ANV_FROM_HANDLE(anv_device, device, _device);
256 ANV_FROM_HANDLE(anv_cmd_pool, pool, pAllocateInfo->commandPool);
257
258 VkResult result = VK_SUCCESS;
259 uint32_t i;
260
261 for (i = 0; i < pAllocateInfo->commandBufferCount; i++) {
262 result = anv_create_cmd_buffer(device, pool, pAllocateInfo->level,
263 &pCommandBuffers[i]);
264 if (result != VK_SUCCESS)
265 break;
266 }
267
268 if (result != VK_SUCCESS) {
269 anv_FreeCommandBuffers(_device, pAllocateInfo->commandPool,
270 i, pCommandBuffers);
271 for (i = 0; i < pAllocateInfo->commandBufferCount; i++)
272 pCommandBuffers[i] = VK_NULL_HANDLE;
273 }
274
275 return result;
276 }
277
278 static void
279 anv_cmd_buffer_destroy(struct anv_cmd_buffer *cmd_buffer)
280 {
281 list_del(&cmd_buffer->pool_link);
282
283 anv_cmd_buffer_fini_batch_bo_chain(cmd_buffer);
284
285 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
286 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
287
288 anv_cmd_state_finish(cmd_buffer);
289
290 vk_object_base_finish(&cmd_buffer->base);
291 vk_free(&cmd_buffer->pool->alloc, cmd_buffer);
292 }
293
294 void anv_FreeCommandBuffers(
295 VkDevice device,
296 VkCommandPool commandPool,
297 uint32_t commandBufferCount,
298 const VkCommandBuffer* pCommandBuffers)
299 {
300 for (uint32_t i = 0; i < commandBufferCount; i++) {
301 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);
302
303 if (!cmd_buffer)
304 continue;
305
306 anv_cmd_buffer_destroy(cmd_buffer);
307 }
308 }
309
310 VkResult
311 anv_cmd_buffer_reset(struct anv_cmd_buffer *cmd_buffer)
312 {
313 cmd_buffer->usage_flags = 0;
314 cmd_buffer->perf_query_pool = NULL;
315 anv_cmd_buffer_reset_batch_bo_chain(cmd_buffer);
316 anv_cmd_state_reset(cmd_buffer);
317
318 anv_state_stream_finish(&cmd_buffer->surface_state_stream);
319 anv_state_stream_init(&cmd_buffer->surface_state_stream,
320 &cmd_buffer->device->surface_state_pool, 4096);
321
322 anv_state_stream_finish(&cmd_buffer->dynamic_state_stream);
323 anv_state_stream_init(&cmd_buffer->dynamic_state_stream,
324 &cmd_buffer->device->dynamic_state_pool, 16384);
325 return VK_SUCCESS;
326 }
327
328 VkResult anv_ResetCommandBuffer(
329 VkCommandBuffer commandBuffer,
330 VkCommandBufferResetFlags flags)
331 {
332 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
333 return anv_cmd_buffer_reset(cmd_buffer);
334 }
335
336 #define anv_genX_call(devinfo, func, ...) \
337 switch ((devinfo)->gen) { \
338 case 7: \
339 if ((devinfo)->is_haswell) { \
340 gen75_##func(__VA_ARGS__); \
341 } else { \
342 gen7_##func(__VA_ARGS__); \
343 } \
344 break; \
345 case 8: \
346 gen8_##func(__VA_ARGS__); \
347 break; \
348 case 9: \
349 gen9_##func(__VA_ARGS__); \
350 break; \
351 case 10: \
352 gen10_##func(__VA_ARGS__); \
353 break; \
354 case 11: \
355 gen11_##func(__VA_ARGS__); \
356 break; \
357 case 12: \
358 gen12_##func(__VA_ARGS__); \
359 break; \
360 default: \
361 assert(!"Unknown hardware generation"); \
362 }
363
364 void
365 anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer)
366 {
367 anv_genX_call(&cmd_buffer->device->info,
368 cmd_buffer_emit_state_base_address,
369 cmd_buffer);
370 }
371
372 void
373 anv_cmd_buffer_mark_image_written(struct anv_cmd_buffer *cmd_buffer,
374 const struct anv_image *image,
375 VkImageAspectFlagBits aspect,
376 enum isl_aux_usage aux_usage,
377 uint32_t level,
378 uint32_t base_layer,
379 uint32_t layer_count)
380 {
381 anv_genX_call(&cmd_buffer->device->info,
382 cmd_buffer_mark_image_written,
383 cmd_buffer, image, aspect, aux_usage,
384 level, base_layer, layer_count);
385 }
386
387 void
388 anv_cmd_emit_conditional_render_predicate(struct anv_cmd_buffer *cmd_buffer)
389 {
390 anv_genX_call(&cmd_buffer->device->info,
391 cmd_emit_conditional_render_predicate,
392 cmd_buffer);
393 }
394
395 static bool
396 mem_update(void *dst, const void *src, size_t size)
397 {
398 if (memcmp(dst, src, size) == 0)
399 return false;
400
401 memcpy(dst, src, size);
402 return true;
403 }
404
405 static void
406 set_dirty_for_bind_map(struct anv_cmd_buffer *cmd_buffer,
407 gl_shader_stage stage,
408 const struct anv_pipeline_bind_map *map)
409 {
410 if (mem_update(cmd_buffer->state.surface_sha1s[stage],
411 map->surface_sha1, sizeof(map->surface_sha1)))
412 cmd_buffer->state.descriptors_dirty |= mesa_to_vk_shader_stage(stage);
413
414 if (mem_update(cmd_buffer->state.sampler_sha1s[stage],
415 map->sampler_sha1, sizeof(map->sampler_sha1)))
416 cmd_buffer->state.descriptors_dirty |= mesa_to_vk_shader_stage(stage);
417
418 if (mem_update(cmd_buffer->state.push_sha1s[stage],
419 map->push_sha1, sizeof(map->push_sha1)))
420 cmd_buffer->state.push_constants_dirty |= mesa_to_vk_shader_stage(stage);
421 }
422
423 void anv_CmdBindPipeline(
424 VkCommandBuffer commandBuffer,
425 VkPipelineBindPoint pipelineBindPoint,
426 VkPipeline _pipeline)
427 {
428 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
429 ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
430
431 switch (pipelineBindPoint) {
432 case VK_PIPELINE_BIND_POINT_COMPUTE: {
433 struct anv_compute_pipeline *compute_pipeline =
434 anv_pipeline_to_compute(pipeline);
435 if (cmd_buffer->state.compute.pipeline == compute_pipeline)
436 return;
437
438 cmd_buffer->state.compute.pipeline = compute_pipeline;
439 cmd_buffer->state.compute.pipeline_dirty = true;
440 set_dirty_for_bind_map(cmd_buffer, MESA_SHADER_COMPUTE,
441 &compute_pipeline->cs->bind_map);
442 break;
443 }
444
445 case VK_PIPELINE_BIND_POINT_GRAPHICS: {
446 struct anv_graphics_pipeline *gfx_pipeline =
447 anv_pipeline_to_graphics(pipeline);
448 if (cmd_buffer->state.gfx.pipeline == gfx_pipeline)
449 return;
450
451 cmd_buffer->state.gfx.pipeline = gfx_pipeline;
452 cmd_buffer->state.gfx.vb_dirty |= gfx_pipeline->vb_used;
453 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_PIPELINE;
454
455 anv_foreach_stage(stage, gfx_pipeline->active_stages) {
456 set_dirty_for_bind_map(cmd_buffer, stage,
457 &gfx_pipeline->shaders[stage]->bind_map);
458 }
459
460 /* Apply the dynamic state from the pipeline */
461 cmd_buffer->state.gfx.dirty |=
462 anv_dynamic_state_copy(&cmd_buffer->state.gfx.dynamic,
463 &gfx_pipeline->dynamic_state,
464 gfx_pipeline->dynamic_state_mask);
465 break;
466 }
467
468 default:
469 assert(!"invalid bind point");
470 break;
471 }
472 }
473
474 void anv_CmdSetViewport(
475 VkCommandBuffer commandBuffer,
476 uint32_t firstViewport,
477 uint32_t viewportCount,
478 const VkViewport* pViewports)
479 {
480 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
481
482 const uint32_t total_count = firstViewport + viewportCount;
483 if (cmd_buffer->state.gfx.dynamic.viewport.count < total_count)
484 cmd_buffer->state.gfx.dynamic.viewport.count = total_count;
485
486 memcpy(cmd_buffer->state.gfx.dynamic.viewport.viewports + firstViewport,
487 pViewports, viewportCount * sizeof(*pViewports));
488
489 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_VIEWPORT;
490 }
491
492 void anv_CmdSetScissor(
493 VkCommandBuffer commandBuffer,
494 uint32_t firstScissor,
495 uint32_t scissorCount,
496 const VkRect2D* pScissors)
497 {
498 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
499
500 const uint32_t total_count = firstScissor + scissorCount;
501 if (cmd_buffer->state.gfx.dynamic.scissor.count < total_count)
502 cmd_buffer->state.gfx.dynamic.scissor.count = total_count;
503
504 memcpy(cmd_buffer->state.gfx.dynamic.scissor.scissors + firstScissor,
505 pScissors, scissorCount * sizeof(*pScissors));
506
507 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_SCISSOR;
508 }
509
510 void anv_CmdSetLineWidth(
511 VkCommandBuffer commandBuffer,
512 float lineWidth)
513 {
514 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
515
516 cmd_buffer->state.gfx.dynamic.line_width = lineWidth;
517 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;
518 }
519
520 void anv_CmdSetDepthBias(
521 VkCommandBuffer commandBuffer,
522 float depthBiasConstantFactor,
523 float depthBiasClamp,
524 float depthBiasSlopeFactor)
525 {
526 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
527
528 cmd_buffer->state.gfx.dynamic.depth_bias.bias = depthBiasConstantFactor;
529 cmd_buffer->state.gfx.dynamic.depth_bias.clamp = depthBiasClamp;
530 cmd_buffer->state.gfx.dynamic.depth_bias.slope = depthBiasSlopeFactor;
531
532 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BIAS;
533 }
534
535 void anv_CmdSetBlendConstants(
536 VkCommandBuffer commandBuffer,
537 const float blendConstants[4])
538 {
539 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
540
541 memcpy(cmd_buffer->state.gfx.dynamic.blend_constants,
542 blendConstants, sizeof(float) * 4);
543
544 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_BLEND_CONSTANTS;
545 }
546
547 void anv_CmdSetDepthBounds(
548 VkCommandBuffer commandBuffer,
549 float minDepthBounds,
550 float maxDepthBounds)
551 {
552 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
553
554 cmd_buffer->state.gfx.dynamic.depth_bounds.min = minDepthBounds;
555 cmd_buffer->state.gfx.dynamic.depth_bounds.max = maxDepthBounds;
556
557 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_DEPTH_BOUNDS;
558 }
559
560 void anv_CmdSetStencilCompareMask(
561 VkCommandBuffer commandBuffer,
562 VkStencilFaceFlags faceMask,
563 uint32_t compareMask)
564 {
565 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
566
567 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
568 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.front = compareMask;
569 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
570 cmd_buffer->state.gfx.dynamic.stencil_compare_mask.back = compareMask;
571
572 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK;
573 }
574
575 void anv_CmdSetStencilWriteMask(
576 VkCommandBuffer commandBuffer,
577 VkStencilFaceFlags faceMask,
578 uint32_t writeMask)
579 {
580 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
581
582 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
583 cmd_buffer->state.gfx.dynamic.stencil_write_mask.front = writeMask;
584 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
585 cmd_buffer->state.gfx.dynamic.stencil_write_mask.back = writeMask;
586
587 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK;
588 }
589
590 void anv_CmdSetStencilReference(
591 VkCommandBuffer commandBuffer,
592 VkStencilFaceFlags faceMask,
593 uint32_t reference)
594 {
595 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
596
597 if (faceMask & VK_STENCIL_FACE_FRONT_BIT)
598 cmd_buffer->state.gfx.dynamic.stencil_reference.front = reference;
599 if (faceMask & VK_STENCIL_FACE_BACK_BIT)
600 cmd_buffer->state.gfx.dynamic.stencil_reference.back = reference;
601
602 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;
603 }
604
605 void anv_CmdSetLineStippleEXT(
606 VkCommandBuffer commandBuffer,
607 uint32_t lineStippleFactor,
608 uint16_t lineStipplePattern)
609 {
610 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
611
612 cmd_buffer->state.gfx.dynamic.line_stipple.factor = lineStippleFactor;
613 cmd_buffer->state.gfx.dynamic.line_stipple.pattern = lineStipplePattern;
614
615 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_LINE_STIPPLE;
616 }
617
618 void anv_CmdSetCullModeEXT(
619 VkCommandBuffer commandBuffer,
620 VkCullModeFlags cullMode)
621 {
622 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
623
624 cmd_buffer->state.gfx.dynamic.cull_mode = cullMode;
625
626 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_CULL_MODE;
627 }
628
629 void anv_CmdSetFrontFaceEXT(
630 VkCommandBuffer commandBuffer,
631 VkFrontFace frontFace)
632 {
633 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
634
635 cmd_buffer->state.gfx.dynamic.front_face = frontFace;
636
637 cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_DYNAMIC_FRONT_FACE;
638 }
639
640 static void
641 anv_cmd_buffer_bind_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
642 VkPipelineBindPoint bind_point,
643 struct anv_pipeline_layout *layout,
644 uint32_t set_index,
645 struct anv_descriptor_set *set,
646 uint32_t *dynamic_offset_count,
647 const uint32_t **dynamic_offsets)
648 {
649 struct anv_descriptor_set_layout *set_layout =
650 layout->set[set_index].layout;
651
652 VkShaderStageFlags stages = set_layout->shader_stages;
653 struct anv_cmd_pipeline_state *pipe_state;
654
655 switch (bind_point) {
656 case VK_PIPELINE_BIND_POINT_GRAPHICS:
657 stages &= VK_SHADER_STAGE_ALL_GRAPHICS;
658 pipe_state = &cmd_buffer->state.gfx.base;
659 break;
660
661 case VK_PIPELINE_BIND_POINT_COMPUTE:
662 stages &= VK_SHADER_STAGE_COMPUTE_BIT;
663 pipe_state = &cmd_buffer->state.compute.base;
664 break;
665
666 default:
667 unreachable("invalid bind point");
668 }
669
670 VkShaderStageFlags dirty_stages = 0;
671 if (pipe_state->descriptors[set_index] != set) {
672 pipe_state->descriptors[set_index] = set;
673 dirty_stages |= stages;
674 }
675
676 /* If it's a push descriptor set, we have to flag things as dirty
677 * regardless of whether or not the CPU-side data structure changed as we
678 * may have edited in-place.
679 */
680 if (set->pool == NULL)
681 dirty_stages |= stages;
682
683 if (dynamic_offsets) {
684 if (set_layout->dynamic_offset_count > 0) {
685 uint32_t dynamic_offset_start =
686 layout->set[set_index].dynamic_offset_start;
687
688 anv_foreach_stage(stage, stages) {
689 struct anv_push_constants *push =
690 &cmd_buffer->state.push_constants[stage];
691 uint32_t *push_offsets =
692 &push->dynamic_offsets[dynamic_offset_start];
693
694 /* Assert that everything is in range */
695 assert(set_layout->dynamic_offset_count <= *dynamic_offset_count);
696 assert(dynamic_offset_start + set_layout->dynamic_offset_count <=
697 ARRAY_SIZE(push->dynamic_offsets));
698
699 unsigned mask = set_layout->stage_dynamic_offsets[stage];
700 STATIC_ASSERT(MAX_DYNAMIC_BUFFERS <= sizeof(mask) * 8);
701 while (mask) {
702 int i = u_bit_scan(&mask);
703 if (push_offsets[i] != (*dynamic_offsets)[i]) {
704 push_offsets[i] = (*dynamic_offsets)[i];
705 dirty_stages |= mesa_to_vk_shader_stage(stage);
706 }
707 }
708 }
709
710 *dynamic_offsets += set_layout->dynamic_offset_count;
711 *dynamic_offset_count -= set_layout->dynamic_offset_count;
712 }
713 }
714
715 cmd_buffer->state.descriptors_dirty |= dirty_stages;
716 cmd_buffer->state.push_constants_dirty |= dirty_stages;
717 }
718
719 void anv_CmdBindDescriptorSets(
720 VkCommandBuffer commandBuffer,
721 VkPipelineBindPoint pipelineBindPoint,
722 VkPipelineLayout _layout,
723 uint32_t firstSet,
724 uint32_t descriptorSetCount,
725 const VkDescriptorSet* pDescriptorSets,
726 uint32_t dynamicOffsetCount,
727 const uint32_t* pDynamicOffsets)
728 {
729 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
730 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
731
732 assert(firstSet + descriptorSetCount <= MAX_SETS);
733
734 for (uint32_t i = 0; i < descriptorSetCount; i++) {
735 ANV_FROM_HANDLE(anv_descriptor_set, set, pDescriptorSets[i]);
736 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
737 layout, firstSet + i, set,
738 &dynamicOffsetCount,
739 &pDynamicOffsets);
740 }
741 }
742
743 void anv_CmdBindVertexBuffers(
744 VkCommandBuffer commandBuffer,
745 uint32_t firstBinding,
746 uint32_t bindingCount,
747 const VkBuffer* pBuffers,
748 const VkDeviceSize* pOffsets)
749 {
750 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
751 struct anv_vertex_binding *vb = cmd_buffer->state.vertex_bindings;
752
753 /* We have to defer setting up vertex buffer since we need the buffer
754 * stride from the pipeline. */
755
756 assert(firstBinding + bindingCount <= MAX_VBS);
757 for (uint32_t i = 0; i < bindingCount; i++) {
758 vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
759 vb[firstBinding + i].offset = pOffsets[i];
760 cmd_buffer->state.gfx.vb_dirty |= 1 << (firstBinding + i);
761 }
762 }
763
764 void anv_CmdBindTransformFeedbackBuffersEXT(
765 VkCommandBuffer commandBuffer,
766 uint32_t firstBinding,
767 uint32_t bindingCount,
768 const VkBuffer* pBuffers,
769 const VkDeviceSize* pOffsets,
770 const VkDeviceSize* pSizes)
771 {
772 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
773 struct anv_xfb_binding *xfb = cmd_buffer->state.xfb_bindings;
774
775 /* We have to defer setting up vertex buffer since we need the buffer
776 * stride from the pipeline. */
777
778 assert(firstBinding + bindingCount <= MAX_XFB_BUFFERS);
779 for (uint32_t i = 0; i < bindingCount; i++) {
780 if (pBuffers[i] == VK_NULL_HANDLE) {
781 xfb[firstBinding + i].buffer = NULL;
782 } else {
783 ANV_FROM_HANDLE(anv_buffer, buffer, pBuffers[i]);
784 xfb[firstBinding + i].buffer = buffer;
785 xfb[firstBinding + i].offset = pOffsets[i];
786 xfb[firstBinding + i].size =
787 anv_buffer_get_range(buffer, pOffsets[i],
788 pSizes ? pSizes[i] : VK_WHOLE_SIZE);
789 }
790 }
791 }
792
793 enum isl_format
794 anv_isl_format_for_descriptor_type(VkDescriptorType type)
795 {
796 switch (type) {
797 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
798 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
799 return ISL_FORMAT_R32G32B32A32_FLOAT;
800
801 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
802 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
803 return ISL_FORMAT_RAW;
804
805 default:
806 unreachable("Invalid descriptor type");
807 }
808 }
809
810 struct anv_state
811 anv_cmd_buffer_emit_dynamic(struct anv_cmd_buffer *cmd_buffer,
812 const void *data, uint32_t size, uint32_t alignment)
813 {
814 struct anv_state state;
815
816 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, alignment);
817 memcpy(state.map, data, size);
818
819 VG(VALGRIND_CHECK_MEM_IS_DEFINED(state.map, size));
820
821 return state;
822 }
823
824 struct anv_state
825 anv_cmd_buffer_merge_dynamic(struct anv_cmd_buffer *cmd_buffer,
826 uint32_t *a, uint32_t *b,
827 uint32_t dwords, uint32_t alignment)
828 {
829 struct anv_state state;
830 uint32_t *p;
831
832 state = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
833 dwords * 4, alignment);
834 p = state.map;
835 for (uint32_t i = 0; i < dwords; i++)
836 p[i] = a[i] | b[i];
837
838 VG(VALGRIND_CHECK_MEM_IS_DEFINED(p, dwords * 4));
839
840 return state;
841 }
842
843 struct anv_state
844 anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
845 gl_shader_stage stage)
846 {
847 struct anv_push_constants *data =
848 &cmd_buffer->state.push_constants[stage];
849
850 struct anv_state state =
851 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
852 sizeof(struct anv_push_constants),
853 32 /* bottom 5 bits MBZ */);
854 memcpy(state.map, data, sizeof(struct anv_push_constants));
855
856 return state;
857 }
858
859 struct anv_state
860 anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
861 {
862 struct anv_push_constants *data =
863 &cmd_buffer->state.push_constants[MESA_SHADER_COMPUTE];
864 struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
865 const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
866 const struct anv_push_range *range = &pipeline->cs->bind_map.push_ranges[0];
867
868 const struct anv_cs_parameters cs_params = anv_cs_parameters(pipeline);
869 const unsigned total_push_constants_size =
870 brw_cs_push_const_total_size(cs_prog_data, cs_params.threads);
871 if (total_push_constants_size == 0)
872 return (struct anv_state) { .offset = 0 };
873
874 const unsigned push_constant_alignment =
875 cmd_buffer->device->info.gen < 8 ? 32 : 64;
876 const unsigned aligned_total_push_constants_size =
877 ALIGN(total_push_constants_size, push_constant_alignment);
878 struct anv_state state =
879 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer,
880 aligned_total_push_constants_size,
881 push_constant_alignment);
882
883 void *dst = state.map;
884 const void *src = (char *)data + (range->start * 32);
885
886 if (cs_prog_data->push.cross_thread.size > 0) {
887 memcpy(dst, src, cs_prog_data->push.cross_thread.size);
888 dst += cs_prog_data->push.cross_thread.size;
889 src += cs_prog_data->push.cross_thread.size;
890 }
891
892 if (cs_prog_data->push.per_thread.size > 0) {
893 for (unsigned t = 0; t < cs_params.threads; t++) {
894 memcpy(dst, src, cs_prog_data->push.per_thread.size);
895
896 uint32_t *subgroup_id = dst +
897 offsetof(struct anv_push_constants, cs.subgroup_id) -
898 (range->start * 32 + cs_prog_data->push.cross_thread.size);
899 *subgroup_id = t;
900
901 dst += cs_prog_data->push.per_thread.size;
902 }
903 }
904
905 return state;
906 }
907
908 void anv_CmdPushConstants(
909 VkCommandBuffer commandBuffer,
910 VkPipelineLayout layout,
911 VkShaderStageFlags stageFlags,
912 uint32_t offset,
913 uint32_t size,
914 const void* pValues)
915 {
916 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
917
918 anv_foreach_stage(stage, stageFlags) {
919 memcpy(cmd_buffer->state.push_constants[stage].client_data + offset,
920 pValues, size);
921 }
922
923 cmd_buffer->state.push_constants_dirty |= stageFlags;
924 }
925
926 VkResult anv_CreateCommandPool(
927 VkDevice _device,
928 const VkCommandPoolCreateInfo* pCreateInfo,
929 const VkAllocationCallbacks* pAllocator,
930 VkCommandPool* pCmdPool)
931 {
932 ANV_FROM_HANDLE(anv_device, device, _device);
933 struct anv_cmd_pool *pool;
934
935 pool = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*pool), 8,
936 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
937 if (pool == NULL)
938 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
939
940 vk_object_base_init(&device->vk, &pool->base, VK_OBJECT_TYPE_COMMAND_POOL);
941
942 if (pAllocator)
943 pool->alloc = *pAllocator;
944 else
945 pool->alloc = device->vk.alloc;
946
947 list_inithead(&pool->cmd_buffers);
948
949 *pCmdPool = anv_cmd_pool_to_handle(pool);
950
951 return VK_SUCCESS;
952 }
953
954 void anv_DestroyCommandPool(
955 VkDevice _device,
956 VkCommandPool commandPool,
957 const VkAllocationCallbacks* pAllocator)
958 {
959 ANV_FROM_HANDLE(anv_device, device, _device);
960 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
961
962 if (!pool)
963 return;
964
965 list_for_each_entry_safe(struct anv_cmd_buffer, cmd_buffer,
966 &pool->cmd_buffers, pool_link) {
967 anv_cmd_buffer_destroy(cmd_buffer);
968 }
969
970 vk_object_base_finish(&pool->base);
971 vk_free2(&device->vk.alloc, pAllocator, pool);
972 }
973
974 VkResult anv_ResetCommandPool(
975 VkDevice device,
976 VkCommandPool commandPool,
977 VkCommandPoolResetFlags flags)
978 {
979 ANV_FROM_HANDLE(anv_cmd_pool, pool, commandPool);
980
981 list_for_each_entry(struct anv_cmd_buffer, cmd_buffer,
982 &pool->cmd_buffers, pool_link) {
983 anv_cmd_buffer_reset(cmd_buffer);
984 }
985
986 return VK_SUCCESS;
987 }
988
989 void anv_TrimCommandPool(
990 VkDevice device,
991 VkCommandPool commandPool,
992 VkCommandPoolTrimFlags flags)
993 {
994 /* Nothing for us to do here. Our pools stay pretty tidy. */
995 }
996
997 /**
998 * Return NULL if the current subpass has no depthstencil attachment.
999 */
1000 const struct anv_image_view *
1001 anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer)
1002 {
1003 const struct anv_subpass *subpass = cmd_buffer->state.subpass;
1004
1005 if (subpass->depth_stencil_attachment == NULL)
1006 return NULL;
1007
1008 const struct anv_image_view *iview =
1009 cmd_buffer->state.attachments[subpass->depth_stencil_attachment->attachment].image_view;
1010
1011 assert(iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT |
1012 VK_IMAGE_ASPECT_STENCIL_BIT));
1013
1014 return iview;
1015 }
1016
1017 static struct anv_descriptor_set *
1018 anv_cmd_buffer_push_descriptor_set(struct anv_cmd_buffer *cmd_buffer,
1019 VkPipelineBindPoint bind_point,
1020 struct anv_descriptor_set_layout *layout,
1021 uint32_t _set)
1022 {
1023 struct anv_cmd_pipeline_state *pipe_state;
1024 if (bind_point == VK_PIPELINE_BIND_POINT_COMPUTE) {
1025 pipe_state = &cmd_buffer->state.compute.base;
1026 } else {
1027 assert(bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS);
1028 pipe_state = &cmd_buffer->state.gfx.base;
1029 }
1030
1031 struct anv_push_descriptor_set **push_set =
1032 &pipe_state->push_descriptors[_set];
1033
1034 if (*push_set == NULL) {
1035 *push_set = vk_zalloc(&cmd_buffer->pool->alloc,
1036 sizeof(struct anv_push_descriptor_set), 8,
1037 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1038 if (*push_set == NULL) {
1039 anv_batch_set_error(&cmd_buffer->batch, VK_ERROR_OUT_OF_HOST_MEMORY);
1040 return NULL;
1041 }
1042 }
1043
1044 struct anv_descriptor_set *set = &(*push_set)->set;
1045
1046 if (set->layout != layout) {
1047 if (set->layout)
1048 anv_descriptor_set_layout_unref(cmd_buffer->device, set->layout);
1049 anv_descriptor_set_layout_ref(layout);
1050 set->layout = layout;
1051 }
1052 set->size = anv_descriptor_set_layout_size(layout);
1053 set->buffer_view_count = layout->buffer_view_count;
1054 set->buffer_views = (*push_set)->buffer_views;
1055
1056 if (layout->descriptor_buffer_size &&
1057 ((*push_set)->set_used_on_gpu ||
1058 set->desc_mem.alloc_size < layout->descriptor_buffer_size)) {
1059 /* The previous buffer is either actively used by some GPU command (so
1060 * we can't modify it) or is too small. Allocate a new one.
1061 */
1062 struct anv_state desc_mem =
1063 anv_state_stream_alloc(&cmd_buffer->dynamic_state_stream,
1064 layout->descriptor_buffer_size, 32);
1065 if (set->desc_mem.alloc_size) {
1066 /* TODO: Do we really need to copy all the time? */
1067 memcpy(desc_mem.map, set->desc_mem.map,
1068 MIN2(desc_mem.alloc_size, set->desc_mem.alloc_size));
1069 }
1070 set->desc_mem = desc_mem;
1071
1072 struct anv_address addr = {
1073 .bo = cmd_buffer->dynamic_state_stream.state_pool->block_pool.bo,
1074 .offset = set->desc_mem.offset,
1075 };
1076
1077 const struct isl_device *isl_dev = &cmd_buffer->device->isl_dev;
1078 set->desc_surface_state =
1079 anv_state_stream_alloc(&cmd_buffer->surface_state_stream,
1080 isl_dev->ss.size, isl_dev->ss.align);
1081 anv_fill_buffer_surface_state(cmd_buffer->device,
1082 set->desc_surface_state,
1083 ISL_FORMAT_R32G32B32A32_FLOAT,
1084 addr, layout->descriptor_buffer_size, 1);
1085 }
1086
1087 return set;
1088 }
1089
1090 void anv_CmdPushDescriptorSetKHR(
1091 VkCommandBuffer commandBuffer,
1092 VkPipelineBindPoint pipelineBindPoint,
1093 VkPipelineLayout _layout,
1094 uint32_t _set,
1095 uint32_t descriptorWriteCount,
1096 const VkWriteDescriptorSet* pDescriptorWrites)
1097 {
1098 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1099 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1100
1101 assert(_set < MAX_SETS);
1102
1103 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1104
1105 struct anv_descriptor_set *set =
1106 anv_cmd_buffer_push_descriptor_set(cmd_buffer, pipelineBindPoint,
1107 set_layout, _set);
1108 if (!set)
1109 return;
1110
1111 /* Go through the user supplied descriptors. */
1112 for (uint32_t i = 0; i < descriptorWriteCount; i++) {
1113 const VkWriteDescriptorSet *write = &pDescriptorWrites[i];
1114
1115 switch (write->descriptorType) {
1116 case VK_DESCRIPTOR_TYPE_SAMPLER:
1117 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER:
1118 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE:
1119 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE:
1120 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
1121 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1122 anv_descriptor_set_write_image_view(cmd_buffer->device, set,
1123 write->pImageInfo + j,
1124 write->descriptorType,
1125 write->dstBinding,
1126 write->dstArrayElement + j);
1127 }
1128 break;
1129
1130 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER:
1131 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER:
1132 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1133 ANV_FROM_HANDLE(anv_buffer_view, bview,
1134 write->pTexelBufferView[j]);
1135
1136 anv_descriptor_set_write_buffer_view(cmd_buffer->device, set,
1137 write->descriptorType,
1138 bview,
1139 write->dstBinding,
1140 write->dstArrayElement + j);
1141 }
1142 break;
1143
1144 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
1145 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:
1146 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
1147 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
1148 for (uint32_t j = 0; j < write->descriptorCount; j++) {
1149 ANV_FROM_HANDLE(anv_buffer, buffer, write->pBufferInfo[j].buffer);
1150
1151 anv_descriptor_set_write_buffer(cmd_buffer->device, set,
1152 &cmd_buffer->surface_state_stream,
1153 write->descriptorType,
1154 buffer,
1155 write->dstBinding,
1156 write->dstArrayElement + j,
1157 write->pBufferInfo[j].offset,
1158 write->pBufferInfo[j].range);
1159 }
1160 break;
1161
1162 default:
1163 break;
1164 }
1165 }
1166
1167 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, pipelineBindPoint,
1168 layout, _set, set, NULL, NULL);
1169 }
1170
1171 void anv_CmdPushDescriptorSetWithTemplateKHR(
1172 VkCommandBuffer commandBuffer,
1173 VkDescriptorUpdateTemplate descriptorUpdateTemplate,
1174 VkPipelineLayout _layout,
1175 uint32_t _set,
1176 const void* pData)
1177 {
1178 ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
1179 ANV_FROM_HANDLE(anv_descriptor_update_template, template,
1180 descriptorUpdateTemplate);
1181 ANV_FROM_HANDLE(anv_pipeline_layout, layout, _layout);
1182
1183 assert(_set < MAX_PUSH_DESCRIPTORS);
1184
1185 struct anv_descriptor_set_layout *set_layout = layout->set[_set].layout;
1186
1187 struct anv_descriptor_set *set =
1188 anv_cmd_buffer_push_descriptor_set(cmd_buffer, template->bind_point,
1189 set_layout, _set);
1190 if (!set)
1191 return;
1192
1193 anv_descriptor_set_write_template(cmd_buffer->device, set,
1194 &cmd_buffer->surface_state_stream,
1195 template,
1196 pData);
1197
1198 anv_cmd_buffer_bind_descriptor_set(cmd_buffer, template->bind_point,
1199 layout, _set, set, NULL, NULL);
1200 }
1201
1202 void anv_CmdSetDeviceMask(
1203 VkCommandBuffer commandBuffer,
1204 uint32_t deviceMask)
1205 {
1206 /* No-op */
1207 }