0c41ed301d3e59c53b255de21806f28ce2ab92d4
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "util/debug.h"
32
33 #include "vk_format_info.h"
34
35 /**
36 * Exactly one bit must be set in \a aspect.
37 */
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageUsageFlags vk_usage,
40 VkImageAspectFlags aspect)
41 {
42 isl_surf_usage_flags_t isl_usage = 0;
43
44 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
45 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
46
47 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
48 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
49
50 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
51 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
52
53 if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
54 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
55
56 /* Even if we're only using it for transfer operations, clears to depth and
57 * stencil images happen as depth and stencil so they need the right ISL
58 * usage bits or else things will fall apart.
59 */
60 switch (aspect) {
61 case VK_IMAGE_ASPECT_DEPTH_BIT:
62 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
63 break;
64 case VK_IMAGE_ASPECT_STENCIL_BIT:
65 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
66 break;
67 case VK_IMAGE_ASPECT_COLOR_BIT:
68 break;
69 default:
70 unreachable("bad VkImageAspect");
71 }
72
73 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
74 /* blorp implements transfers by sampling from the source image. */
75 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
76 }
77
78 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
79 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
80 /* blorp implements transfers by rendering into the destination image.
81 * Only request this with color images, as we deal with depth/stencil
82 * formats differently. */
83 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
84 }
85
86 return isl_usage;
87 }
88
89 /**
90 * Exactly one bit must be set in \a aspect.
91 */
92 static struct anv_surface *
93 get_surface(struct anv_image *image, VkImageAspectFlags aspect)
94 {
95 switch (aspect) {
96 default:
97 unreachable("bad VkImageAspect");
98 case VK_IMAGE_ASPECT_COLOR_BIT:
99 return &image->color_surface;
100 case VK_IMAGE_ASPECT_DEPTH_BIT:
101 return &image->depth_surface;
102 case VK_IMAGE_ASPECT_STENCIL_BIT:
103 return &image->stencil_surface;
104 }
105 }
106
107 static void
108 add_surface(struct anv_image *image, struct anv_surface *surf)
109 {
110 assert(surf->isl.size > 0); /* isl surface must be initialized */
111
112 surf->offset = align_u32(image->size, surf->isl.alignment);
113 image->size = surf->offset + surf->isl.size;
114 image->alignment = MAX2(image->alignment, surf->isl.alignment);
115 }
116
117 /**
118 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
119 * image's memory requirements (that is, the image's size and alignment).
120 *
121 * Exactly one bit must be set in \a aspect.
122 */
123 static VkResult
124 make_surface(const struct anv_device *dev,
125 struct anv_image *image,
126 const struct anv_image_create_info *anv_info,
127 VkImageAspectFlags aspect)
128 {
129 const VkImageCreateInfo *vk_info = anv_info->vk_info;
130 bool ok UNUSED;
131
132 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
133 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
134 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
135 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
136 };
137
138 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
139 * result with an optionally provided ISL tiling argument.
140 */
141 isl_tiling_flags_t tiling_flags =
142 (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
143 ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
144
145 if (anv_info->isl_tiling_flags)
146 tiling_flags &= anv_info->isl_tiling_flags;
147
148 assert(tiling_flags);
149
150 struct anv_surface *anv_surf = get_surface(image, aspect);
151
152 image->extent = anv_sanitize_image_extent(vk_info->imageType,
153 vk_info->extent);
154
155 enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
156 aspect, vk_info->tiling);
157 assert(format != ISL_FORMAT_UNSUPPORTED);
158
159 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
160 .dim = vk_to_isl_surf_dim[vk_info->imageType],
161 .format = format,
162 .width = image->extent.width,
163 .height = image->extent.height,
164 .depth = image->extent.depth,
165 .levels = vk_info->mipLevels,
166 .array_len = vk_info->arrayLayers,
167 .samples = vk_info->samples,
168 .min_alignment = 0,
169 .min_pitch = anv_info->stride,
170 .usage = choose_isl_surf_usage(image->usage, aspect),
171 .tiling_flags = tiling_flags);
172
173 /* isl_surf_init() will fail only if provided invalid input. Invalid input
174 * is illegal in Vulkan.
175 */
176 assert(ok);
177
178 add_surface(image, anv_surf);
179
180 /* Add a HiZ surface to a depth buffer that will be used for rendering.
181 */
182 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
183 /* We don't advertise that depth buffers could be used as storage
184 * images.
185 */
186 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
187
188 /* Allow the user to control HiZ enabling. Disable by default on gen7
189 * because resolves are not currently implemented pre-BDW.
190 */
191 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
192 /* It will never be used as an attachment, HiZ is pointless. */
193 } else if (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
194 /* From the 1.0.37 spec:
195 *
196 * "An attachment used as an input attachment and depth/stencil
197 * attachment must be in either VK_IMAGE_LAYOUT_GENERAL or
198 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL."
199 *
200 * It will never have a layout of
201 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL, so HiZ is
202 * currently pointless. If transfer operations learn to use the HiZ
203 * buffer, we can enable HiZ for VK_IMAGE_LAYOUT_GENERAL and support
204 * input attachments.
205 */
206 anv_finishme("Implement HiZ for input attachments");
207 } else if (!env_var_as_boolean("INTEL_VK_HIZ", dev->info.gen >= 8)) {
208 anv_finishme("Implement gen7 HiZ");
209 } else if (vk_info->mipLevels > 1) {
210 anv_finishme("Test multi-LOD HiZ");
211 } else if (vk_info->arrayLayers > 1) {
212 anv_finishme("Implement multi-arrayLayer HiZ clears and resolves");
213 } else if (dev->info.gen == 8 && vk_info->samples > 1) {
214 anv_finishme("Test gen8 multisampled HiZ");
215 } else {
216 assert(image->aux_surface.isl.size == 0);
217 ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
218 &image->aux_surface.isl);
219 assert(ok);
220 add_surface(image, &image->aux_surface);
221 image->aux_usage = ISL_AUX_USAGE_HIZ;
222 }
223 } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples == 1) {
224 if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
225 assert(image->aux_surface.isl.size == 0);
226 ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
227 &image->aux_surface.isl);
228 if (ok) {
229 add_surface(image, &image->aux_surface);
230
231 /* For images created without MUTABLE_FORMAT_BIT set, we know that
232 * they will always be used with the original format. In
233 * particular, they will always be used with a format that
234 * supports color compression. If it's never used as a storage
235 * image, then it will only be used through the sampler or the as
236 * a render target. This means that it's safe to just leave
237 * compression on at all times for these formats.
238 */
239 if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
240 !(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
241 isl_format_supports_ccs_e(&dev->info, format)) {
242 image->aux_usage = ISL_AUX_USAGE_CCS_E;
243 }
244 }
245 }
246 } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples > 1) {
247 assert(image->aux_surface.isl.size == 0);
248 assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
249 ok = isl_surf_get_mcs_surf(&dev->isl_dev, &anv_surf->isl,
250 &image->aux_surface.isl);
251 if (ok) {
252 add_surface(image, &image->aux_surface);
253 image->aux_usage = ISL_AUX_USAGE_MCS;
254 }
255 }
256
257 return VK_SUCCESS;
258 }
259
260 VkResult
261 anv_image_create(VkDevice _device,
262 const struct anv_image_create_info *create_info,
263 const VkAllocationCallbacks* alloc,
264 VkImage *pImage)
265 {
266 ANV_FROM_HANDLE(anv_device, device, _device);
267 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
268 struct anv_image *image = NULL;
269 VkResult r;
270
271 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
272
273 anv_assert(pCreateInfo->mipLevels > 0);
274 anv_assert(pCreateInfo->arrayLayers > 0);
275 anv_assert(pCreateInfo->samples > 0);
276 anv_assert(pCreateInfo->extent.width > 0);
277 anv_assert(pCreateInfo->extent.height > 0);
278 anv_assert(pCreateInfo->extent.depth > 0);
279
280 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
281 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
282 if (!image)
283 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
284
285 memset(image, 0, sizeof(*image));
286 image->type = pCreateInfo->imageType;
287 image->extent = pCreateInfo->extent;
288 image->vk_format = pCreateInfo->format;
289 image->aspects = vk_format_aspects(image->vk_format);
290 image->levels = pCreateInfo->mipLevels;
291 image->array_size = pCreateInfo->arrayLayers;
292 image->samples = pCreateInfo->samples;
293 image->usage = pCreateInfo->usage;
294 image->tiling = pCreateInfo->tiling;
295 image->aux_usage = ISL_AUX_USAGE_NONE;
296
297 uint32_t b;
298 for_each_bit(b, image->aspects) {
299 r = make_surface(device, image, create_info, (1 << b));
300 if (r != VK_SUCCESS)
301 goto fail;
302 }
303
304 *pImage = anv_image_to_handle(image);
305
306 return VK_SUCCESS;
307
308 fail:
309 if (image)
310 vk_free2(&device->alloc, alloc, image);
311
312 return r;
313 }
314
315 VkResult
316 anv_CreateImage(VkDevice device,
317 const VkImageCreateInfo *pCreateInfo,
318 const VkAllocationCallbacks *pAllocator,
319 VkImage *pImage)
320 {
321 return anv_image_create(device,
322 &(struct anv_image_create_info) {
323 .vk_info = pCreateInfo,
324 },
325 pAllocator,
326 pImage);
327 }
328
329 void
330 anv_DestroyImage(VkDevice _device, VkImage _image,
331 const VkAllocationCallbacks *pAllocator)
332 {
333 ANV_FROM_HANDLE(anv_device, device, _device);
334 ANV_FROM_HANDLE(anv_image, image, _image);
335
336 if (!image)
337 return;
338
339 vk_free2(&device->alloc, pAllocator, image);
340 }
341
342 VkResult anv_BindImageMemory(
343 VkDevice _device,
344 VkImage _image,
345 VkDeviceMemory _memory,
346 VkDeviceSize memoryOffset)
347 {
348 ANV_FROM_HANDLE(anv_device, device, _device);
349 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
350 ANV_FROM_HANDLE(anv_image, image, _image);
351
352 if (mem) {
353 image->bo = &mem->bo;
354 image->offset = memoryOffset;
355 } else {
356 image->bo = NULL;
357 image->offset = 0;
358 }
359
360 if (image->aux_surface.isl.size > 0) {
361
362 /* The offset and size must be a multiple of 4K or else the
363 * anv_gem_mmap call below will return NULL.
364 */
365 assert((image->offset + image->aux_surface.offset) % 4096 == 0);
366 assert(image->aux_surface.isl.size % 4096 == 0);
367
368 /* Auxiliary surfaces need to have their memory cleared to 0 before they
369 * can be used. For CCS surfaces, this puts them in the "resolved"
370 * state so they can be used with CCS enabled before we ever touch it
371 * from the GPU. For HiZ, we need something valid or else we may get
372 * GPU hangs on some hardware and 0 works fine.
373 */
374 void *map = anv_gem_mmap(device, image->bo->gem_handle,
375 image->offset + image->aux_surface.offset,
376 image->aux_surface.isl.size,
377 device->info.has_llc ? 0 : I915_MMAP_WC);
378
379 /* If anv_gem_mmap returns NULL, it's likely that the kernel was
380 * not able to find space on the host to create a proper mapping.
381 */
382 if (map == NULL)
383 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
384
385 memset(map, 0, image->aux_surface.isl.size);
386
387 anv_gem_munmap(map, image->aux_surface.isl.size);
388 }
389
390 return VK_SUCCESS;
391 }
392
393 static void
394 anv_surface_get_subresource_layout(struct anv_image *image,
395 struct anv_surface *surface,
396 const VkImageSubresource *subresource,
397 VkSubresourceLayout *layout)
398 {
399 /* If we are on a non-zero mip level or array slice, we need to
400 * calculate a real offset.
401 */
402 anv_assert(subresource->mipLevel == 0);
403 anv_assert(subresource->arrayLayer == 0);
404
405 layout->offset = surface->offset;
406 layout->rowPitch = surface->isl.row_pitch;
407 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
408 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
409 layout->size = surface->isl.size;
410 }
411
412 void anv_GetImageSubresourceLayout(
413 VkDevice device,
414 VkImage _image,
415 const VkImageSubresource* pSubresource,
416 VkSubresourceLayout* pLayout)
417 {
418 ANV_FROM_HANDLE(anv_image, image, _image);
419
420 assert(__builtin_popcount(pSubresource->aspectMask) == 1);
421
422 switch (pSubresource->aspectMask) {
423 case VK_IMAGE_ASPECT_COLOR_BIT:
424 anv_surface_get_subresource_layout(image, &image->color_surface,
425 pSubresource, pLayout);
426 break;
427 case VK_IMAGE_ASPECT_DEPTH_BIT:
428 anv_surface_get_subresource_layout(image, &image->depth_surface,
429 pSubresource, pLayout);
430 break;
431 case VK_IMAGE_ASPECT_STENCIL_BIT:
432 anv_surface_get_subresource_layout(image, &image->stencil_surface,
433 pSubresource, pLayout);
434 break;
435 default:
436 assert(!"Invalid image aspect");
437 }
438 }
439
440 /**
441 * This function determines the optimal buffer to use for device
442 * accesses given a VkImageLayout and other pieces of information needed to
443 * make that determination. This does not determine the optimal buffer to
444 * use during a resolve operation.
445 *
446 * NOTE: Some layouts do not support device access.
447 *
448 * @param devinfo The device information of the Intel GPU.
449 * @param image The image that may contain a collection of buffers.
450 * @param aspects The aspect(s) of the image to be accessed.
451 * @param layout The current layout of the image aspect(s).
452 *
453 * @return The primary buffer that should be used for the given layout.
454 */
455 enum isl_aux_usage
456 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
457 const struct anv_image * const image,
458 const VkImageAspectFlags aspects,
459 const VkImageLayout layout)
460 {
461 /* Validate the inputs. */
462
463 /* The devinfo is needed as the optimal buffer varies across generations. */
464 assert(devinfo != NULL);
465
466 /* The layout of a NULL image is not properly defined. */
467 assert(image != NULL);
468
469 /* The aspects must be a subset of the image aspects. */
470 assert(aspects & image->aspects && aspects <= image->aspects);
471
472 /* Determine the optimal buffer. */
473
474 /* If there is no auxiliary surface allocated, we must use the one and only
475 * main buffer.
476 */
477 if (image->aux_surface.isl.size == 0)
478 return ISL_AUX_USAGE_NONE;
479
480 /* All images that use an auxiliary surface are required to be tiled. */
481 assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
482
483 /* On BDW+, when clearing the stencil aspect of a depth stencil image,
484 * the HiZ buffer allows us to record the clear with a relatively small
485 * number of packets. Prior to BDW, the HiZ buffer provides no known benefit
486 * to the stencil aspect.
487 */
488 if (devinfo->gen < 8 && aspects == VK_IMAGE_ASPECT_STENCIL_BIT)
489 return ISL_AUX_USAGE_NONE;
490
491 const bool color_aspect = aspects == VK_IMAGE_ASPECT_COLOR_BIT;
492
493 /* The following switch currently only handles depth stencil aspects.
494 * TODO: Handle the color aspect.
495 */
496 if (color_aspect)
497 return image->aux_usage;
498
499 switch (layout) {
500
501 /* Invalid Layouts */
502
503 /* According to the Vulkan Spec, the following layouts are valid only as
504 * initial layouts in a layout transition and don't support device access.
505 */
506 case VK_IMAGE_LAYOUT_UNDEFINED:
507 case VK_IMAGE_LAYOUT_PREINITIALIZED:
508 case VK_IMAGE_LAYOUT_RANGE_SIZE:
509 case VK_IMAGE_LAYOUT_MAX_ENUM:
510 unreachable("Invalid image layout for device access.");
511
512
513 /* Transfer Layouts
514 *
515 * This buffer could be a depth buffer used in a transfer operation. BLORP
516 * currently doesn't use HiZ for transfer operations so we must use the main
517 * buffer for this layout. TODO: Enable HiZ in BLORP.
518 */
519 case VK_IMAGE_LAYOUT_GENERAL:
520 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
521 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
522 return ISL_AUX_USAGE_NONE;
523
524
525 /* Sampling Layouts */
526 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
527 assert(!color_aspect);
528 /* Fall-through */
529 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
530 if (anv_can_sample_with_hiz(devinfo, aspects, image->samples))
531 return ISL_AUX_USAGE_HIZ;
532 else
533 return ISL_AUX_USAGE_NONE;
534
535 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
536 assert(color_aspect);
537
538 /* On SKL+, the render buffer can be decompressed by the presentation
539 * engine. Support for this feature has not yet landed in the wider
540 * ecosystem. TODO: Update this code when support lands.
541 *
542 * From the BDW PRM, Vol 7, Render Target Resolve:
543 *
544 * If the MCS is enabled on a non-multisampled render target, the
545 * render target must be resolved before being used for other
546 * purposes (display, texture, CPU lock) The clear value from
547 * SURFACE_STATE is written into pixels in the render target
548 * indicated as clear in the MCS.
549 *
550 * Pre-SKL, the render buffer must be resolved before being used for
551 * presentation. We can infer that the auxiliary buffer is not used.
552 */
553 return ISL_AUX_USAGE_NONE;
554
555
556 /* Rendering Layouts */
557 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
558 assert(color_aspect);
559 unreachable("Color images are not yet supported.");
560
561 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
562 assert(!color_aspect);
563 return ISL_AUX_USAGE_HIZ;
564 }
565
566 /* If the layout isn't recognized in the exhaustive switch above, the
567 * VkImageLayout value is not defined in vulkan.h.
568 */
569 unreachable("layout is not a VkImageLayout enumeration member.");
570 }
571
572
573 static struct anv_state
574 alloc_surface_state(struct anv_device *device)
575 {
576 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
577 }
578
579 static enum isl_channel_select
580 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
581 struct isl_swizzle format_swizzle)
582 {
583 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
584 swizzle = component;
585
586 switch (swizzle) {
587 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
588 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
589 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
590 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
591 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
592 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
593 default:
594 unreachable("Invalid swizzle");
595 }
596 }
597
598
599 VkResult
600 anv_CreateImageView(VkDevice _device,
601 const VkImageViewCreateInfo *pCreateInfo,
602 const VkAllocationCallbacks *pAllocator,
603 VkImageView *pView)
604 {
605 ANV_FROM_HANDLE(anv_device, device, _device);
606 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
607 struct anv_image_view *iview;
608
609 iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
610 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
611 if (iview == NULL)
612 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
613
614 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
615
616 assert(range->layerCount > 0);
617 assert(range->baseMipLevel < image->levels);
618 assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
619 VK_IMAGE_USAGE_STORAGE_BIT |
620 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
621 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
622
623 switch (image->type) {
624 default:
625 unreachable("bad VkImageType");
626 case VK_IMAGE_TYPE_1D:
627 case VK_IMAGE_TYPE_2D:
628 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
629 break;
630 case VK_IMAGE_TYPE_3D:
631 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
632 <= anv_minify(image->extent.depth, range->baseMipLevel));
633 break;
634 }
635
636 const struct anv_surface *surface =
637 anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
638
639 iview->image = image;
640 iview->bo = image->bo;
641 iview->offset = image->offset + surface->offset;
642
643 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
644 iview->vk_format = pCreateInfo->format;
645
646 struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
647 range->aspectMask, image->tiling);
648
649 iview->isl = (struct isl_view) {
650 .format = format.isl_format,
651 .base_level = range->baseMipLevel,
652 .levels = anv_get_levelCount(image, range),
653 .base_array_layer = range->baseArrayLayer,
654 .array_len = anv_get_layerCount(image, range),
655 .swizzle = {
656 .r = remap_swizzle(pCreateInfo->components.r,
657 VK_COMPONENT_SWIZZLE_R, format.swizzle),
658 .g = remap_swizzle(pCreateInfo->components.g,
659 VK_COMPONENT_SWIZZLE_G, format.swizzle),
660 .b = remap_swizzle(pCreateInfo->components.b,
661 VK_COMPONENT_SWIZZLE_B, format.swizzle),
662 .a = remap_swizzle(pCreateInfo->components.a,
663 VK_COMPONENT_SWIZZLE_A, format.swizzle),
664 },
665 };
666
667 iview->extent = (VkExtent3D) {
668 .width = anv_minify(image->extent.width , range->baseMipLevel),
669 .height = anv_minify(image->extent.height, range->baseMipLevel),
670 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
671 };
672
673 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
674 iview->isl.base_array_layer = 0;
675 iview->isl.array_len = iview->extent.depth;
676 }
677
678 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
679 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
680 iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
681 } else {
682 iview->isl.usage = 0;
683 }
684
685 /* If the HiZ buffer can be sampled from, set the constant clear color.
686 * If it cannot, disable the isl aux usage flag.
687 */
688 float red_clear_color = 0.0f;
689 enum isl_aux_usage surf_usage = image->aux_usage;
690 if (image->aux_usage == ISL_AUX_USAGE_HIZ) {
691 if (anv_can_sample_with_hiz(&device->info, iview->aspect_mask,
692 image->samples)) {
693 /* When a HiZ buffer is sampled on gen9+, ensure that
694 * the constant fast clear value is set in the surface state.
695 */
696 if (device->info.gen >= 9)
697 red_clear_color = ANV_HZ_FC_VAL;
698 } else {
699 surf_usage = ISL_AUX_USAGE_NONE;
700 }
701 }
702
703 /* Input attachment surfaces for color are allocated and filled
704 * out at BeginRenderPass time because they need compression information.
705 * Compression is not yet enabled for depth textures and stencil doesn't
706 * allow compression so we can just use the texture surface state from the
707 * view.
708 */
709 if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
710 (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
711 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
712 iview->sampler_surface_state = alloc_surface_state(device);
713
714 struct isl_view view = iview->isl;
715 view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
716 isl_surf_fill_state(&device->isl_dev,
717 iview->sampler_surface_state.map,
718 .surf = &surface->isl,
719 .view = &view,
720 .clear_color.f32 = { red_clear_color,},
721 .aux_surf = &image->aux_surface.isl,
722 .aux_usage = surf_usage,
723 .mocs = device->default_mocs);
724
725 anv_state_flush(device, iview->sampler_surface_state);
726 } else {
727 iview->sampler_surface_state.alloc_size = 0;
728 }
729
730 /* NOTE: This one needs to go last since it may stomp isl_view.format */
731 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
732 iview->storage_surface_state = alloc_surface_state(device);
733 iview->writeonly_storage_surface_state = alloc_surface_state(device);
734
735 struct isl_view view = iview->isl;
736 view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
737
738 /* Write-only accesses always used a typed write instruction and should
739 * therefore use the real format.
740 */
741 isl_surf_fill_state(&device->isl_dev,
742 iview->writeonly_storage_surface_state.map,
743 .surf = &surface->isl,
744 .view = &view,
745 .aux_surf = &image->aux_surface.isl,
746 .aux_usage = image->aux_usage,
747 .mocs = device->default_mocs);
748
749 if (isl_has_matching_typed_storage_image_format(&device->info,
750 format.isl_format)) {
751 /* Typed surface reads support a very limited subset of the shader
752 * image formats. Translate it into the closest format the hardware
753 * supports.
754 */
755 view.format = isl_lower_storage_image_format(&device->info,
756 format.isl_format);
757
758 isl_surf_fill_state(&device->isl_dev,
759 iview->storage_surface_state.map,
760 .surf = &surface->isl,
761 .view = &view,
762 .aux_surf = &image->aux_surface.isl,
763 .aux_usage = image->aux_usage,
764 .mocs = device->default_mocs);
765 } else {
766 anv_fill_buffer_surface_state(device, iview->storage_surface_state,
767 ISL_FORMAT_RAW,
768 iview->offset,
769 iview->bo->size - iview->offset, 1);
770 }
771
772 isl_surf_fill_image_param(&device->isl_dev,
773 &iview->storage_image_param,
774 &surface->isl, &iview->isl);
775
776 anv_state_flush(device, iview->storage_surface_state);
777 anv_state_flush(device, iview->writeonly_storage_surface_state);
778 } else {
779 iview->storage_surface_state.alloc_size = 0;
780 iview->writeonly_storage_surface_state.alloc_size = 0;
781 }
782
783 *pView = anv_image_view_to_handle(iview);
784
785 return VK_SUCCESS;
786 }
787
788 void
789 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
790 const VkAllocationCallbacks *pAllocator)
791 {
792 ANV_FROM_HANDLE(anv_device, device, _device);
793 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
794
795 if (!iview)
796 return;
797
798 if (iview->sampler_surface_state.alloc_size > 0) {
799 anv_state_pool_free(&device->surface_state_pool,
800 iview->sampler_surface_state);
801 }
802
803 if (iview->storage_surface_state.alloc_size > 0) {
804 anv_state_pool_free(&device->surface_state_pool,
805 iview->storage_surface_state);
806 }
807
808 if (iview->writeonly_storage_surface_state.alloc_size > 0) {
809 anv_state_pool_free(&device->surface_state_pool,
810 iview->writeonly_storage_surface_state);
811 }
812
813 vk_free2(&device->alloc, pAllocator, iview);
814 }
815
816
817 VkResult
818 anv_CreateBufferView(VkDevice _device,
819 const VkBufferViewCreateInfo *pCreateInfo,
820 const VkAllocationCallbacks *pAllocator,
821 VkBufferView *pView)
822 {
823 ANV_FROM_HANDLE(anv_device, device, _device);
824 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
825 struct anv_buffer_view *view;
826
827 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
828 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
829 if (!view)
830 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
831
832 /* TODO: Handle the format swizzle? */
833
834 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
835 VK_IMAGE_ASPECT_COLOR_BIT,
836 VK_IMAGE_TILING_LINEAR);
837 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
838 view->bo = buffer->bo;
839 view->offset = buffer->offset + pCreateInfo->offset;
840 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
841 buffer->size - pCreateInfo->offset : pCreateInfo->range;
842 view->range = align_down_npot_u32(view->range, format_bs);
843
844 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
845 view->surface_state = alloc_surface_state(device);
846
847 anv_fill_buffer_surface_state(device, view->surface_state,
848 view->format,
849 view->offset, view->range, format_bs);
850 } else {
851 view->surface_state = (struct anv_state){ 0 };
852 }
853
854 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
855 view->storage_surface_state = alloc_surface_state(device);
856 view->writeonly_storage_surface_state = alloc_surface_state(device);
857
858 enum isl_format storage_format =
859 isl_has_matching_typed_storage_image_format(&device->info,
860 view->format) ?
861 isl_lower_storage_image_format(&device->info, view->format) :
862 ISL_FORMAT_RAW;
863
864 anv_fill_buffer_surface_state(device, view->storage_surface_state,
865 storage_format,
866 view->offset, view->range,
867 (storage_format == ISL_FORMAT_RAW ? 1 :
868 isl_format_get_layout(storage_format)->bpb / 8));
869
870 /* Write-only accesses should use the original format. */
871 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
872 view->format,
873 view->offset, view->range,
874 isl_format_get_layout(view->format)->bpb / 8);
875
876 isl_buffer_fill_image_param(&device->isl_dev,
877 &view->storage_image_param,
878 view->format, view->range);
879 } else {
880 view->storage_surface_state = (struct anv_state){ 0 };
881 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
882 }
883
884 *pView = anv_buffer_view_to_handle(view);
885
886 return VK_SUCCESS;
887 }
888
889 void
890 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
891 const VkAllocationCallbacks *pAllocator)
892 {
893 ANV_FROM_HANDLE(anv_device, device, _device);
894 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
895
896 if (!view)
897 return;
898
899 if (view->surface_state.alloc_size > 0)
900 anv_state_pool_free(&device->surface_state_pool,
901 view->surface_state);
902
903 if (view->storage_surface_state.alloc_size > 0)
904 anv_state_pool_free(&device->surface_state_pool,
905 view->storage_surface_state);
906
907 if (view->writeonly_storage_surface_state.alloc_size > 0)
908 anv_state_pool_free(&device->surface_state_pool,
909 view->writeonly_storage_surface_state);
910
911 vk_free2(&device->alloc, pAllocator, view);
912 }
913
914 const struct anv_surface *
915 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
916 VkImageAspectFlags aspect_mask)
917 {
918 switch (aspect_mask) {
919 case VK_IMAGE_ASPECT_COLOR_BIT:
920 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
921 return &image->color_surface;
922 case VK_IMAGE_ASPECT_DEPTH_BIT:
923 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
924 return &image->depth_surface;
925 case VK_IMAGE_ASPECT_STENCIL_BIT:
926 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
927 return &image->stencil_surface;
928 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
929 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
930 * combined depth stencil formats. Specifically, it states:
931 *
932 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
933 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
934 *
935 * Image views with both depth and stencil aspects are only valid for
936 * render target attachments, in which case
937 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
938 * stencil surfaces from the underlying surface.
939 */
940 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
941 return &image->depth_surface;
942 } else {
943 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
944 return &image->stencil_surface;
945 }
946 default:
947 unreachable("image does not have aspect");
948 return NULL;
949 }
950 }