2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
96 const struct isl_drm_modifier_info
*isl_mod_info
)
98 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
99 isl_tiling_flags_t flags
= 0;
101 switch (base_info
->tiling
) {
103 unreachable("bad VkImageTiling");
104 case VK_IMAGE_TILING_OPTIMAL
:
105 flags
= ISL_TILING_ANY_MASK
;
107 case VK_IMAGE_TILING_LINEAR
:
108 flags
= ISL_TILING_LINEAR_BIT
;
112 if (anv_info
->isl_tiling_flags
)
113 flags
&= anv_info
->isl_tiling_flags
;
116 flags
&= 1 << isl_mod_info
->tiling
;
123 static struct anv_surface
*
124 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
126 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
127 return &image
->planes
[plane
].surface
;
131 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
133 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
135 if (image
->disjoint
) {
136 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
137 /* Plane offset is always 0 when it's disjoint. */
139 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
140 /* Determine plane's offset only once when the first surface is added. */
141 if (image
->planes
[plane
].size
== 0)
142 image
->planes
[plane
].offset
= image
->size
;
145 image
->size
= surf
->offset
+ surf
->isl
.size
;
146 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
148 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
149 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
150 surf
->isl
.alignment
);
155 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
156 const struct VkImageCreateInfo
*vk_info
)
158 enum isl_format format
=
159 anv_get_isl_format(devinfo
, vk_info
->format
,
160 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
162 if (!isl_format_supports_ccs_e(devinfo
, format
))
165 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
168 const VkImageFormatListCreateInfoKHR
*fmt_list
=
169 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
171 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
174 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
175 enum isl_format view_format
=
176 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
177 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
179 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
187 * For color images that have an auxiliary surface, request allocation for an
188 * additional buffer that mainly stores fast-clear values. Use of this buffer
189 * allows us to access the image's subresources while being aware of their
190 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
191 * which a fast clear has occurred).
193 * For the purpose of discoverability, the algorithm used to manage this buffer
194 * is described here. A clear value in this buffer is updated when a fast clear
195 * is performed on a subresource. One of two synchronization operations is
196 * performed in order for a following memory access to use the fast-clear
198 * a. Copy the value from the buffer to the surface state object used for
199 * reading. This is done implicitly when the value is the clear value
200 * predetermined to be the default in other surface state objects. This
201 * is currently only done explicitly for the operation below.
202 * b. Do (a) and use the surface state object to resolve the subresource.
203 * This is only done during layout transitions for decent performance.
205 * With the above scheme, we can fast-clear whenever the hardware allows except
206 * for two cases in which synchronization becomes impossible or undesirable:
207 * * The subresource is in the GENERAL layout and is cleared to a value
208 * other than the special default value.
210 * Performing a synchronization operation in order to read from the
211 * subresource is undesirable in this case. Firstly, b) is not an option
212 * because a layout transition isn't required between a write and read of
213 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
214 * explicitly because it would require large infrastructural changes. The
215 * Vulkan API supports us in deciding not to optimize this layout by
216 * stating that using this layout may cause suboptimal performance. NOTE:
217 * the auxiliary buffer must always be enabled to support a) implicitly.
220 * * For the given miplevel, only some of the layers are cleared at once.
222 * If the user clears each layer to a different value, then tries to
223 * render to multiple layers at once, we have no ability to perform a
224 * synchronization operation in between. a) is not helpful because the
225 * object can only hold one clear value. b) is not an option because a
226 * layout transition isn't required in this case.
229 add_fast_clear_state_buffer(struct anv_image
*image
,
230 VkImageAspectFlagBits aspect
,
232 const struct anv_device
*device
)
234 assert(image
&& device
);
235 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
236 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
238 /* Compressed images must be tiled and therefore everything should be 4K
239 * aligned. The CCS has the same alignment requirements. This is good
240 * because we need at least dword-alignment for MI_LOAD/STORE operations.
242 assert(image
->alignment
% 4 == 0);
243 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
245 /* This buffer should be at the very end of the plane. */
246 if (image
->disjoint
) {
247 assert(image
->planes
[plane
].size
==
248 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
250 assert(image
->size
==
251 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
254 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
255 /* There's no padding between entries, so ensure that they're always a
256 * multiple of 32 bits in order to enable GPU memcpy operations.
258 assert(entry_size
% 4 == 0);
260 const unsigned plane_state_size
=
261 entry_size
* anv_image_aux_levels(image
, aspect
);
263 image
->planes
[plane
].fast_clear_state_offset
=
264 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
266 image
->planes
[plane
].size
+= plane_state_size
;
267 image
->size
+= plane_state_size
;
271 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
272 * image's memory requirements (that is, the image's size and alignment).
275 make_surface(const struct anv_device
*dev
,
276 struct anv_image
*image
,
277 const struct anv_image_create_info
*anv_info
,
278 isl_tiling_flags_t tiling_flags
,
279 VkImageAspectFlagBits aspect
)
281 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
284 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
285 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
286 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
287 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
290 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
293 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
294 const struct anv_format_plane plane_format
=
295 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
296 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
298 const isl_surf_usage_flags_t usage
=
299 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
300 anv_info
->isl_extra_usage_flags
, aspect
);
302 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
303 * fall back to linear on Broadwell and earlier because we aren't
304 * guaranteed that we can handle offsets correctly. On Sky Lake, the
305 * horizontal and vertical alignments are sufficiently high that we can
306 * just use RENDER_SURFACE_STATE::X/Y Offset.
308 bool needs_shadow
= false;
309 if (dev
->info
.gen
<= 8 &&
310 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
311 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
312 assert(isl_format_is_compressed(plane_format
.isl_format
));
313 tiling_flags
= ISL_TILING_LINEAR_BIT
;
317 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
318 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
319 .format
= plane_format
.isl_format
,
320 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
321 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
322 .depth
= image
->extent
.depth
,
323 .levels
= vk_info
->mipLevels
,
324 .array_len
= vk_info
->arrayLayers
,
325 .samples
= vk_info
->samples
,
327 .row_pitch
= anv_info
->stride
,
329 .tiling_flags
= tiling_flags
);
332 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
334 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
336 add_surface(image
, anv_surf
, plane
);
338 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
339 * create an identical tiled shadow surface for use while texturing so we
340 * don't get garbage performance.
343 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
344 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
346 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
347 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
348 .format
= plane_format
.isl_format
,
349 .width
= image
->extent
.width
,
350 .height
= image
->extent
.height
,
351 .depth
= image
->extent
.depth
,
352 .levels
= vk_info
->mipLevels
,
353 .array_len
= vk_info
->arrayLayers
,
354 .samples
= vk_info
->samples
,
356 .row_pitch
= anv_info
->stride
,
358 .tiling_flags
= ISL_TILING_ANY_MASK
);
360 /* isl_surf_init() will fail only if provided invalid input. Invalid input
361 * is illegal in Vulkan.
365 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
368 /* Add a HiZ surface to a depth buffer that will be used for rendering.
370 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
371 /* We don't advertise that depth buffers could be used as storage
374 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
376 /* Allow the user to control HiZ enabling. Disable by default on gen7
377 * because resolves are not currently implemented pre-BDW.
379 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
380 /* It will never be used as an attachment, HiZ is pointless. */
381 } else if (dev
->info
.gen
== 7) {
382 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
383 } else if (vk_info
->mipLevels
> 1) {
384 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
385 } else if (vk_info
->arrayLayers
> 1) {
386 anv_perf_warn(dev
->instance
, image
,
387 "Implement multi-arrayLayer HiZ clears and resolves");
388 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
389 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
390 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
391 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
392 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
393 &image
->planes
[plane
].surface
.isl
,
394 &image
->planes
[plane
].aux_surface
.isl
);
396 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
397 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
399 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
400 /* TODO: Disallow compression with :
402 * 1) non multiplanar images (We appear to hit a sampler bug with
403 * CCS & R16G16 format. Putting the clear state a page/4096bytes
404 * further fixes the issue).
406 * 2) alias images, because they might be aliases of images
409 * 3) compression disabled by debug
411 const bool allow_compression
=
412 image
->n_planes
== 1 &&
413 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
414 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
416 if (allow_compression
) {
417 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
418 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
419 &image
->planes
[plane
].surface
.isl
,
420 &image
->planes
[plane
].aux_surface
.isl
, 0);
423 /* Disable CCS when it is not useful (i.e., when you can't render
424 * to the image with CCS enabled).
426 if (!isl_format_supports_rendering(&dev
->info
,
427 plane_format
.isl_format
)) {
428 /* While it may be technically possible to enable CCS for this
429 * image, we currently don't have things hooked up to get it
432 anv_perf_warn(dev
->instance
, image
,
433 "This image format doesn't support rendering. "
434 "Not allocating an CCS buffer.");
435 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
439 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
440 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
442 /* For images created without MUTABLE_FORMAT_BIT set, we know that
443 * they will always be used with the original format. In
444 * particular, they will always be used with a format that
445 * supports color compression. If it's never used as a storage
446 * image, then it will only be used through the sampler or the as
447 * a render target. This means that it's safe to just leave
448 * compression on at all times for these formats.
450 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
451 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
452 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
456 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
457 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
458 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
459 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
460 &image
->planes
[plane
].surface
.isl
,
461 &image
->planes
[plane
].aux_surface
.isl
);
463 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
464 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
465 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
469 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
471 /* Upper bound of the last surface should be smaller than the plane's
474 assert((MAX2(image
->planes
[plane
].surface
.offset
,
475 image
->planes
[plane
].aux_surface
.offset
) +
476 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
477 image
->planes
[plane
].aux_surface
.isl
.size
:
478 image
->planes
[plane
].surface
.isl
.size
)) <=
479 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
481 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
482 /* assert(image->planes[plane].fast_clear_state_offset == */
483 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
484 assert(image
->planes
[plane
].fast_clear_state_offset
<
485 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
491 static const struct isl_drm_modifier_info
*
492 get_legacy_scanout_drm_format_mod(VkImageTiling tiling
)
495 case VK_IMAGE_TILING_OPTIMAL
:
496 return isl_drm_modifier_get_info(I915_FORMAT_MOD_X_TILED
);
497 case VK_IMAGE_TILING_LINEAR
:
498 return isl_drm_modifier_get_info(DRM_FORMAT_MOD_LINEAR
);
500 unreachable("bad VkImageTiling");
505 anv_image_create(VkDevice _device
,
506 const struct anv_image_create_info
*create_info
,
507 const VkAllocationCallbacks
* alloc
,
510 ANV_FROM_HANDLE(anv_device
, device
, _device
);
511 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
512 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
513 struct anv_image
*image
= NULL
;
516 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
518 const struct wsi_image_create_info
*wsi_info
=
519 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
520 if (wsi_info
&& wsi_info
->scanout
)
521 isl_mod_info
= get_legacy_scanout_drm_format_mod(pCreateInfo
->tiling
);
523 anv_assert(pCreateInfo
->mipLevels
> 0);
524 anv_assert(pCreateInfo
->arrayLayers
> 0);
525 anv_assert(pCreateInfo
->samples
> 0);
526 anv_assert(pCreateInfo
->extent
.width
> 0);
527 anv_assert(pCreateInfo
->extent
.height
> 0);
528 anv_assert(pCreateInfo
->extent
.depth
> 0);
530 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
531 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
533 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
535 image
->type
= pCreateInfo
->imageType
;
536 image
->extent
= pCreateInfo
->extent
;
537 image
->vk_format
= pCreateInfo
->format
;
538 image
->format
= anv_get_format(pCreateInfo
->format
);
539 image
->aspects
= vk_format_aspects(image
->vk_format
);
540 image
->levels
= pCreateInfo
->mipLevels
;
541 image
->array_size
= pCreateInfo
->arrayLayers
;
542 image
->samples
= pCreateInfo
->samples
;
543 image
->usage
= pCreateInfo
->usage
;
544 image
->tiling
= pCreateInfo
->tiling
;
545 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
546 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
547 DRM_FORMAT_MOD_INVALID
;
549 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
550 assert(format
!= NULL
);
552 const isl_tiling_flags_t isl_tiling_flags
=
553 choose_isl_tiling_flags(create_info
, isl_mod_info
);
555 image
->n_planes
= format
->n_planes
;
558 for_each_bit(b
, image
->aspects
) {
559 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
565 *pImage
= anv_image_to_handle(image
);
571 vk_free2(&device
->alloc
, alloc
, image
);
577 anv_CreateImage(VkDevice device
,
578 const VkImageCreateInfo
*pCreateInfo
,
579 const VkAllocationCallbacks
*pAllocator
,
583 const VkNativeBufferANDROID
*gralloc_info
=
584 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
587 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
591 return anv_image_create(device
,
592 &(struct anv_image_create_info
) {
593 .vk_info
= pCreateInfo
,
600 anv_DestroyImage(VkDevice _device
, VkImage _image
,
601 const VkAllocationCallbacks
*pAllocator
)
603 ANV_FROM_HANDLE(anv_device
, device
, _device
);
604 ANV_FROM_HANDLE(anv_image
, image
, _image
);
609 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
610 if (image
->planes
[p
].bo_is_owned
) {
611 assert(image
->planes
[p
].bo
!= NULL
);
612 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
616 vk_free2(&device
->alloc
, pAllocator
, image
);
619 static void anv_image_bind_memory_plane(struct anv_device
*device
,
620 struct anv_image
*image
,
622 struct anv_device_memory
*memory
,
623 uint32_t memory_offset
)
625 assert(!image
->planes
[plane
].bo_is_owned
);
628 image
->planes
[plane
].bo
= NULL
;
629 image
->planes
[plane
].bo_offset
= 0;
633 image
->planes
[plane
].bo
= memory
->bo
;
634 image
->planes
[plane
].bo_offset
= memory_offset
;
637 VkResult
anv_BindImageMemory(
640 VkDeviceMemory _memory
,
641 VkDeviceSize memoryOffset
)
643 ANV_FROM_HANDLE(anv_device
, device
, _device
);
644 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
645 ANV_FROM_HANDLE(anv_image
, image
, _image
);
648 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
650 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
651 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
657 VkResult
anv_BindImageMemory2KHR(
659 uint32_t bindInfoCount
,
660 const VkBindImageMemoryInfoKHR
* pBindInfos
)
662 ANV_FROM_HANDLE(anv_device
, device
, _device
);
664 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
665 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
666 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
667 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
668 VkImageAspectFlags aspects
= image
->aspects
;
670 vk_foreach_struct_const(s
, bind_info
->pNext
) {
672 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
673 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
674 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
676 aspects
= plane_info
->planeAspect
;
680 anv_debug_ignored_stype(s
->sType
);
686 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
688 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
689 anv_image_bind_memory_plane(device
, image
, plane
,
690 mem
, bind_info
->memoryOffset
);
697 void anv_GetImageSubresourceLayout(
700 const VkImageSubresource
* subresource
,
701 VkSubresourceLayout
* layout
)
703 ANV_FROM_HANDLE(anv_image
, image
, _image
);
704 const struct anv_surface
*surface
=
705 get_surface(image
, subresource
->aspectMask
);
707 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
709 /* If we are on a non-zero mip level or array slice, we need to
710 * calculate a real offset.
712 anv_assert(subresource
->mipLevel
== 0);
713 anv_assert(subresource
->arrayLayer
== 0);
715 layout
->offset
= surface
->offset
;
716 layout
->rowPitch
= surface
->isl
.row_pitch
;
717 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
718 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
719 layout
->size
= surface
->isl
.size
;
723 * This function determines the optimal buffer to use for a given
724 * VkImageLayout and other pieces of information needed to make that
725 * determination. This does not determine the optimal buffer to use
726 * during a resolve operation.
728 * @param devinfo The device information of the Intel GPU.
729 * @param image The image that may contain a collection of buffers.
730 * @param aspect The aspect of the image to be accessed.
731 * @param layout The current layout of the image aspect(s).
733 * @return The primary buffer that should be used for the given layout.
736 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
737 const struct anv_image
* const image
,
738 const VkImageAspectFlagBits aspect
,
739 const VkImageLayout layout
)
741 /* Validate the inputs. */
743 /* The devinfo is needed as the optimal buffer varies across generations. */
744 assert(devinfo
!= NULL
);
746 /* The layout of a NULL image is not properly defined. */
747 assert(image
!= NULL
);
749 /* The aspect must be exactly one of the image aspects. */
750 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
752 /* Determine the optimal buffer. */
754 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
756 /* If there is no auxiliary surface allocated, we must use the one and only
759 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
760 return ISL_AUX_USAGE_NONE
;
762 /* All images that use an auxiliary surface are required to be tiled. */
763 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
765 /* Stencil has no aux */
766 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
770 /* Invalid Layouts */
771 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
772 case VK_IMAGE_LAYOUT_MAX_ENUM
:
773 unreachable("Invalid image layout.");
777 * The pre-initialized layout is equivalent to the undefined layout for
778 * optimally-tiled images. We can only do color compression (CCS or HiZ)
781 case VK_IMAGE_LAYOUT_UNDEFINED
:
782 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
783 return ISL_AUX_USAGE_NONE
;
788 case VK_IMAGE_LAYOUT_GENERAL
:
789 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
790 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
791 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
792 /* This buffer could be a depth buffer used in a transfer operation.
793 * BLORP currently doesn't use HiZ for transfer operations so we must
794 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
796 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
797 return ISL_AUX_USAGE_NONE
;
799 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
800 return image
->planes
[plane
].aux_usage
;
804 /* Sampling Layouts */
805 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
806 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
807 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
809 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
810 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
811 if (anv_can_sample_with_hiz(devinfo
, image
))
812 return ISL_AUX_USAGE_HIZ
;
814 return ISL_AUX_USAGE_NONE
;
816 return image
->planes
[plane
].aux_usage
;
820 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
821 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
823 /* On SKL+, the render buffer can be decompressed by the presentation
824 * engine. Support for this feature has not yet landed in the wider
825 * ecosystem. TODO: Update this code when support lands.
827 * From the BDW PRM, Vol 7, Render Target Resolve:
829 * If the MCS is enabled on a non-multisampled render target, the
830 * render target must be resolved before being used for other
831 * purposes (display, texture, CPU lock) The clear value from
832 * SURFACE_STATE is written into pixels in the render target
833 * indicated as clear in the MCS.
835 * Pre-SKL, the render buffer must be resolved before being used for
836 * presentation. We can infer that the auxiliary buffer is not used.
838 return ISL_AUX_USAGE_NONE
;
841 /* Rendering Layouts */
842 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
843 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
844 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
845 assert(image
->samples
== 1);
846 return ISL_AUX_USAGE_CCS_D
;
848 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
849 return image
->planes
[plane
].aux_usage
;
852 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
853 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
854 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
855 return ISL_AUX_USAGE_HIZ
;
857 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
858 unreachable("VK_KHR_shared_presentable_image is unsupported");
861 /* If the layout isn't recognized in the exhaustive switch above, the
862 * VkImageLayout value is not defined in vulkan.h.
864 unreachable("layout is not a VkImageLayout enumeration member.");
868 * This function returns the level of unresolved fast-clear support of the
869 * given image in the given VkImageLayout.
871 * @param devinfo The device information of the Intel GPU.
872 * @param image The image that may contain a collection of buffers.
873 * @param aspect The aspect of the image to be accessed.
874 * @param layout The current layout of the image aspect(s).
876 enum anv_fast_clear_type
877 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
878 const struct anv_image
* const image
,
879 const VkImageAspectFlagBits aspect
,
880 const VkImageLayout layout
)
882 /* The aspect must be exactly one of the image aspects. */
883 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
885 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
887 /* If there is no auxiliary surface allocated, there are no fast-clears */
888 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
889 return ANV_FAST_CLEAR_NONE
;
891 /* All images that use an auxiliary surface are required to be tiled. */
892 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
894 /* Stencil has no aux */
895 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
897 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
898 /* For depth images (with HiZ), the layout supports fast-clears if and
899 * only if it supports HiZ. However, we only support fast-clears to the
900 * default depth value.
902 enum isl_aux_usage aux_usage
=
903 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
904 return aux_usage
== ISL_AUX_USAGE_HIZ
?
905 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
908 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
910 /* Multisample fast-clear is not yet supported. */
911 if (image
->samples
> 1)
912 return ANV_FAST_CLEAR_NONE
;
915 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
916 return ANV_FAST_CLEAR_ANY
;
918 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
919 return ANV_FAST_CLEAR_NONE
;
922 /* If the image has CCS_E enabled all the time then we can use
923 * fast-clear as long as the clear color is the default value of zero
924 * since this is the default value we program into every surface state
925 * used for texturing.
927 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
928 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
930 return ANV_FAST_CLEAR_NONE
;
935 static struct anv_state
936 alloc_surface_state(struct anv_device
*device
)
938 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
941 static enum isl_channel_select
942 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
943 struct isl_swizzle format_swizzle
)
945 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
949 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
950 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
951 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
952 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
953 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
954 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
956 unreachable("Invalid swizzle");
961 anv_image_fill_surface_state(struct anv_device
*device
,
962 const struct anv_image
*image
,
963 VkImageAspectFlagBits aspect
,
964 const struct isl_view
*view_in
,
965 isl_surf_usage_flags_t view_usage
,
966 enum isl_aux_usage aux_usage
,
967 const union isl_color_value
*clear_color
,
968 enum anv_image_view_state_flags flags
,
969 struct anv_surface_state
*state_inout
,
970 struct brw_image_param
*image_param_out
)
972 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
974 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
975 *aux_surface
= &image
->planes
[plane
].aux_surface
;
977 struct isl_view view
= *view_in
;
978 view
.usage
|= view_usage
;
980 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
981 * compressed surface with a shadow surface, we use the shadow instead of
982 * the primary surface. The shadow surface will be tiled, unlike the main
983 * surface, so it should get significantly better performance.
985 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
986 isl_format_is_compressed(view
.format
) &&
987 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
988 assert(isl_format_is_compressed(surface
->isl
.format
));
989 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
990 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
991 surface
= &image
->planes
[plane
].shadow_surface
;
994 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
995 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
997 /* If this is a HiZ buffer we can sample from with a programmable clear
998 * value (SKL+), define the clear value to the optimal constant.
1000 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1001 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1002 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1004 clear_color
= &default_clear_color
;
1006 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
1007 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
1008 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
1010 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1011 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1012 !isl_has_matching_typed_storage_image_format(&device
->info
,
1014 /* In this case, we are a writeable storage buffer which needs to be
1015 * lowered to linear. All tiling and offset calculations will be done in
1018 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1019 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1021 .size
= surface
->isl
.size
,
1022 .format
= ISL_FORMAT_RAW
,
1024 .mocs
= device
->default_mocs
);
1025 state_inout
->address
= address
,
1026 state_inout
->aux_address
= 0;
1028 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1029 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1030 /* Typed surface reads support a very limited subset of the shader
1031 * image formats. Translate it into the closest format the hardware
1034 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1035 view
.format
= isl_lower_storage_image_format(&device
->info
,
1039 const struct isl_surf
*isl_surf
= &surface
->isl
;
1041 struct isl_surf tmp_surf
;
1042 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1043 if (isl_format_is_compressed(surface
->isl
.format
) &&
1044 !isl_format_is_compressed(view
.format
)) {
1045 /* We're creating an uncompressed view of a compressed surface. This
1046 * is allowed but only for a single level/layer.
1048 assert(surface
->isl
.samples
== 1);
1049 assert(view
.levels
== 1);
1050 assert(view
.array_len
== 1);
1052 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1054 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1055 0 : view
.base_array_layer
,
1056 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1057 view
.base_array_layer
: 0,
1059 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1061 /* The newly created image represents the one subimage we're
1062 * referencing with this view so it only has one array slice and
1065 view
.base_array_layer
= 0;
1066 view
.base_level
= 0;
1068 /* We're making an uncompressed view here. The image dimensions need
1069 * to be scaled down by the block size.
1071 const struct isl_format_layout
*fmtl
=
1072 isl_format_get_layout(surface
->isl
.format
);
1073 tmp_surf
.format
= view
.format
;
1074 tmp_surf
.logical_level0_px
.width
=
1075 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1076 tmp_surf
.logical_level0_px
.height
=
1077 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1078 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1079 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1080 tile_x_sa
/= fmtl
->bw
;
1081 tile_y_sa
/= fmtl
->bh
;
1083 isl_surf
= &tmp_surf
;
1085 if (device
->info
.gen
<= 8) {
1086 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1087 assert(tile_x_sa
== 0);
1088 assert(tile_y_sa
== 0);
1092 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1095 .address
= address
+ offset_B
,
1096 .clear_color
= *clear_color
,
1097 .aux_surf
= &aux_surface
->isl
,
1098 .aux_usage
= aux_usage
,
1099 .aux_address
= aux_address
,
1100 .mocs
= device
->default_mocs
,
1101 .x_offset_sa
= tile_x_sa
,
1102 .y_offset_sa
= tile_y_sa
);
1103 state_inout
->address
= address
+ offset_B
;
1104 if (device
->info
.gen
>= 8) {
1105 state_inout
->aux_address
= aux_address
;
1107 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1108 * used to store other information. This should be ok, however,
1109 * because surface buffer addresses are always 4K page alinged.
1111 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1112 device
->isl_dev
.ss
.aux_addr_offset
;
1113 assert((aux_address
& 0xfff) == 0);
1114 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1115 state_inout
->aux_address
= *aux_addr_dw
;
1119 anv_state_flush(device
, state_inout
->state
);
1121 if (image_param_out
) {
1122 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1123 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1124 &surface
->isl
, &view
);
1128 static VkImageAspectFlags
1129 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1131 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1132 if (_mesa_bitcount(view_aspects
) == 1)
1133 return VK_IMAGE_ASPECT_COLOR_BIT
;
1135 VkImageAspectFlags color_aspects
= 0;
1136 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1137 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1138 return color_aspects
;
1140 /* No special remapping needed for depth & stencil aspects. */
1141 return view_aspects
;
1145 anv_CreateImageView(VkDevice _device
,
1146 const VkImageViewCreateInfo
*pCreateInfo
,
1147 const VkAllocationCallbacks
*pAllocator
,
1150 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1151 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1152 struct anv_image_view
*iview
;
1154 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1155 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1157 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1159 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1161 assert(range
->layerCount
> 0);
1162 assert(range
->baseMipLevel
< image
->levels
);
1164 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1165 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1166 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1167 /* View usage should be a subset of image usage */
1168 assert((view_usage
& ~image
->usage
) == 0);
1169 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1170 VK_IMAGE_USAGE_STORAGE_BIT
|
1171 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1172 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1173 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1175 switch (image
->type
) {
1177 unreachable("bad VkImageType");
1178 case VK_IMAGE_TYPE_1D
:
1179 case VK_IMAGE_TYPE_2D
:
1180 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1182 case VK_IMAGE_TYPE_3D
:
1183 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1184 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1188 /* First expand aspects to the image's ones (for example
1189 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1190 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1191 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1192 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1194 VkImageAspectFlags expanded_aspects
=
1195 anv_image_expand_aspects(image
, range
->aspectMask
);
1197 iview
->image
= image
;
1199 /* Remap the expanded aspects for the image view. For example if only
1200 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1201 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1202 * the image view, it only has a single plane.
1204 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1205 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1206 iview
->vk_format
= pCreateInfo
->format
;
1208 iview
->extent
= (VkExtent3D
) {
1209 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1210 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1211 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1214 /* Now go through the underlying image selected planes (computed in
1215 * expanded_aspects) and map them to planes in the image view.
1217 uint32_t iaspect_bit
, vplane
= 0;
1218 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1220 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1221 VkImageAspectFlags vplane_aspect
=
1222 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1223 struct anv_format_plane format
=
1224 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1225 vplane_aspect
, image
->tiling
);
1227 iview
->planes
[vplane
].image_plane
= iplane
;
1229 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1230 .format
= format
.isl_format
,
1231 .base_level
= range
->baseMipLevel
,
1232 .levels
= anv_get_levelCount(image
, range
),
1233 .base_array_layer
= range
->baseArrayLayer
,
1234 .array_len
= anv_get_layerCount(image
, range
),
1236 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1237 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1238 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1239 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1240 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1241 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1242 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1243 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1247 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1248 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1249 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1252 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1253 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1254 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1256 iview
->planes
[vplane
].isl
.usage
= 0;
1259 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1260 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1261 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1262 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1263 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1265 enum isl_aux_usage general_aux_usage
=
1266 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1267 VK_IMAGE_LAYOUT_GENERAL
);
1268 enum isl_aux_usage optimal_aux_usage
=
1269 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1270 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1272 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1273 &iview
->planes
[vplane
].isl
,
1274 ISL_SURF_USAGE_TEXTURE_BIT
,
1275 optimal_aux_usage
, NULL
,
1276 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1277 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1280 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1281 &iview
->planes
[vplane
].isl
,
1282 ISL_SURF_USAGE_TEXTURE_BIT
,
1283 general_aux_usage
, NULL
,
1285 &iview
->planes
[vplane
].general_sampler_surface_state
,
1289 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1290 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1291 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1292 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1294 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1295 &iview
->planes
[vplane
].isl
,
1296 ISL_SURF_USAGE_STORAGE_BIT
,
1297 ISL_AUX_USAGE_NONE
, NULL
,
1299 &iview
->planes
[vplane
].storage_surface_state
,
1300 &iview
->planes
[vplane
].storage_image_param
);
1302 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1303 &iview
->planes
[vplane
].isl
,
1304 ISL_SURF_USAGE_STORAGE_BIT
,
1305 ISL_AUX_USAGE_NONE
, NULL
,
1306 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1307 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1314 *pView
= anv_image_view_to_handle(iview
);
1320 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1321 const VkAllocationCallbacks
*pAllocator
)
1323 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1324 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1329 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1330 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1331 anv_state_pool_free(&device
->surface_state_pool
,
1332 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1335 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1336 anv_state_pool_free(&device
->surface_state_pool
,
1337 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1340 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1341 anv_state_pool_free(&device
->surface_state_pool
,
1342 iview
->planes
[plane
].storage_surface_state
.state
);
1345 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1346 anv_state_pool_free(&device
->surface_state_pool
,
1347 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1351 vk_free2(&device
->alloc
, pAllocator
, iview
);
1356 anv_CreateBufferView(VkDevice _device
,
1357 const VkBufferViewCreateInfo
*pCreateInfo
,
1358 const VkAllocationCallbacks
*pAllocator
,
1359 VkBufferView
*pView
)
1361 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1362 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1363 struct anv_buffer_view
*view
;
1365 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1366 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1368 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1370 /* TODO: Handle the format swizzle? */
1372 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1373 VK_IMAGE_ASPECT_COLOR_BIT
,
1374 VK_IMAGE_TILING_LINEAR
);
1375 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1376 view
->bo
= buffer
->bo
;
1377 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1378 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1379 pCreateInfo
->range
);
1380 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1382 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1383 view
->surface_state
= alloc_surface_state(device
);
1385 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1387 view
->offset
, view
->range
, format_bs
);
1389 view
->surface_state
= (struct anv_state
){ 0 };
1392 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1393 view
->storage_surface_state
= alloc_surface_state(device
);
1394 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1396 enum isl_format storage_format
=
1397 isl_has_matching_typed_storage_image_format(&device
->info
,
1399 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1402 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1404 view
->offset
, view
->range
,
1405 (storage_format
== ISL_FORMAT_RAW
? 1 :
1406 isl_format_get_layout(storage_format
)->bpb
/ 8));
1408 /* Write-only accesses should use the original format. */
1409 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1411 view
->offset
, view
->range
,
1412 isl_format_get_layout(view
->format
)->bpb
/ 8);
1414 isl_buffer_fill_image_param(&device
->isl_dev
,
1415 &view
->storage_image_param
,
1416 view
->format
, view
->range
);
1418 view
->storage_surface_state
= (struct anv_state
){ 0 };
1419 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1422 *pView
= anv_buffer_view_to_handle(view
);
1428 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1429 const VkAllocationCallbacks
*pAllocator
)
1431 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1432 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1437 if (view
->surface_state
.alloc_size
> 0)
1438 anv_state_pool_free(&device
->surface_state_pool
,
1439 view
->surface_state
);
1441 if (view
->storage_surface_state
.alloc_size
> 0)
1442 anv_state_pool_free(&device
->surface_state_pool
,
1443 view
->storage_surface_state
);
1445 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1446 anv_state_pool_free(&device
->surface_state_pool
,
1447 view
->writeonly_storage_surface_state
);
1449 vk_free2(&device
->alloc
, pAllocator
, view
);
1452 const struct anv_surface
*
1453 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1454 VkImageAspectFlags aspect_mask
)
1456 VkImageAspectFlags sanitized_mask
;
1458 switch (aspect_mask
) {
1459 case VK_IMAGE_ASPECT_COLOR_BIT
:
1460 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1461 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1463 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1464 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1465 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1467 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1468 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1469 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1471 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1472 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1473 * combined depth stencil formats. Specifically, it states:
1475 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1476 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1478 * Image views with both depth and stencil aspects are only valid for
1479 * render target attachments, in which case
1480 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1481 * stencil surfaces from the underlying surface.
1483 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1484 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1486 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1487 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1490 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1491 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1492 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1494 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1495 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1496 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1498 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1499 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1500 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1503 unreachable("image does not have aspect");
1507 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1508 return &image
->planes
[plane
].surface
;