3bd8be4c07227dbdbef709bc56e7e38dfb98b293
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "util/debug.h"
32
33 #include "vk_format_info.h"
34
35 /**
36 * Exactly one bit must be set in \a aspect.
37 */
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageUsageFlags vk_usage,
40 VkImageAspectFlags aspect)
41 {
42 isl_surf_usage_flags_t isl_usage = 0;
43
44 /* FINISHME: Support aux surfaces */
45 isl_usage |= ISL_SURF_USAGE_DISABLE_AUX_BIT;
46
47 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
48 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
49
50 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
51 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
52
53 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
54 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
55
56 if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
57 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
58
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
62 */
63 switch (aspect) {
64 case VK_IMAGE_ASPECT_DEPTH_BIT:
65 isl_usage &= ~ISL_SURF_USAGE_DISABLE_AUX_BIT;
66 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
67 break;
68 case VK_IMAGE_ASPECT_STENCIL_BIT:
69 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
70 break;
71 case VK_IMAGE_ASPECT_COLOR_BIT:
72 break;
73 default:
74 unreachable("bad VkImageAspect");
75 }
76
77 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
78 /* blorp implements transfers by sampling from the source image. */
79 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
80 }
81
82 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT) {
83 /* blorp implements transfers by rendering into the destination image. */
84 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
85 }
86
87 return isl_usage;
88 }
89
90 /**
91 * Exactly one bit must be set in \a aspect.
92 */
93 static struct anv_surface *
94 get_surface(struct anv_image *image, VkImageAspectFlags aspect)
95 {
96 switch (aspect) {
97 default:
98 unreachable("bad VkImageAspect");
99 case VK_IMAGE_ASPECT_COLOR_BIT:
100 return &image->color_surface;
101 case VK_IMAGE_ASPECT_DEPTH_BIT:
102 return &image->depth_surface;
103 case VK_IMAGE_ASPECT_STENCIL_BIT:
104 return &image->stencil_surface;
105 }
106 }
107
108 static void
109 add_surface(struct anv_image *image, struct anv_surface *surf)
110 {
111 assert(surf->isl.size > 0); /* isl surface must be initialized */
112
113 surf->offset = align_u32(image->size, surf->isl.alignment);
114 image->size = surf->offset + surf->isl.size;
115 image->alignment = MAX2(image->alignment, surf->isl.alignment);
116 }
117
118 /**
119 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
120 * image's memory requirements (that is, the image's size and alignment).
121 *
122 * Exactly one bit must be set in \a aspect.
123 */
124 static VkResult
125 make_surface(const struct anv_device *dev,
126 struct anv_image *image,
127 const struct anv_image_create_info *anv_info,
128 VkImageAspectFlags aspect)
129 {
130 const VkImageCreateInfo *vk_info = anv_info->vk_info;
131 bool ok UNUSED;
132
133 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
134 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
135 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
136 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
137 };
138
139 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
140 * result with an optionally provided ISL tiling argument.
141 */
142 isl_tiling_flags_t tiling_flags =
143 (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
144 ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
145
146 if (anv_info->isl_tiling_flags)
147 tiling_flags &= anv_info->isl_tiling_flags;
148
149 assert(tiling_flags);
150
151 struct anv_surface *anv_surf = get_surface(image, aspect);
152
153 image->extent = anv_sanitize_image_extent(vk_info->imageType,
154 vk_info->extent);
155
156 enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
157 aspect, vk_info->tiling);
158 assert(format != ISL_FORMAT_UNSUPPORTED);
159
160 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
161 .dim = vk_to_isl_surf_dim[vk_info->imageType],
162 .format = format,
163 .width = image->extent.width,
164 .height = image->extent.height,
165 .depth = image->extent.depth,
166 .levels = vk_info->mipLevels,
167 .array_len = vk_info->arrayLayers,
168 .samples = vk_info->samples,
169 .min_alignment = 0,
170 .min_pitch = anv_info->stride,
171 .usage = choose_isl_surf_usage(image->usage, aspect),
172 .tiling_flags = tiling_flags);
173
174 /* isl_surf_init() will fail only if provided invalid input. Invalid input
175 * is illegal in Vulkan.
176 */
177 assert(ok);
178
179 add_surface(image, anv_surf);
180
181 /* Add a HiZ surface to a depth buffer that will be used for rendering.
182 */
183 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT &&
184 (image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
185
186 /* Allow the user to control HiZ enabling. Disable by default on gen7
187 * because resolves are not currently implemented pre-BDW.
188 */
189 if (!env_var_as_boolean("INTEL_VK_HIZ", dev->info.gen >= 8)) {
190 anv_finishme("Implement gen7 HiZ");
191 } else if (vk_info->mipLevels > 1) {
192 anv_finishme("Test multi-LOD HiZ");
193 } else if (dev->info.gen == 8 && vk_info->samples > 1) {
194 anv_finishme("Test gen8 multisampled HiZ");
195 } else {
196 isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
197 &image->hiz_surface.isl);
198 add_surface(image, &image->hiz_surface);
199 }
200 }
201
202 return VK_SUCCESS;
203 }
204
205 VkResult
206 anv_image_create(VkDevice _device,
207 const struct anv_image_create_info *create_info,
208 const VkAllocationCallbacks* alloc,
209 VkImage *pImage)
210 {
211 ANV_FROM_HANDLE(anv_device, device, _device);
212 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
213 struct anv_image *image = NULL;
214 VkResult r;
215
216 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
217
218 anv_assert(pCreateInfo->mipLevels > 0);
219 anv_assert(pCreateInfo->arrayLayers > 0);
220 anv_assert(pCreateInfo->samples > 0);
221 anv_assert(pCreateInfo->extent.width > 0);
222 anv_assert(pCreateInfo->extent.height > 0);
223 anv_assert(pCreateInfo->extent.depth > 0);
224
225 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
226 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
227 if (!image)
228 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
229
230 memset(image, 0, sizeof(*image));
231 image->type = pCreateInfo->imageType;
232 image->extent = pCreateInfo->extent;
233 image->vk_format = pCreateInfo->format;
234 image->aspects = vk_format_aspects(image->vk_format);
235 image->levels = pCreateInfo->mipLevels;
236 image->array_size = pCreateInfo->arrayLayers;
237 image->samples = pCreateInfo->samples;
238 image->usage = pCreateInfo->usage;
239 image->tiling = pCreateInfo->tiling;
240
241 uint32_t b;
242 for_each_bit(b, image->aspects) {
243 r = make_surface(device, image, create_info, (1 << b));
244 if (r != VK_SUCCESS)
245 goto fail;
246 }
247
248 *pImage = anv_image_to_handle(image);
249
250 return VK_SUCCESS;
251
252 fail:
253 if (image)
254 vk_free2(&device->alloc, alloc, image);
255
256 return r;
257 }
258
259 VkResult
260 anv_CreateImage(VkDevice device,
261 const VkImageCreateInfo *pCreateInfo,
262 const VkAllocationCallbacks *pAllocator,
263 VkImage *pImage)
264 {
265 return anv_image_create(device,
266 &(struct anv_image_create_info) {
267 .vk_info = pCreateInfo,
268 },
269 pAllocator,
270 pImage);
271 }
272
273 void
274 anv_DestroyImage(VkDevice _device, VkImage _image,
275 const VkAllocationCallbacks *pAllocator)
276 {
277 ANV_FROM_HANDLE(anv_device, device, _device);
278 ANV_FROM_HANDLE(anv_image, image, _image);
279
280 if (!image)
281 return;
282
283 vk_free2(&device->alloc, pAllocator, image);
284 }
285
286 VkResult anv_BindImageMemory(
287 VkDevice _device,
288 VkImage _image,
289 VkDeviceMemory _memory,
290 VkDeviceSize memoryOffset)
291 {
292 ANV_FROM_HANDLE(anv_device, device, _device);
293 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
294 ANV_FROM_HANDLE(anv_image, image, _image);
295
296 if (mem) {
297 image->bo = &mem->bo;
298 image->offset = memoryOffset;
299 } else {
300 image->bo = NULL;
301 image->offset = 0;
302 }
303
304 if (anv_image_has_hiz(image)) {
305
306 /* The offset and size must be a multiple of 4K or else the
307 * anv_gem_mmap call below will return NULL.
308 */
309 assert((image->offset + image->hiz_surface.offset) % 4096 == 0);
310 assert(image->hiz_surface.isl.size % 4096 == 0);
311
312 /* HiZ surfaces need to have their memory cleared to 0 before they
313 * can be used. If we let it have garbage data, it can cause GPU
314 * hangs on some hardware.
315 */
316 void *map = anv_gem_mmap(device, image->bo->gem_handle,
317 image->offset + image->hiz_surface.offset,
318 image->hiz_surface.isl.size,
319 device->info.has_llc ? 0 : I915_MMAP_WC);
320
321 /* If anv_gem_mmap returns NULL, it's likely that the kernel was
322 * not able to find space on the host to create a proper mapping.
323 */
324 if (map == NULL)
325 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
326
327 memset(map, 0, image->hiz_surface.isl.size);
328
329 anv_gem_munmap(map, image->hiz_surface.isl.size);
330 }
331
332 return VK_SUCCESS;
333 }
334
335 static void
336 anv_surface_get_subresource_layout(struct anv_image *image,
337 struct anv_surface *surface,
338 const VkImageSubresource *subresource,
339 VkSubresourceLayout *layout)
340 {
341 /* If we are on a non-zero mip level or array slice, we need to
342 * calculate a real offset.
343 */
344 anv_assert(subresource->mipLevel == 0);
345 anv_assert(subresource->arrayLayer == 0);
346
347 layout->offset = surface->offset;
348 layout->rowPitch = surface->isl.row_pitch;
349 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
350 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
351 layout->size = surface->isl.size;
352 }
353
354 void anv_GetImageSubresourceLayout(
355 VkDevice device,
356 VkImage _image,
357 const VkImageSubresource* pSubresource,
358 VkSubresourceLayout* pLayout)
359 {
360 ANV_FROM_HANDLE(anv_image, image, _image);
361
362 assert(__builtin_popcount(pSubresource->aspectMask) == 1);
363
364 switch (pSubresource->aspectMask) {
365 case VK_IMAGE_ASPECT_COLOR_BIT:
366 anv_surface_get_subresource_layout(image, &image->color_surface,
367 pSubresource, pLayout);
368 break;
369 case VK_IMAGE_ASPECT_DEPTH_BIT:
370 anv_surface_get_subresource_layout(image, &image->depth_surface,
371 pSubresource, pLayout);
372 break;
373 case VK_IMAGE_ASPECT_STENCIL_BIT:
374 anv_surface_get_subresource_layout(image, &image->stencil_surface,
375 pSubresource, pLayout);
376 break;
377 default:
378 assert(!"Invalid image aspect");
379 }
380 }
381
382 static struct anv_state
383 alloc_surface_state(struct anv_device *device)
384 {
385 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
386 }
387
388 static enum isl_channel_select
389 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
390 struct isl_swizzle format_swizzle)
391 {
392 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
393 swizzle = component;
394
395 switch (swizzle) {
396 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
397 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
398 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
399 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
400 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
401 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
402 default:
403 unreachable("Invalid swizzle");
404 }
405 }
406
407
408 VkResult
409 anv_CreateImageView(VkDevice _device,
410 const VkImageViewCreateInfo *pCreateInfo,
411 const VkAllocationCallbacks *pAllocator,
412 VkImageView *pView)
413 {
414 ANV_FROM_HANDLE(anv_device, device, _device);
415 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
416 struct anv_image_view *iview;
417
418 iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
419 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
420 if (iview == NULL)
421 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
422
423 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
424
425 assert(range->layerCount > 0);
426 assert(range->baseMipLevel < image->levels);
427 assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
428 VK_IMAGE_USAGE_STORAGE_BIT |
429 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
430 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
431
432 switch (image->type) {
433 default:
434 unreachable("bad VkImageType");
435 case VK_IMAGE_TYPE_1D:
436 case VK_IMAGE_TYPE_2D:
437 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
438 break;
439 case VK_IMAGE_TYPE_3D:
440 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
441 <= anv_minify(image->extent.depth, range->baseMipLevel));
442 break;
443 }
444
445 const struct anv_surface *surface =
446 anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
447
448 iview->image = image;
449 iview->bo = image->bo;
450 iview->offset = image->offset + surface->offset;
451
452 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
453 iview->vk_format = pCreateInfo->format;
454
455 struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
456 range->aspectMask, image->tiling);
457
458 iview->isl = (struct isl_view) {
459 .format = format.isl_format,
460 .base_level = range->baseMipLevel,
461 .levels = anv_get_levelCount(image, range),
462 .base_array_layer = range->baseArrayLayer,
463 .array_len = anv_get_layerCount(image, range),
464 .swizzle = {
465 .r = remap_swizzle(pCreateInfo->components.r,
466 VK_COMPONENT_SWIZZLE_R, format.swizzle),
467 .g = remap_swizzle(pCreateInfo->components.g,
468 VK_COMPONENT_SWIZZLE_G, format.swizzle),
469 .b = remap_swizzle(pCreateInfo->components.b,
470 VK_COMPONENT_SWIZZLE_B, format.swizzle),
471 .a = remap_swizzle(pCreateInfo->components.a,
472 VK_COMPONENT_SWIZZLE_A, format.swizzle),
473 },
474 };
475
476 iview->extent = (VkExtent3D) {
477 .width = anv_minify(image->extent.width , range->baseMipLevel),
478 .height = anv_minify(image->extent.height, range->baseMipLevel),
479 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
480 };
481
482 if (image->type == VK_IMAGE_TYPE_3D) {
483 iview->isl.base_array_layer = 0;
484 iview->isl.array_len = iview->extent.depth;
485 }
486
487 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
488 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
489 iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
490 } else {
491 iview->isl.usage = 0;
492 }
493
494 if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT) {
495 iview->sampler_surface_state = alloc_surface_state(device);
496
497 struct isl_view view = iview->isl;
498 view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
499 isl_surf_fill_state(&device->isl_dev,
500 iview->sampler_surface_state.map,
501 .surf = &surface->isl,
502 .view = &view,
503 .mocs = device->default_mocs);
504
505 if (!device->info.has_llc)
506 anv_state_clflush(iview->sampler_surface_state);
507 } else {
508 iview->sampler_surface_state.alloc_size = 0;
509 }
510
511 /* NOTE: This one needs to go last since it may stomp isl_view.format */
512 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
513 iview->storage_surface_state = alloc_surface_state(device);
514
515 if (isl_has_matching_typed_storage_image_format(&device->info,
516 format.isl_format)) {
517 struct isl_view view = iview->isl;
518 view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
519 view.format = isl_lower_storage_image_format(&device->info,
520 format.isl_format);
521 isl_surf_fill_state(&device->isl_dev,
522 iview->storage_surface_state.map,
523 .surf = &surface->isl,
524 .view = &view,
525 .mocs = device->default_mocs);
526 } else {
527 anv_fill_buffer_surface_state(device, iview->storage_surface_state,
528 ISL_FORMAT_RAW,
529 iview->offset,
530 iview->bo->size - iview->offset, 1);
531 }
532
533 isl_surf_fill_image_param(&device->isl_dev,
534 &iview->storage_image_param,
535 &surface->isl, &iview->isl);
536
537 if (!device->info.has_llc)
538 anv_state_clflush(iview->storage_surface_state);
539 } else {
540 iview->storage_surface_state.alloc_size = 0;
541 }
542
543 *pView = anv_image_view_to_handle(iview);
544
545 return VK_SUCCESS;
546 }
547
548 void
549 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
550 const VkAllocationCallbacks *pAllocator)
551 {
552 ANV_FROM_HANDLE(anv_device, device, _device);
553 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
554
555 if (!iview)
556 return;
557
558 if (iview->sampler_surface_state.alloc_size > 0) {
559 anv_state_pool_free(&device->surface_state_pool,
560 iview->sampler_surface_state);
561 }
562
563 if (iview->storage_surface_state.alloc_size > 0) {
564 anv_state_pool_free(&device->surface_state_pool,
565 iview->storage_surface_state);
566 }
567
568 vk_free2(&device->alloc, pAllocator, iview);
569 }
570
571
572 VkResult
573 anv_CreateBufferView(VkDevice _device,
574 const VkBufferViewCreateInfo *pCreateInfo,
575 const VkAllocationCallbacks *pAllocator,
576 VkBufferView *pView)
577 {
578 ANV_FROM_HANDLE(anv_device, device, _device);
579 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
580 struct anv_buffer_view *view;
581
582 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
583 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
584 if (!view)
585 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
586
587 /* TODO: Handle the format swizzle? */
588
589 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
590 VK_IMAGE_ASPECT_COLOR_BIT,
591 VK_IMAGE_TILING_LINEAR);
592 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
593 view->bo = buffer->bo;
594 view->offset = buffer->offset + pCreateInfo->offset;
595 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
596 buffer->size - pCreateInfo->offset : pCreateInfo->range;
597 view->range = align_down_npot_u32(view->range, format_bs);
598
599 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
600 view->surface_state = alloc_surface_state(device);
601
602 anv_fill_buffer_surface_state(device, view->surface_state,
603 view->format,
604 view->offset, view->range, format_bs);
605 } else {
606 view->surface_state = (struct anv_state){ 0 };
607 }
608
609 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
610 view->storage_surface_state = alloc_surface_state(device);
611
612 enum isl_format storage_format =
613 isl_has_matching_typed_storage_image_format(&device->info,
614 view->format) ?
615 isl_lower_storage_image_format(&device->info, view->format) :
616 ISL_FORMAT_RAW;
617
618 anv_fill_buffer_surface_state(device, view->storage_surface_state,
619 storage_format,
620 view->offset, view->range,
621 (storage_format == ISL_FORMAT_RAW ? 1 :
622 isl_format_get_layout(storage_format)->bpb / 8));
623
624 isl_buffer_fill_image_param(&device->isl_dev,
625 &view->storage_image_param,
626 view->format, view->range);
627 } else {
628 view->storage_surface_state = (struct anv_state){ 0 };
629 }
630
631 *pView = anv_buffer_view_to_handle(view);
632
633 return VK_SUCCESS;
634 }
635
636 void
637 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
638 const VkAllocationCallbacks *pAllocator)
639 {
640 ANV_FROM_HANDLE(anv_device, device, _device);
641 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
642
643 if (!view)
644 return;
645
646 if (view->surface_state.alloc_size > 0)
647 anv_state_pool_free(&device->surface_state_pool,
648 view->surface_state);
649
650 if (view->storage_surface_state.alloc_size > 0)
651 anv_state_pool_free(&device->surface_state_pool,
652 view->storage_surface_state);
653
654 vk_free2(&device->alloc, pAllocator, view);
655 }
656
657 const struct anv_surface *
658 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
659 VkImageAspectFlags aspect_mask)
660 {
661 switch (aspect_mask) {
662 case VK_IMAGE_ASPECT_COLOR_BIT:
663 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
664 return &image->color_surface;
665 case VK_IMAGE_ASPECT_DEPTH_BIT:
666 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
667 return &image->depth_surface;
668 case VK_IMAGE_ASPECT_STENCIL_BIT:
669 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
670 return &image->stencil_surface;
671 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
672 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
673 * combined depth stencil formats. Specifically, it states:
674 *
675 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
676 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
677 *
678 * Image views with both depth and stencil aspects are only valid for
679 * render target attachments, in which case
680 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
681 * stencil surfaces from the underlying surface.
682 */
683 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
684 return &image->depth_surface;
685 } else {
686 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
687 return &image->stencil_surface;
688 }
689 default:
690 unreachable("image does not have aspect");
691 return NULL;
692 }
693 }