2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
96 const struct isl_drm_modifier_info
*isl_mod_info
,
99 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
100 isl_tiling_flags_t flags
= 0;
102 switch (base_info
->tiling
) {
104 unreachable("bad VkImageTiling");
105 case VK_IMAGE_TILING_OPTIMAL
:
106 flags
= ISL_TILING_ANY_MASK
;
108 case VK_IMAGE_TILING_LINEAR
:
109 flags
= ISL_TILING_LINEAR_BIT
;
113 if (anv_info
->isl_tiling_flags
)
114 flags
&= anv_info
->isl_tiling_flags
;
117 flags
&= ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
;
120 flags
&= 1 << isl_mod_info
->tiling
;
127 static struct anv_surface
*
128 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
130 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
131 return &image
->planes
[plane
].surface
;
135 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
137 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
139 if (image
->disjoint
) {
140 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
141 /* Plane offset is always 0 when it's disjoint. */
143 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
144 /* Determine plane's offset only once when the first surface is added. */
145 if (image
->planes
[plane
].size
== 0)
146 image
->planes
[plane
].offset
= image
->size
;
149 image
->size
= surf
->offset
+ surf
->isl
.size
;
150 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
152 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
153 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
154 surf
->isl
.alignment
);
159 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
160 const struct VkImageCreateInfo
*vk_info
)
162 enum isl_format format
=
163 anv_get_isl_format(devinfo
, vk_info
->format
,
164 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
166 if (!isl_format_supports_ccs_e(devinfo
, format
))
169 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
172 const VkImageFormatListCreateInfoKHR
*fmt_list
=
173 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
175 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
178 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
179 enum isl_format view_format
=
180 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
181 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
183 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
191 * For color images that have an auxiliary surface, request allocation for an
192 * additional buffer that mainly stores fast-clear values. Use of this buffer
193 * allows us to access the image's subresources while being aware of their
194 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
195 * which a fast clear has occurred).
197 * In order to avoid having multiple clear colors for a single plane of an
198 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
199 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
200 * 2018), there were no known applications which would benefit from fast-
201 * clearing more than just the first slice.
203 * The fast clear portion of the image is laid out in the following order:
205 * * 1 or 4 dwords (depending on hardware generation) for the clear color
206 * * 1 dword for the anv_fast_clear_type of the clear color
207 * * On gen9+, 1 dword per level and layer of the image (3D levels count
208 * multiple layers) in level-major order for compression state.
210 * For the purpose of discoverability, the algorithm used to manage
211 * compression and fast-clears is described here:
213 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
214 * all of the values in the fast clear portion of the image are initialized
217 * * On fast-clear, the clear value is written into surface state and also
218 * into the buffer and the fast clear type is set appropriately. Both
219 * setting the fast-clear value in the buffer and setting the fast-clear
220 * type happen from the GPU using MI commands.
222 * * Whenever a render or blorp operation is performed with CCS_E, we call
223 * genX(cmd_buffer_mark_image_written) to set the compression state to
224 * true (which is represented by UINT32_MAX).
226 * * On pipeline barrier transitions, the worst-case transition is computed
227 * from the image layouts. The command streamer inspects the fast clear
228 * type and compression state dwords and constructs a predicate. The
229 * worst-case resolve is performed with the given predicate and the fast
230 * clear and compression state is set accordingly.
232 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
233 * details on exactly what is allowed in what layouts.
235 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
236 * In order to deal with this, we have to do some clear color management.
238 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
239 * value from the buffer into the surface state with MI commands.
241 * * For any blorp operations, we pass the address to the clear value into
242 * blorp and it knows to copy the clear color.
245 add_aux_state_tracking_buffer(struct anv_image
*image
,
246 VkImageAspectFlagBits aspect
,
248 const struct anv_device
*device
)
250 assert(image
&& device
);
251 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
252 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
254 /* Compressed images must be tiled and therefore everything should be 4K
255 * aligned. The CCS has the same alignment requirements. This is good
256 * because we need at least dword-alignment for MI_LOAD/STORE operations.
258 assert(image
->alignment
% 4 == 0);
259 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
261 /* This buffer should be at the very end of the plane. */
262 if (image
->disjoint
) {
263 assert(image
->planes
[plane
].size
==
264 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
266 assert(image
->size
==
267 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
270 /* Clear color and fast clear type */
271 unsigned state_size
= device
->isl_dev
.ss
.clear_value_size
+ 4;
273 /* We only need to track compression on CCS_E surfaces. */
274 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
275 if (image
->type
== VK_IMAGE_TYPE_3D
) {
276 for (uint32_t l
= 0; l
< image
->levels
; l
++)
277 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
279 state_size
+= image
->levels
* image
->array_size
* 4;
283 image
->planes
[plane
].fast_clear_state_offset
=
284 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
286 image
->planes
[plane
].size
+= state_size
;
287 image
->size
+= state_size
;
291 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
292 * image's memory requirements (that is, the image's size and alignment).
295 make_surface(const struct anv_device
*dev
,
296 struct anv_image
*image
,
297 const struct anv_image_create_info
*anv_info
,
298 isl_tiling_flags_t tiling_flags
,
299 VkImageAspectFlagBits aspect
)
301 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
304 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
305 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
306 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
307 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
310 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
313 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
314 const struct anv_format_plane plane_format
=
315 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
316 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
318 const isl_surf_usage_flags_t usage
=
319 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
320 anv_info
->isl_extra_usage_flags
, aspect
);
322 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
323 * fall back to linear on Broadwell and earlier because we aren't
324 * guaranteed that we can handle offsets correctly. On Sky Lake, the
325 * horizontal and vertical alignments are sufficiently high that we can
326 * just use RENDER_SURFACE_STATE::X/Y Offset.
328 bool needs_shadow
= false;
329 if (dev
->info
.gen
<= 8 &&
330 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT
) &&
331 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
332 assert(isl_format_is_compressed(plane_format
.isl_format
));
333 tiling_flags
= ISL_TILING_LINEAR_BIT
;
337 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
338 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
339 .format
= plane_format
.isl_format
,
340 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
341 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
342 .depth
= image
->extent
.depth
,
343 .levels
= vk_info
->mipLevels
,
344 .array_len
= vk_info
->arrayLayers
,
345 .samples
= vk_info
->samples
,
347 .row_pitch
= anv_info
->stride
,
349 .tiling_flags
= tiling_flags
);
352 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
354 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
356 add_surface(image
, anv_surf
, plane
);
358 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
359 * create an identical tiled shadow surface for use while texturing so we
360 * don't get garbage performance.
363 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
364 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
366 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
367 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
368 .format
= plane_format
.isl_format
,
369 .width
= image
->extent
.width
,
370 .height
= image
->extent
.height
,
371 .depth
= image
->extent
.depth
,
372 .levels
= vk_info
->mipLevels
,
373 .array_len
= vk_info
->arrayLayers
,
374 .samples
= vk_info
->samples
,
376 .row_pitch
= anv_info
->stride
,
378 .tiling_flags
= ISL_TILING_ANY_MASK
);
380 /* isl_surf_init() will fail only if provided invalid input. Invalid input
381 * is illegal in Vulkan.
385 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
388 /* Add a HiZ surface to a depth buffer that will be used for rendering.
390 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
391 /* We don't advertise that depth buffers could be used as storage
394 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
396 /* Allow the user to control HiZ enabling. Disable by default on gen7
397 * because resolves are not currently implemented pre-BDW.
399 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
400 /* It will never be used as an attachment, HiZ is pointless. */
401 } else if (dev
->info
.gen
== 7) {
402 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
403 } else if (vk_info
->mipLevels
> 1) {
404 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
405 } else if (vk_info
->arrayLayers
> 1) {
406 anv_perf_warn(dev
->instance
, image
,
407 "Implement multi-arrayLayer HiZ clears and resolves");
408 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
409 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
410 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
411 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
412 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
413 &image
->planes
[plane
].surface
.isl
,
414 &image
->planes
[plane
].aux_surface
.isl
);
416 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
417 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
419 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
420 /* TODO: Disallow compression with :
422 * 1) non multiplanar images (We appear to hit a sampler bug with
423 * CCS & R16G16 format. Putting the clear state a page/4096bytes
424 * further fixes the issue).
426 * 2) alias images, because they might be aliases of images
429 * 3) compression disabled by debug
431 const bool allow_compression
=
432 image
->n_planes
== 1 &&
433 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT
) == 0 &&
434 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
436 if (allow_compression
) {
437 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
438 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
439 &image
->planes
[plane
].surface
.isl
,
440 &image
->planes
[plane
].aux_surface
.isl
, 0);
443 /* Disable CCS when it is not useful (i.e., when you can't render
444 * to the image with CCS enabled).
446 if (!isl_format_supports_rendering(&dev
->info
,
447 plane_format
.isl_format
)) {
448 /* While it may be technically possible to enable CCS for this
449 * image, we currently don't have things hooked up to get it
452 anv_perf_warn(dev
->instance
, image
,
453 "This image format doesn't support rendering. "
454 "Not allocating an CCS buffer.");
455 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
459 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
460 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
462 /* For images created without MUTABLE_FORMAT_BIT set, we know that
463 * they will always be used with the original format. In
464 * particular, they will always be used with a format that
465 * supports color compression. If it's never used as a storage
466 * image, then it will only be used through the sampler or the as
467 * a render target. This means that it's safe to just leave
468 * compression on at all times for these formats.
470 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
471 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
472 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
476 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
477 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
478 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
479 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
480 &image
->planes
[plane
].surface
.isl
,
481 &image
->planes
[plane
].aux_surface
.isl
);
483 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
484 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
485 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
489 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
491 /* Upper bound of the last surface should be smaller than the plane's
494 assert((MAX2(image
->planes
[plane
].surface
.offset
,
495 image
->planes
[plane
].aux_surface
.offset
) +
496 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
497 image
->planes
[plane
].aux_surface
.isl
.size
:
498 image
->planes
[plane
].surface
.isl
.size
)) <=
499 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
501 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
502 /* assert(image->planes[plane].fast_clear_state_offset == */
503 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
504 assert(image
->planes
[plane
].fast_clear_state_offset
<
505 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
512 score_drm_format_mod(uint64_t modifier
)
515 case DRM_FORMAT_MOD_LINEAR
: return 1;
516 case I915_FORMAT_MOD_X_TILED
: return 2;
517 case I915_FORMAT_MOD_Y_TILED
: return 3;
518 default: unreachable("bad DRM format modifier");
522 static const struct isl_drm_modifier_info
*
523 choose_drm_format_mod(const struct anv_physical_device
*device
,
524 uint32_t modifier_count
, const uint64_t *modifiers
)
526 uint64_t best_mod
= UINT64_MAX
;
527 uint32_t best_score
= 0;
529 for (uint32_t i
= 0; i
< modifier_count
; ++i
) {
530 uint32_t score
= score_drm_format_mod(modifiers
[i
]);
531 if (score
> best_score
) {
532 best_mod
= modifiers
[i
];
538 return isl_drm_modifier_get_info(best_mod
);
544 anv_image_create(VkDevice _device
,
545 const struct anv_image_create_info
*create_info
,
546 const VkAllocationCallbacks
* alloc
,
549 ANV_FROM_HANDLE(anv_device
, device
, _device
);
550 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
551 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
552 struct anv_image
*image
= NULL
;
555 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
557 const struct wsi_image_create_info
*wsi_info
=
558 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
559 if (wsi_info
&& wsi_info
->modifier_count
> 0) {
560 isl_mod_info
= choose_drm_format_mod(&device
->instance
->physicalDevice
,
561 wsi_info
->modifier_count
,
562 wsi_info
->modifiers
);
563 assert(isl_mod_info
);
566 anv_assert(pCreateInfo
->mipLevels
> 0);
567 anv_assert(pCreateInfo
->arrayLayers
> 0);
568 anv_assert(pCreateInfo
->samples
> 0);
569 anv_assert(pCreateInfo
->extent
.width
> 0);
570 anv_assert(pCreateInfo
->extent
.height
> 0);
571 anv_assert(pCreateInfo
->extent
.depth
> 0);
573 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
574 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
576 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
578 image
->type
= pCreateInfo
->imageType
;
579 image
->extent
= pCreateInfo
->extent
;
580 image
->vk_format
= pCreateInfo
->format
;
581 image
->format
= anv_get_format(pCreateInfo
->format
);
582 image
->aspects
= vk_format_aspects(image
->vk_format
);
583 image
->levels
= pCreateInfo
->mipLevels
;
584 image
->array_size
= pCreateInfo
->arrayLayers
;
585 image
->samples
= pCreateInfo
->samples
;
586 image
->usage
= pCreateInfo
->usage
;
587 image
->tiling
= pCreateInfo
->tiling
;
588 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT
;
589 image
->needs_set_tiling
= wsi_info
&& wsi_info
->scanout
;
590 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
591 DRM_FORMAT_MOD_INVALID
;
593 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
594 assert(format
!= NULL
);
596 const isl_tiling_flags_t isl_tiling_flags
=
597 choose_isl_tiling_flags(create_info
, isl_mod_info
,
598 image
->needs_set_tiling
);
600 image
->n_planes
= format
->n_planes
;
603 for_each_bit(b
, image
->aspects
) {
604 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
610 *pImage
= anv_image_to_handle(image
);
616 vk_free2(&device
->alloc
, alloc
, image
);
622 anv_CreateImage(VkDevice device
,
623 const VkImageCreateInfo
*pCreateInfo
,
624 const VkAllocationCallbacks
*pAllocator
,
628 const VkNativeBufferANDROID
*gralloc_info
=
629 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
632 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
636 return anv_image_create(device
,
637 &(struct anv_image_create_info
) {
638 .vk_info
= pCreateInfo
,
645 anv_DestroyImage(VkDevice _device
, VkImage _image
,
646 const VkAllocationCallbacks
*pAllocator
)
648 ANV_FROM_HANDLE(anv_device
, device
, _device
);
649 ANV_FROM_HANDLE(anv_image
, image
, _image
);
654 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
655 if (image
->planes
[p
].bo_is_owned
) {
656 assert(image
->planes
[p
].bo
!= NULL
);
657 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
661 vk_free2(&device
->alloc
, pAllocator
, image
);
664 static void anv_image_bind_memory_plane(struct anv_device
*device
,
665 struct anv_image
*image
,
667 struct anv_device_memory
*memory
,
668 uint32_t memory_offset
)
670 assert(!image
->planes
[plane
].bo_is_owned
);
673 image
->planes
[plane
].bo
= NULL
;
674 image
->planes
[plane
].bo_offset
= 0;
678 image
->planes
[plane
].bo
= memory
->bo
;
679 image
->planes
[plane
].bo_offset
= memory_offset
;
682 VkResult
anv_BindImageMemory(
685 VkDeviceMemory _memory
,
686 VkDeviceSize memoryOffset
)
688 ANV_FROM_HANDLE(anv_device
, device
, _device
);
689 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
690 ANV_FROM_HANDLE(anv_image
, image
, _image
);
693 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
695 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
696 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
702 VkResult
anv_BindImageMemory2(
704 uint32_t bindInfoCount
,
705 const VkBindImageMemoryInfo
* pBindInfos
)
707 ANV_FROM_HANDLE(anv_device
, device
, _device
);
709 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
710 const VkBindImageMemoryInfo
*bind_info
= &pBindInfos
[i
];
711 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
712 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
713 VkImageAspectFlags aspects
= image
->aspects
;
715 vk_foreach_struct_const(s
, bind_info
->pNext
) {
717 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO
: {
718 const VkBindImagePlaneMemoryInfo
*plane_info
=
719 (const VkBindImagePlaneMemoryInfo
*) s
;
721 aspects
= plane_info
->planeAspect
;
725 anv_debug_ignored_stype(s
->sType
);
731 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
733 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
734 anv_image_bind_memory_plane(device
, image
, plane
,
735 mem
, bind_info
->memoryOffset
);
742 void anv_GetImageSubresourceLayout(
745 const VkImageSubresource
* subresource
,
746 VkSubresourceLayout
* layout
)
748 ANV_FROM_HANDLE(anv_image
, image
, _image
);
749 const struct anv_surface
*surface
=
750 get_surface(image
, subresource
->aspectMask
);
752 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
754 /* If we are on a non-zero mip level or array slice, we need to
755 * calculate a real offset.
757 anv_assert(subresource
->mipLevel
== 0);
758 anv_assert(subresource
->arrayLayer
== 0);
760 layout
->offset
= surface
->offset
;
761 layout
->rowPitch
= surface
->isl
.row_pitch
;
762 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
763 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
764 layout
->size
= surface
->isl
.size
;
768 * This function determines the optimal buffer to use for a given
769 * VkImageLayout and other pieces of information needed to make that
770 * determination. This does not determine the optimal buffer to use
771 * during a resolve operation.
773 * @param devinfo The device information of the Intel GPU.
774 * @param image The image that may contain a collection of buffers.
775 * @param aspect The aspect of the image to be accessed.
776 * @param layout The current layout of the image aspect(s).
778 * @return The primary buffer that should be used for the given layout.
781 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
782 const struct anv_image
* const image
,
783 const VkImageAspectFlagBits aspect
,
784 const VkImageLayout layout
)
786 /* Validate the inputs. */
788 /* The devinfo is needed as the optimal buffer varies across generations. */
789 assert(devinfo
!= NULL
);
791 /* The layout of a NULL image is not properly defined. */
792 assert(image
!= NULL
);
794 /* The aspect must be exactly one of the image aspects. */
795 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
797 /* Determine the optimal buffer. */
799 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
801 /* If there is no auxiliary surface allocated, we must use the one and only
804 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
805 return ISL_AUX_USAGE_NONE
;
807 /* All images that use an auxiliary surface are required to be tiled. */
808 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
810 /* Stencil has no aux */
811 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
815 /* Invalid Layouts */
816 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
817 case VK_IMAGE_LAYOUT_MAX_ENUM
:
818 unreachable("Invalid image layout.");
822 * The pre-initialized layout is equivalent to the undefined layout for
823 * optimally-tiled images. We can only do color compression (CCS or HiZ)
826 case VK_IMAGE_LAYOUT_UNDEFINED
:
827 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
828 return ISL_AUX_USAGE_NONE
;
833 case VK_IMAGE_LAYOUT_GENERAL
:
834 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
835 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
836 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
837 /* This buffer could be a depth buffer used in a transfer operation.
838 * BLORP currently doesn't use HiZ for transfer operations so we must
839 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
841 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
842 return ISL_AUX_USAGE_NONE
;
844 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
845 return image
->planes
[plane
].aux_usage
;
849 /* Sampling Layouts */
850 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
851 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
:
852 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
854 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
855 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
856 if (anv_can_sample_with_hiz(devinfo
, image
))
857 return ISL_AUX_USAGE_HIZ
;
859 return ISL_AUX_USAGE_NONE
;
861 return image
->planes
[plane
].aux_usage
;
865 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
866 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
868 /* On SKL+, the render buffer can be decompressed by the presentation
869 * engine. Support for this feature has not yet landed in the wider
870 * ecosystem. TODO: Update this code when support lands.
872 * From the BDW PRM, Vol 7, Render Target Resolve:
874 * If the MCS is enabled on a non-multisampled render target, the
875 * render target must be resolved before being used for other
876 * purposes (display, texture, CPU lock) The clear value from
877 * SURFACE_STATE is written into pixels in the render target
878 * indicated as clear in the MCS.
880 * Pre-SKL, the render buffer must be resolved before being used for
881 * presentation. We can infer that the auxiliary buffer is not used.
883 return ISL_AUX_USAGE_NONE
;
886 /* Rendering Layouts */
887 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
888 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
889 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
890 assert(image
->samples
== 1);
891 return ISL_AUX_USAGE_CCS_D
;
893 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
894 return image
->planes
[plane
].aux_usage
;
897 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
898 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
:
899 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
900 return ISL_AUX_USAGE_HIZ
;
902 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
903 unreachable("VK_KHR_shared_presentable_image is unsupported");
906 /* If the layout isn't recognized in the exhaustive switch above, the
907 * VkImageLayout value is not defined in vulkan.h.
909 unreachable("layout is not a VkImageLayout enumeration member.");
913 * This function returns the level of unresolved fast-clear support of the
914 * given image in the given VkImageLayout.
916 * @param devinfo The device information of the Intel GPU.
917 * @param image The image that may contain a collection of buffers.
918 * @param aspect The aspect of the image to be accessed.
919 * @param layout The current layout of the image aspect(s).
921 enum anv_fast_clear_type
922 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
923 const struct anv_image
* const image
,
924 const VkImageAspectFlagBits aspect
,
925 const VkImageLayout layout
)
927 /* The aspect must be exactly one of the image aspects. */
928 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
930 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
932 /* If there is no auxiliary surface allocated, there are no fast-clears */
933 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
934 return ANV_FAST_CLEAR_NONE
;
936 /* All images that use an auxiliary surface are required to be tiled. */
937 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
939 /* Stencil has no aux */
940 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
942 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
943 /* For depth images (with HiZ), the layout supports fast-clears if and
944 * only if it supports HiZ. However, we only support fast-clears to the
945 * default depth value.
947 enum isl_aux_usage aux_usage
=
948 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
949 return aux_usage
== ISL_AUX_USAGE_HIZ
?
950 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
953 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
955 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
956 * lack the MI ALU which we need to determine the predicates.
958 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& image
->samples
> 1)
959 return ANV_FAST_CLEAR_NONE
;
962 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
963 return ANV_FAST_CLEAR_ANY
;
965 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
966 return ANV_FAST_CLEAR_NONE
;
969 /* If the image has MCS or CCS_E enabled all the time then we can use
970 * fast-clear as long as the clear color is the default value of zero
971 * since this is the default value we program into every surface state
972 * used for texturing.
974 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_MCS
||
975 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
976 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
978 return ANV_FAST_CLEAR_NONE
;
983 static struct anv_state
984 alloc_surface_state(struct anv_device
*device
)
986 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
989 static enum isl_channel_select
990 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
991 struct isl_swizzle format_swizzle
)
993 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
997 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
998 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
999 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
1000 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
1001 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
1002 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
1004 unreachable("Invalid swizzle");
1009 anv_image_fill_surface_state(struct anv_device
*device
,
1010 const struct anv_image
*image
,
1011 VkImageAspectFlagBits aspect
,
1012 const struct isl_view
*view_in
,
1013 isl_surf_usage_flags_t view_usage
,
1014 enum isl_aux_usage aux_usage
,
1015 const union isl_color_value
*clear_color
,
1016 enum anv_image_view_state_flags flags
,
1017 struct anv_surface_state
*state_inout
,
1018 struct brw_image_param
*image_param_out
)
1020 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1022 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
1023 *aux_surface
= &image
->planes
[plane
].aux_surface
;
1025 struct isl_view view
= *view_in
;
1026 view
.usage
|= view_usage
;
1028 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1029 * compressed surface with a shadow surface, we use the shadow instead of
1030 * the primary surface. The shadow surface will be tiled, unlike the main
1031 * surface, so it should get significantly better performance.
1033 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
1034 isl_format_is_compressed(view
.format
) &&
1035 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
1036 assert(isl_format_is_compressed(surface
->isl
.format
));
1037 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1038 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1039 surface
= &image
->planes
[plane
].shadow_surface
;
1042 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1043 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1045 /* If this is a HiZ buffer we can sample from with a programmable clear
1046 * value (SKL+), define the clear value to the optimal constant.
1048 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1049 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1050 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1052 clear_color
= &default_clear_color
;
1054 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
1055 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
1056 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
1058 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1059 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1060 !isl_has_matching_typed_storage_image_format(&device
->info
,
1062 /* In this case, we are a writeable storage buffer which needs to be
1063 * lowered to linear. All tiling and offset calculations will be done in
1066 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1067 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1069 .size
= surface
->isl
.size
,
1070 .format
= ISL_FORMAT_RAW
,
1072 .mocs
= device
->default_mocs
);
1073 state_inout
->address
= address
,
1074 state_inout
->aux_address
= 0;
1076 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1077 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1078 /* Typed surface reads support a very limited subset of the shader
1079 * image formats. Translate it into the closest format the hardware
1082 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1083 view
.format
= isl_lower_storage_image_format(&device
->info
,
1087 const struct isl_surf
*isl_surf
= &surface
->isl
;
1089 struct isl_surf tmp_surf
;
1090 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1091 if (isl_format_is_compressed(surface
->isl
.format
) &&
1092 !isl_format_is_compressed(view
.format
)) {
1093 /* We're creating an uncompressed view of a compressed surface. This
1094 * is allowed but only for a single level/layer.
1096 assert(surface
->isl
.samples
== 1);
1097 assert(view
.levels
== 1);
1098 assert(view
.array_len
== 1);
1100 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1102 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1103 0 : view
.base_array_layer
,
1104 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1105 view
.base_array_layer
: 0,
1107 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1109 /* The newly created image represents the one subimage we're
1110 * referencing with this view so it only has one array slice and
1113 view
.base_array_layer
= 0;
1114 view
.base_level
= 0;
1116 /* We're making an uncompressed view here. The image dimensions need
1117 * to be scaled down by the block size.
1119 const struct isl_format_layout
*fmtl
=
1120 isl_format_get_layout(surface
->isl
.format
);
1121 tmp_surf
.format
= view
.format
;
1122 tmp_surf
.logical_level0_px
.width
=
1123 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1124 tmp_surf
.logical_level0_px
.height
=
1125 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1126 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1127 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1128 tile_x_sa
/= fmtl
->bw
;
1129 tile_y_sa
/= fmtl
->bh
;
1131 isl_surf
= &tmp_surf
;
1133 if (device
->info
.gen
<= 8) {
1134 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1135 assert(tile_x_sa
== 0);
1136 assert(tile_y_sa
== 0);
1140 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1143 .address
= address
+ offset_B
,
1144 .clear_color
= *clear_color
,
1145 .aux_surf
= &aux_surface
->isl
,
1146 .aux_usage
= aux_usage
,
1147 .aux_address
= aux_address
,
1148 .mocs
= device
->default_mocs
,
1149 .x_offset_sa
= tile_x_sa
,
1150 .y_offset_sa
= tile_y_sa
);
1151 state_inout
->address
= address
+ offset_B
;
1152 if (device
->info
.gen
>= 8) {
1153 state_inout
->aux_address
= aux_address
;
1155 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1156 * used to store other information. This should be ok, however,
1157 * because surface buffer addresses are always 4K page alinged.
1159 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1160 device
->isl_dev
.ss
.aux_addr_offset
;
1161 assert((aux_address
& 0xfff) == 0);
1162 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1163 state_inout
->aux_address
= *aux_addr_dw
;
1167 anv_state_flush(device
, state_inout
->state
);
1169 if (image_param_out
) {
1170 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1171 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1172 &surface
->isl
, &view
);
1176 static VkImageAspectFlags
1177 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1179 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1180 if (_mesa_bitcount(view_aspects
) == 1)
1181 return VK_IMAGE_ASPECT_COLOR_BIT
;
1183 VkImageAspectFlags color_aspects
= 0;
1184 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1185 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT
<< i
;
1186 return color_aspects
;
1188 /* No special remapping needed for depth & stencil aspects. */
1189 return view_aspects
;
1193 anv_CreateImageView(VkDevice _device
,
1194 const VkImageViewCreateInfo
*pCreateInfo
,
1195 const VkAllocationCallbacks
*pAllocator
,
1198 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1199 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1200 struct anv_image_view
*iview
;
1202 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1205 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1207 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1209 assert(range
->layerCount
> 0);
1210 assert(range
->baseMipLevel
< image
->levels
);
1212 const VkImageViewUsageCreateInfo
*usage_info
=
1213 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO
);
1214 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1215 /* View usage should be a subset of image usage */
1216 assert((view_usage
& ~image
->usage
) == 0);
1217 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1218 VK_IMAGE_USAGE_STORAGE_BIT
|
1219 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1220 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1221 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1223 switch (image
->type
) {
1225 unreachable("bad VkImageType");
1226 case VK_IMAGE_TYPE_1D
:
1227 case VK_IMAGE_TYPE_2D
:
1228 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1230 case VK_IMAGE_TYPE_3D
:
1231 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1232 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1236 /* First expand aspects to the image's ones (for example
1237 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1238 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1239 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1240 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1242 VkImageAspectFlags expanded_aspects
=
1243 anv_image_expand_aspects(image
, range
->aspectMask
);
1245 iview
->image
= image
;
1247 /* Remap the expanded aspects for the image view. For example if only
1248 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1249 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1250 * the image view, it only has a single plane.
1252 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1253 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1254 iview
->vk_format
= pCreateInfo
->format
;
1256 iview
->extent
= (VkExtent3D
) {
1257 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1258 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1259 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1262 /* Now go through the underlying image selected planes (computed in
1263 * expanded_aspects) and map them to planes in the image view.
1265 uint32_t iaspect_bit
, vplane
= 0;
1266 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1268 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1269 VkImageAspectFlags vplane_aspect
=
1270 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1271 struct anv_format_plane format
=
1272 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1273 vplane_aspect
, image
->tiling
);
1275 iview
->planes
[vplane
].image_plane
= iplane
;
1277 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1278 .format
= format
.isl_format
,
1279 .base_level
= range
->baseMipLevel
,
1280 .levels
= anv_get_levelCount(image
, range
),
1281 .base_array_layer
= range
->baseArrayLayer
,
1282 .array_len
= anv_get_layerCount(image
, range
),
1284 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1285 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1286 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1287 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1288 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1289 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1290 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1291 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1295 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1296 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1297 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1300 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1301 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1302 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1304 iview
->planes
[vplane
].isl
.usage
= 0;
1307 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1308 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1309 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1310 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1311 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1313 enum isl_aux_usage general_aux_usage
=
1314 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1315 VK_IMAGE_LAYOUT_GENERAL
);
1316 enum isl_aux_usage optimal_aux_usage
=
1317 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1318 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1320 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1321 &iview
->planes
[vplane
].isl
,
1322 ISL_SURF_USAGE_TEXTURE_BIT
,
1323 optimal_aux_usage
, NULL
,
1324 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1325 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1328 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1329 &iview
->planes
[vplane
].isl
,
1330 ISL_SURF_USAGE_TEXTURE_BIT
,
1331 general_aux_usage
, NULL
,
1333 &iview
->planes
[vplane
].general_sampler_surface_state
,
1337 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1338 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1339 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1340 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1342 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1343 &iview
->planes
[vplane
].isl
,
1344 ISL_SURF_USAGE_STORAGE_BIT
,
1345 ISL_AUX_USAGE_NONE
, NULL
,
1347 &iview
->planes
[vplane
].storage_surface_state
,
1348 &iview
->planes
[vplane
].storage_image_param
);
1350 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1351 &iview
->planes
[vplane
].isl
,
1352 ISL_SURF_USAGE_STORAGE_BIT
,
1353 ISL_AUX_USAGE_NONE
, NULL
,
1354 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1355 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1362 *pView
= anv_image_view_to_handle(iview
);
1368 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1369 const VkAllocationCallbacks
*pAllocator
)
1371 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1372 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1377 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1378 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1379 anv_state_pool_free(&device
->surface_state_pool
,
1380 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1383 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1384 anv_state_pool_free(&device
->surface_state_pool
,
1385 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1388 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1389 anv_state_pool_free(&device
->surface_state_pool
,
1390 iview
->planes
[plane
].storage_surface_state
.state
);
1393 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1394 anv_state_pool_free(&device
->surface_state_pool
,
1395 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1399 vk_free2(&device
->alloc
, pAllocator
, iview
);
1404 anv_CreateBufferView(VkDevice _device
,
1405 const VkBufferViewCreateInfo
*pCreateInfo
,
1406 const VkAllocationCallbacks
*pAllocator
,
1407 VkBufferView
*pView
)
1409 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1410 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1411 struct anv_buffer_view
*view
;
1413 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1414 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1416 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1418 /* TODO: Handle the format swizzle? */
1420 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1421 VK_IMAGE_ASPECT_COLOR_BIT
,
1422 VK_IMAGE_TILING_LINEAR
);
1423 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1424 view
->bo
= buffer
->bo
;
1425 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1426 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1427 pCreateInfo
->range
);
1428 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1430 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1431 view
->surface_state
= alloc_surface_state(device
);
1433 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1435 view
->offset
, view
->range
, format_bs
);
1437 view
->surface_state
= (struct anv_state
){ 0 };
1440 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1441 view
->storage_surface_state
= alloc_surface_state(device
);
1442 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1444 enum isl_format storage_format
=
1445 isl_has_matching_typed_storage_image_format(&device
->info
,
1447 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1450 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1452 view
->offset
, view
->range
,
1453 (storage_format
== ISL_FORMAT_RAW
? 1 :
1454 isl_format_get_layout(storage_format
)->bpb
/ 8));
1456 /* Write-only accesses should use the original format. */
1457 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1459 view
->offset
, view
->range
,
1460 isl_format_get_layout(view
->format
)->bpb
/ 8);
1462 isl_buffer_fill_image_param(&device
->isl_dev
,
1463 &view
->storage_image_param
,
1464 view
->format
, view
->range
);
1466 view
->storage_surface_state
= (struct anv_state
){ 0 };
1467 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1470 *pView
= anv_buffer_view_to_handle(view
);
1476 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1477 const VkAllocationCallbacks
*pAllocator
)
1479 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1480 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1485 if (view
->surface_state
.alloc_size
> 0)
1486 anv_state_pool_free(&device
->surface_state_pool
,
1487 view
->surface_state
);
1489 if (view
->storage_surface_state
.alloc_size
> 0)
1490 anv_state_pool_free(&device
->surface_state_pool
,
1491 view
->storage_surface_state
);
1493 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1494 anv_state_pool_free(&device
->surface_state_pool
,
1495 view
->writeonly_storage_surface_state
);
1497 vk_free2(&device
->alloc
, pAllocator
, view
);
1500 const struct anv_surface
*
1501 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1502 VkImageAspectFlags aspect_mask
)
1504 VkImageAspectFlags sanitized_mask
;
1506 switch (aspect_mask
) {
1507 case VK_IMAGE_ASPECT_COLOR_BIT
:
1508 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1509 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1511 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1512 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1513 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1515 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1516 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1517 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1519 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1520 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1521 * combined depth stencil formats. Specifically, it states:
1523 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1524 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1526 * Image views with both depth and stencil aspects are only valid for
1527 * render target attachments, in which case
1528 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1529 * stencil surfaces from the underlying surface.
1531 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1532 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1534 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1535 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1538 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1539 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1540 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT
;
1542 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1543 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1544 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT
;
1546 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1547 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1548 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT
;
1551 unreachable("image does not have aspect");
1555 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1556 return &image
->planes
[plane
].surface
;