2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
96 const struct isl_drm_modifier_info
*isl_mod_info
)
98 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
99 isl_tiling_flags_t flags
= 0;
101 switch (base_info
->tiling
) {
103 unreachable("bad VkImageTiling");
104 case VK_IMAGE_TILING_OPTIMAL
:
105 flags
= ISL_TILING_ANY_MASK
;
107 case VK_IMAGE_TILING_LINEAR
:
108 flags
= ISL_TILING_LINEAR_BIT
;
112 if (anv_info
->isl_tiling_flags
)
113 flags
&= anv_info
->isl_tiling_flags
;
116 flags
&= 1 << isl_mod_info
->tiling
;
123 static struct anv_surface
*
124 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
126 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
127 return &image
->planes
[plane
].surface
;
131 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
133 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
135 if (image
->disjoint
) {
136 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
137 /* Plane offset is always 0 when it's disjoint. */
139 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
140 /* Determine plane's offset only once when the first surface is added. */
141 if (image
->planes
[plane
].size
== 0)
142 image
->planes
[plane
].offset
= image
->size
;
145 image
->size
= surf
->offset
+ surf
->isl
.size
;
146 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
148 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
149 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
150 surf
->isl
.alignment
);
155 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
156 const struct VkImageCreateInfo
*vk_info
)
158 enum isl_format format
=
159 anv_get_isl_format(devinfo
, vk_info
->format
,
160 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
162 if (!isl_format_supports_ccs_e(devinfo
, format
))
165 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
168 const VkImageFormatListCreateInfoKHR
*fmt_list
=
169 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
171 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
174 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
175 enum isl_format view_format
=
176 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
177 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
179 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
187 * For color images that have an auxiliary surface, request allocation for an
188 * additional buffer that mainly stores fast-clear values. Use of this buffer
189 * allows us to access the image's subresources while being aware of their
190 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
191 * which a fast clear has occurred).
193 * For the purpose of discoverability, the algorithm used to manage this buffer
194 * is described here. A clear value in this buffer is updated when a fast clear
195 * is performed on a subresource. One of two synchronization operations is
196 * performed in order for a following memory access to use the fast-clear
198 * a. Copy the value from the buffer to the surface state object used for
199 * reading. This is done implicitly when the value is the clear value
200 * predetermined to be the default in other surface state objects. This
201 * is currently only done explicitly for the operation below.
202 * b. Do (a) and use the surface state object to resolve the subresource.
203 * This is only done during layout transitions for decent performance.
205 * With the above scheme, we can fast-clear whenever the hardware allows except
206 * for two cases in which synchronization becomes impossible or undesirable:
207 * * The subresource is in the GENERAL layout and is cleared to a value
208 * other than the special default value.
210 * Performing a synchronization operation in order to read from the
211 * subresource is undesirable in this case. Firstly, b) is not an option
212 * because a layout transition isn't required between a write and read of
213 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
214 * explicitly because it would require large infrastructural changes. The
215 * Vulkan API supports us in deciding not to optimize this layout by
216 * stating that using this layout may cause suboptimal performance. NOTE:
217 * the auxiliary buffer must always be enabled to support a) implicitly.
220 * * For the given miplevel, only some of the layers are cleared at once.
222 * If the user clears each layer to a different value, then tries to
223 * render to multiple layers at once, we have no ability to perform a
224 * synchronization operation in between. a) is not helpful because the
225 * object can only hold one clear value. b) is not an option because a
226 * layout transition isn't required in this case.
229 add_fast_clear_state_buffer(struct anv_image
*image
,
230 VkImageAspectFlagBits aspect
,
232 const struct anv_device
*device
)
234 assert(image
&& device
);
235 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
236 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
238 /* The offset to the buffer of clear values must be dword-aligned for GPU
239 * memcpy operations. It is located immediately after the auxiliary surface.
242 /* Tiled images are guaranteed to be 4K aligned, so the image alignment
243 * should also be dword-aligned.
245 assert(image
->alignment
% 4 == 0);
247 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
248 * values buffer should already be dword-aligned.
250 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
252 /* This buffer should be at the very end of the plane. */
253 if (image
->disjoint
) {
254 assert(image
->planes
[plane
].size
==
255 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
257 assert(image
->size
==
258 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
261 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
262 /* There's no padding between entries, so ensure that they're always a
263 * multiple of 32 bits in order to enable GPU memcpy operations.
265 assert(entry_size
% 4 == 0);
267 const unsigned plane_state_size
=
268 entry_size
* anv_image_aux_levels(image
, aspect
);
270 image
->planes
[plane
].fast_clear_state_offset
=
271 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
273 image
->planes
[plane
].size
+= plane_state_size
;
274 image
->size
+= plane_state_size
;
278 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
279 * image's memory requirements (that is, the image's size and alignment).
282 make_surface(const struct anv_device
*dev
,
283 struct anv_image
*image
,
284 const struct anv_image_create_info
*anv_info
,
285 isl_tiling_flags_t tiling_flags
,
286 VkImageAspectFlagBits aspect
)
288 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
291 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
292 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
293 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
294 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
297 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
300 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
301 const struct anv_format_plane plane_format
=
302 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
303 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
305 const isl_surf_usage_flags_t usage
=
306 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
307 anv_info
->isl_extra_usage_flags
, aspect
);
309 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
310 * fall back to linear on Broadwell and earlier because we aren't
311 * guaranteed that we can handle offsets correctly. On Sky Lake, the
312 * horizontal and vertical alignments are sufficiently high that we can
313 * just use RENDER_SURFACE_STATE::X/Y Offset.
315 bool needs_shadow
= false;
316 if (dev
->info
.gen
<= 8 &&
317 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
318 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
319 assert(isl_format_is_compressed(plane_format
.isl_format
));
320 tiling_flags
= ISL_TILING_LINEAR_BIT
;
324 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
325 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
326 .format
= plane_format
.isl_format
,
327 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
328 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
329 .depth
= image
->extent
.depth
,
330 .levels
= vk_info
->mipLevels
,
331 .array_len
= vk_info
->arrayLayers
,
332 .samples
= vk_info
->samples
,
334 .row_pitch
= anv_info
->stride
,
336 .tiling_flags
= tiling_flags
);
339 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
341 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
343 add_surface(image
, anv_surf
, plane
);
345 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
346 * create an identical tiled shadow surface for use while texturing so we
347 * don't get garbage performance.
350 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
351 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
353 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
354 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
355 .format
= plane_format
.isl_format
,
356 .width
= image
->extent
.width
,
357 .height
= image
->extent
.height
,
358 .depth
= image
->extent
.depth
,
359 .levels
= vk_info
->mipLevels
,
360 .array_len
= vk_info
->arrayLayers
,
361 .samples
= vk_info
->samples
,
363 .row_pitch
= anv_info
->stride
,
365 .tiling_flags
= ISL_TILING_ANY_MASK
);
367 /* isl_surf_init() will fail only if provided invalid input. Invalid input
368 * is illegal in Vulkan.
372 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
375 /* Add a HiZ surface to a depth buffer that will be used for rendering.
377 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
378 /* We don't advertise that depth buffers could be used as storage
381 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
383 /* Allow the user to control HiZ enabling. Disable by default on gen7
384 * because resolves are not currently implemented pre-BDW.
386 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
387 /* It will never be used as an attachment, HiZ is pointless. */
388 } else if (dev
->info
.gen
== 7) {
389 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
390 } else if (vk_info
->mipLevels
> 1) {
391 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
392 } else if (vk_info
->arrayLayers
> 1) {
393 anv_perf_warn(dev
->instance
, image
,
394 "Implement multi-arrayLayer HiZ clears and resolves");
395 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
396 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
397 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
398 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
399 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
400 &image
->planes
[plane
].surface
.isl
,
401 &image
->planes
[plane
].aux_surface
.isl
);
403 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
404 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
406 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
407 /* TODO: Disallow compression with :
409 * 1) non multiplanar images (We appear to hit a sampler bug with
410 * CCS & R16G16 format. Putting the clear state a page/4096bytes
411 * further fixes the issue).
413 * 2) alias images, because they might be aliases of images
416 * 3) compression disabled by debug
418 const bool allow_compression
=
419 image
->n_planes
== 1 &&
420 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
421 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
423 if (allow_compression
) {
424 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
425 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
426 &image
->planes
[plane
].surface
.isl
,
427 &image
->planes
[plane
].aux_surface
.isl
, 0);
430 /* Disable CCS when it is not useful (i.e., when you can't render
431 * to the image with CCS enabled).
433 if (!isl_format_supports_rendering(&dev
->info
,
434 plane_format
.isl_format
)) {
435 /* While it may be technically possible to enable CCS for this
436 * image, we currently don't have things hooked up to get it
439 anv_perf_warn(dev
->instance
, image
,
440 "This image format doesn't support rendering. "
441 "Not allocating an CCS buffer.");
442 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
446 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
447 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
449 /* For images created without MUTABLE_FORMAT_BIT set, we know that
450 * they will always be used with the original format. In
451 * particular, they will always be used with a format that
452 * supports color compression. If it's never used as a storage
453 * image, then it will only be used through the sampler or the as
454 * a render target. This means that it's safe to just leave
455 * compression on at all times for these formats.
457 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
458 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
459 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
463 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
464 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
465 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
466 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
467 &image
->planes
[plane
].surface
.isl
,
468 &image
->planes
[plane
].aux_surface
.isl
);
470 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
471 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
472 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
476 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
478 /* Upper bound of the last surface should be smaller than the plane's
481 assert((MAX2(image
->planes
[plane
].surface
.offset
,
482 image
->planes
[plane
].aux_surface
.offset
) +
483 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
484 image
->planes
[plane
].aux_surface
.isl
.size
:
485 image
->planes
[plane
].surface
.isl
.size
)) <=
486 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
488 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
489 /* assert(image->planes[plane].fast_clear_state_offset == */
490 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
491 assert(image
->planes
[plane
].fast_clear_state_offset
<
492 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
498 static const struct isl_drm_modifier_info
*
499 get_legacy_scanout_drm_format_mod(VkImageTiling tiling
)
502 case VK_IMAGE_TILING_OPTIMAL
:
503 return isl_drm_modifier_get_info(I915_FORMAT_MOD_X_TILED
);
504 case VK_IMAGE_TILING_LINEAR
:
505 return isl_drm_modifier_get_info(DRM_FORMAT_MOD_LINEAR
);
507 unreachable("bad VkImageTiling");
512 anv_image_create(VkDevice _device
,
513 const struct anv_image_create_info
*create_info
,
514 const VkAllocationCallbacks
* alloc
,
517 ANV_FROM_HANDLE(anv_device
, device
, _device
);
518 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
519 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
520 struct anv_image
*image
= NULL
;
523 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
525 const struct wsi_image_create_info
*wsi_info
=
526 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
527 if (wsi_info
&& wsi_info
->scanout
)
528 isl_mod_info
= get_legacy_scanout_drm_format_mod(pCreateInfo
->tiling
);
530 anv_assert(pCreateInfo
->mipLevels
> 0);
531 anv_assert(pCreateInfo
->arrayLayers
> 0);
532 anv_assert(pCreateInfo
->samples
> 0);
533 anv_assert(pCreateInfo
->extent
.width
> 0);
534 anv_assert(pCreateInfo
->extent
.height
> 0);
535 anv_assert(pCreateInfo
->extent
.depth
> 0);
537 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
538 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
540 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
542 image
->type
= pCreateInfo
->imageType
;
543 image
->extent
= pCreateInfo
->extent
;
544 image
->vk_format
= pCreateInfo
->format
;
545 image
->format
= anv_get_format(pCreateInfo
->format
);
546 image
->aspects
= vk_format_aspects(image
->vk_format
);
547 image
->levels
= pCreateInfo
->mipLevels
;
548 image
->array_size
= pCreateInfo
->arrayLayers
;
549 image
->samples
= pCreateInfo
->samples
;
550 image
->usage
= pCreateInfo
->usage
;
551 image
->tiling
= pCreateInfo
->tiling
;
552 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
553 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
554 DRM_FORMAT_MOD_INVALID
;
556 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
557 assert(format
!= NULL
);
559 const isl_tiling_flags_t isl_tiling_flags
=
560 choose_isl_tiling_flags(create_info
, isl_mod_info
);
562 image
->n_planes
= format
->n_planes
;
565 for_each_bit(b
, image
->aspects
) {
566 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
572 *pImage
= anv_image_to_handle(image
);
578 vk_free2(&device
->alloc
, alloc
, image
);
584 anv_CreateImage(VkDevice device
,
585 const VkImageCreateInfo
*pCreateInfo
,
586 const VkAllocationCallbacks
*pAllocator
,
590 const VkNativeBufferANDROID
*gralloc_info
=
591 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
594 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
598 return anv_image_create(device
,
599 &(struct anv_image_create_info
) {
600 .vk_info
= pCreateInfo
,
607 anv_DestroyImage(VkDevice _device
, VkImage _image
,
608 const VkAllocationCallbacks
*pAllocator
)
610 ANV_FROM_HANDLE(anv_device
, device
, _device
);
611 ANV_FROM_HANDLE(anv_image
, image
, _image
);
616 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
617 if (image
->planes
[p
].bo_is_owned
) {
618 assert(image
->planes
[p
].bo
!= NULL
);
619 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
623 vk_free2(&device
->alloc
, pAllocator
, image
);
626 static void anv_image_bind_memory_plane(struct anv_device
*device
,
627 struct anv_image
*image
,
629 struct anv_device_memory
*memory
,
630 uint32_t memory_offset
)
632 assert(!image
->planes
[plane
].bo_is_owned
);
635 image
->planes
[plane
].bo
= NULL
;
636 image
->planes
[plane
].bo_offset
= 0;
640 image
->planes
[plane
].bo
= memory
->bo
;
641 image
->planes
[plane
].bo_offset
= memory_offset
;
644 VkResult
anv_BindImageMemory(
647 VkDeviceMemory _memory
,
648 VkDeviceSize memoryOffset
)
650 ANV_FROM_HANDLE(anv_device
, device
, _device
);
651 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
652 ANV_FROM_HANDLE(anv_image
, image
, _image
);
655 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
657 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
658 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
664 VkResult
anv_BindImageMemory2KHR(
666 uint32_t bindInfoCount
,
667 const VkBindImageMemoryInfoKHR
* pBindInfos
)
669 ANV_FROM_HANDLE(anv_device
, device
, _device
);
671 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
672 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
673 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
674 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
675 VkImageAspectFlags aspects
= image
->aspects
;
677 vk_foreach_struct_const(s
, bind_info
->pNext
) {
679 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
680 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
681 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
683 aspects
= plane_info
->planeAspect
;
687 anv_debug_ignored_stype(s
->sType
);
693 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
695 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
696 anv_image_bind_memory_plane(device
, image
, plane
,
697 mem
, bind_info
->memoryOffset
);
704 void anv_GetImageSubresourceLayout(
707 const VkImageSubresource
* subresource
,
708 VkSubresourceLayout
* layout
)
710 ANV_FROM_HANDLE(anv_image
, image
, _image
);
711 const struct anv_surface
*surface
=
712 get_surface(image
, subresource
->aspectMask
);
714 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
716 /* If we are on a non-zero mip level or array slice, we need to
717 * calculate a real offset.
719 anv_assert(subresource
->mipLevel
== 0);
720 anv_assert(subresource
->arrayLayer
== 0);
722 layout
->offset
= surface
->offset
;
723 layout
->rowPitch
= surface
->isl
.row_pitch
;
724 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
725 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
726 layout
->size
= surface
->isl
.size
;
730 * This function determines the optimal buffer to use for a given
731 * VkImageLayout and other pieces of information needed to make that
732 * determination. This does not determine the optimal buffer to use
733 * during a resolve operation.
735 * @param devinfo The device information of the Intel GPU.
736 * @param image The image that may contain a collection of buffers.
737 * @param aspect The aspect of the image to be accessed.
738 * @param layout The current layout of the image aspect(s).
740 * @return The primary buffer that should be used for the given layout.
743 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
744 const struct anv_image
* const image
,
745 const VkImageAspectFlagBits aspect
,
746 const VkImageLayout layout
)
748 /* Validate the inputs. */
750 /* The devinfo is needed as the optimal buffer varies across generations. */
751 assert(devinfo
!= NULL
);
753 /* The layout of a NULL image is not properly defined. */
754 assert(image
!= NULL
);
756 /* The aspect must be exactly one of the image aspects. */
757 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
759 /* Determine the optimal buffer. */
761 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
763 /* If there is no auxiliary surface allocated, we must use the one and only
766 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
767 return ISL_AUX_USAGE_NONE
;
769 /* All images that use an auxiliary surface are required to be tiled. */
770 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
772 /* Stencil has no aux */
773 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
777 /* Invalid Layouts */
778 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
779 case VK_IMAGE_LAYOUT_MAX_ENUM
:
780 unreachable("Invalid image layout.");
784 * The pre-initialized layout is equivalent to the undefined layout for
785 * optimally-tiled images. We can only do color compression (CCS or HiZ)
788 case VK_IMAGE_LAYOUT_UNDEFINED
:
789 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
790 return ISL_AUX_USAGE_NONE
;
795 case VK_IMAGE_LAYOUT_GENERAL
:
796 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
797 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
798 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
799 /* This buffer could be a depth buffer used in a transfer operation.
800 * BLORP currently doesn't use HiZ for transfer operations so we must
801 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
803 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
804 return ISL_AUX_USAGE_NONE
;
806 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
807 return image
->planes
[plane
].aux_usage
;
811 /* Sampling Layouts */
812 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
813 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
814 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
816 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
817 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
818 if (anv_can_sample_with_hiz(devinfo
, image
))
819 return ISL_AUX_USAGE_HIZ
;
821 return ISL_AUX_USAGE_NONE
;
823 return image
->planes
[plane
].aux_usage
;
827 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
828 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
830 /* On SKL+, the render buffer can be decompressed by the presentation
831 * engine. Support for this feature has not yet landed in the wider
832 * ecosystem. TODO: Update this code when support lands.
834 * From the BDW PRM, Vol 7, Render Target Resolve:
836 * If the MCS is enabled on a non-multisampled render target, the
837 * render target must be resolved before being used for other
838 * purposes (display, texture, CPU lock) The clear value from
839 * SURFACE_STATE is written into pixels in the render target
840 * indicated as clear in the MCS.
842 * Pre-SKL, the render buffer must be resolved before being used for
843 * presentation. We can infer that the auxiliary buffer is not used.
845 return ISL_AUX_USAGE_NONE
;
848 /* Rendering Layouts */
849 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
850 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
851 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
852 assert(image
->samples
== 1);
853 return ISL_AUX_USAGE_CCS_D
;
855 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
856 return image
->planes
[plane
].aux_usage
;
859 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
860 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
861 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
862 return ISL_AUX_USAGE_HIZ
;
864 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
865 unreachable("VK_KHR_shared_presentable_image is unsupported");
868 /* If the layout isn't recognized in the exhaustive switch above, the
869 * VkImageLayout value is not defined in vulkan.h.
871 unreachable("layout is not a VkImageLayout enumeration member.");
875 * This function returns the level of unresolved fast-clear support of the
876 * given image in the given VkImageLayout.
878 * @param devinfo The device information of the Intel GPU.
879 * @param image The image that may contain a collection of buffers.
880 * @param aspect The aspect of the image to be accessed.
881 * @param layout The current layout of the image aspect(s).
883 enum anv_fast_clear_type
884 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
885 const struct anv_image
* const image
,
886 const VkImageAspectFlagBits aspect
,
887 const VkImageLayout layout
)
889 /* The aspect must be exactly one of the image aspects. */
890 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
892 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
894 /* If there is no auxiliary surface allocated, there are no fast-clears */
895 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
896 return ANV_FAST_CLEAR_NONE
;
898 /* All images that use an auxiliary surface are required to be tiled. */
899 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
901 /* Stencil has no aux */
902 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
904 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
905 /* For depth images (with HiZ), the layout supports fast-clears if and
906 * only if it supports HiZ. However, we only support fast-clears to the
907 * default depth value.
909 enum isl_aux_usage aux_usage
=
910 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
911 return aux_usage
== ISL_AUX_USAGE_HIZ
?
912 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
915 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
917 /* Multisample fast-clear is not yet supported. */
918 if (image
->samples
> 1)
919 return ANV_FAST_CLEAR_NONE
;
922 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
923 return ANV_FAST_CLEAR_ANY
;
925 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
926 return ANV_FAST_CLEAR_NONE
;
929 /* If the image has CCS_E enabled all the time then we can use
930 * fast-clear as long as the clear color is the default value of zero
931 * since this is the default value we program into every surface state
932 * used for texturing.
934 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
935 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
937 return ANV_FAST_CLEAR_NONE
;
942 static struct anv_state
943 alloc_surface_state(struct anv_device
*device
)
945 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
948 static enum isl_channel_select
949 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
950 struct isl_swizzle format_swizzle
)
952 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
956 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
957 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
958 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
959 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
960 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
961 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
963 unreachable("Invalid swizzle");
968 anv_image_fill_surface_state(struct anv_device
*device
,
969 const struct anv_image
*image
,
970 VkImageAspectFlagBits aspect
,
971 const struct isl_view
*view_in
,
972 isl_surf_usage_flags_t view_usage
,
973 enum isl_aux_usage aux_usage
,
974 const union isl_color_value
*clear_color
,
975 enum anv_image_view_state_flags flags
,
976 struct anv_surface_state
*state_inout
,
977 struct brw_image_param
*image_param_out
)
979 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
981 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
982 *aux_surface
= &image
->planes
[plane
].aux_surface
;
984 struct isl_view view
= *view_in
;
985 view
.usage
|= view_usage
;
987 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
988 * compressed surface with a shadow surface, we use the shadow instead of
989 * the primary surface. The shadow surface will be tiled, unlike the main
990 * surface, so it should get significantly better performance.
992 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
993 isl_format_is_compressed(view
.format
) &&
994 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
995 assert(isl_format_is_compressed(surface
->isl
.format
));
996 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
997 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
998 surface
= &image
->planes
[plane
].shadow_surface
;
1001 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1002 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1004 /* If this is a HiZ buffer we can sample from with a programmable clear
1005 * value (SKL+), define the clear value to the optimal constant.
1007 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1008 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1009 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1011 clear_color
= &default_clear_color
;
1013 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
1014 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
1015 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
1017 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1018 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1019 !isl_has_matching_typed_storage_image_format(&device
->info
,
1021 /* In this case, we are a writeable storage buffer which needs to be
1022 * lowered to linear. All tiling and offset calculations will be done in
1025 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1026 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1028 .size
= surface
->isl
.size
,
1029 .format
= ISL_FORMAT_RAW
,
1031 .mocs
= device
->default_mocs
);
1032 state_inout
->address
= address
,
1033 state_inout
->aux_address
= 0;
1035 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1036 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1037 /* Typed surface reads support a very limited subset of the shader
1038 * image formats. Translate it into the closest format the hardware
1041 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1042 view
.format
= isl_lower_storage_image_format(&device
->info
,
1046 const struct isl_surf
*isl_surf
= &surface
->isl
;
1048 struct isl_surf tmp_surf
;
1049 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1050 if (isl_format_is_compressed(surface
->isl
.format
) &&
1051 !isl_format_is_compressed(view
.format
)) {
1052 /* We're creating an uncompressed view of a compressed surface. This
1053 * is allowed but only for a single level/layer.
1055 assert(surface
->isl
.samples
== 1);
1056 assert(view
.levels
== 1);
1057 assert(view
.array_len
== 1);
1059 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1061 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1062 0 : view
.base_array_layer
,
1063 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1064 view
.base_array_layer
: 0,
1066 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1068 /* The newly created image represents the one subimage we're
1069 * referencing with this view so it only has one array slice and
1072 view
.base_array_layer
= 0;
1073 view
.base_level
= 0;
1075 /* We're making an uncompressed view here. The image dimensions need
1076 * to be scaled down by the block size.
1078 const struct isl_format_layout
*fmtl
=
1079 isl_format_get_layout(surface
->isl
.format
);
1080 tmp_surf
.format
= view
.format
;
1081 tmp_surf
.logical_level0_px
.width
=
1082 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1083 tmp_surf
.logical_level0_px
.height
=
1084 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1085 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1086 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1087 tile_x_sa
/= fmtl
->bw
;
1088 tile_y_sa
/= fmtl
->bh
;
1090 isl_surf
= &tmp_surf
;
1092 if (device
->info
.gen
<= 8) {
1093 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1094 assert(tile_x_sa
== 0);
1095 assert(tile_y_sa
== 0);
1099 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1102 .address
= address
+ offset_B
,
1103 .clear_color
= *clear_color
,
1104 .aux_surf
= &aux_surface
->isl
,
1105 .aux_usage
= aux_usage
,
1106 .aux_address
= aux_address
,
1107 .mocs
= device
->default_mocs
,
1108 .x_offset_sa
= tile_x_sa
,
1109 .y_offset_sa
= tile_y_sa
);
1110 state_inout
->address
= address
+ offset_B
;
1111 if (device
->info
.gen
>= 8) {
1112 state_inout
->aux_address
= aux_address
;
1114 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1115 * used to store other information. This should be ok, however,
1116 * because surface buffer addresses are always 4K page alinged.
1118 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1119 device
->isl_dev
.ss
.aux_addr_offset
;
1120 assert((aux_address
& 0xfff) == 0);
1121 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1122 state_inout
->aux_address
= *aux_addr_dw
;
1126 anv_state_flush(device
, state_inout
->state
);
1128 if (image_param_out
) {
1129 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1130 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1131 &surface
->isl
, &view
);
1135 static VkImageAspectFlags
1136 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1138 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1139 if (_mesa_bitcount(view_aspects
) == 1)
1140 return VK_IMAGE_ASPECT_COLOR_BIT
;
1142 VkImageAspectFlags color_aspects
= 0;
1143 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1144 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1145 return color_aspects
;
1147 /* No special remapping needed for depth & stencil aspects. */
1148 return view_aspects
;
1152 anv_CreateImageView(VkDevice _device
,
1153 const VkImageViewCreateInfo
*pCreateInfo
,
1154 const VkAllocationCallbacks
*pAllocator
,
1157 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1158 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1159 struct anv_image_view
*iview
;
1161 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1162 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1164 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1166 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1168 assert(range
->layerCount
> 0);
1169 assert(range
->baseMipLevel
< image
->levels
);
1171 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1172 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1173 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1174 /* View usage should be a subset of image usage */
1175 assert((view_usage
& ~image
->usage
) == 0);
1176 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1177 VK_IMAGE_USAGE_STORAGE_BIT
|
1178 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1179 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1180 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1182 switch (image
->type
) {
1184 unreachable("bad VkImageType");
1185 case VK_IMAGE_TYPE_1D
:
1186 case VK_IMAGE_TYPE_2D
:
1187 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1189 case VK_IMAGE_TYPE_3D
:
1190 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1191 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1195 /* First expand aspects to the image's ones (for example
1196 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1197 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1198 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1199 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1201 VkImageAspectFlags expanded_aspects
=
1202 anv_image_expand_aspects(image
, range
->aspectMask
);
1204 iview
->image
= image
;
1206 /* Remap the expanded aspects for the image view. For example if only
1207 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1208 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1209 * the image view, it only has a single plane.
1211 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1212 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1213 iview
->vk_format
= pCreateInfo
->format
;
1215 iview
->extent
= (VkExtent3D
) {
1216 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1217 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1218 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1221 /* Now go through the underlying image selected planes (computed in
1222 * expanded_aspects) and map them to planes in the image view.
1224 uint32_t iaspect_bit
, vplane
= 0;
1225 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1227 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1228 VkImageAspectFlags vplane_aspect
=
1229 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1230 struct anv_format_plane format
=
1231 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1232 vplane_aspect
, image
->tiling
);
1234 iview
->planes
[vplane
].image_plane
= iplane
;
1236 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1237 .format
= format
.isl_format
,
1238 .base_level
= range
->baseMipLevel
,
1239 .levels
= anv_get_levelCount(image
, range
),
1240 .base_array_layer
= range
->baseArrayLayer
,
1241 .array_len
= anv_get_layerCount(image
, range
),
1243 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1244 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1245 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1246 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1247 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1248 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1249 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1250 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1254 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1255 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1256 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1259 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1260 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1261 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1263 iview
->planes
[vplane
].isl
.usage
= 0;
1266 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1267 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1268 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1269 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1270 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1272 enum isl_aux_usage general_aux_usage
=
1273 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1274 VK_IMAGE_LAYOUT_GENERAL
);
1275 enum isl_aux_usage optimal_aux_usage
=
1276 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1277 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1279 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1280 &iview
->planes
[vplane
].isl
,
1281 ISL_SURF_USAGE_TEXTURE_BIT
,
1282 optimal_aux_usage
, NULL
,
1283 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1284 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1287 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1288 &iview
->planes
[vplane
].isl
,
1289 ISL_SURF_USAGE_TEXTURE_BIT
,
1290 general_aux_usage
, NULL
,
1292 &iview
->planes
[vplane
].general_sampler_surface_state
,
1296 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1297 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1298 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1299 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1301 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1302 &iview
->planes
[vplane
].isl
,
1303 ISL_SURF_USAGE_STORAGE_BIT
,
1304 ISL_AUX_USAGE_NONE
, NULL
,
1306 &iview
->planes
[vplane
].storage_surface_state
,
1307 &iview
->planes
[vplane
].storage_image_param
);
1309 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1310 &iview
->planes
[vplane
].isl
,
1311 ISL_SURF_USAGE_STORAGE_BIT
,
1312 ISL_AUX_USAGE_NONE
, NULL
,
1313 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1314 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1321 *pView
= anv_image_view_to_handle(iview
);
1327 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1328 const VkAllocationCallbacks
*pAllocator
)
1330 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1331 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1336 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1337 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1338 anv_state_pool_free(&device
->surface_state_pool
,
1339 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1342 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1343 anv_state_pool_free(&device
->surface_state_pool
,
1344 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1347 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1348 anv_state_pool_free(&device
->surface_state_pool
,
1349 iview
->planes
[plane
].storage_surface_state
.state
);
1352 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1353 anv_state_pool_free(&device
->surface_state_pool
,
1354 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1358 vk_free2(&device
->alloc
, pAllocator
, iview
);
1363 anv_CreateBufferView(VkDevice _device
,
1364 const VkBufferViewCreateInfo
*pCreateInfo
,
1365 const VkAllocationCallbacks
*pAllocator
,
1366 VkBufferView
*pView
)
1368 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1369 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1370 struct anv_buffer_view
*view
;
1372 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1373 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1375 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1377 /* TODO: Handle the format swizzle? */
1379 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1380 VK_IMAGE_ASPECT_COLOR_BIT
,
1381 VK_IMAGE_TILING_LINEAR
);
1382 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1383 view
->bo
= buffer
->bo
;
1384 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1385 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1386 pCreateInfo
->range
);
1387 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1389 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1390 view
->surface_state
= alloc_surface_state(device
);
1392 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1394 view
->offset
, view
->range
, format_bs
);
1396 view
->surface_state
= (struct anv_state
){ 0 };
1399 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1400 view
->storage_surface_state
= alloc_surface_state(device
);
1401 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1403 enum isl_format storage_format
=
1404 isl_has_matching_typed_storage_image_format(&device
->info
,
1406 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1409 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1411 view
->offset
, view
->range
,
1412 (storage_format
== ISL_FORMAT_RAW
? 1 :
1413 isl_format_get_layout(storage_format
)->bpb
/ 8));
1415 /* Write-only accesses should use the original format. */
1416 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1418 view
->offset
, view
->range
,
1419 isl_format_get_layout(view
->format
)->bpb
/ 8);
1421 isl_buffer_fill_image_param(&device
->isl_dev
,
1422 &view
->storage_image_param
,
1423 view
->format
, view
->range
);
1425 view
->storage_surface_state
= (struct anv_state
){ 0 };
1426 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1429 *pView
= anv_buffer_view_to_handle(view
);
1435 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1436 const VkAllocationCallbacks
*pAllocator
)
1438 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1439 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1444 if (view
->surface_state
.alloc_size
> 0)
1445 anv_state_pool_free(&device
->surface_state_pool
,
1446 view
->surface_state
);
1448 if (view
->storage_surface_state
.alloc_size
> 0)
1449 anv_state_pool_free(&device
->surface_state_pool
,
1450 view
->storage_surface_state
);
1452 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1453 anv_state_pool_free(&device
->surface_state_pool
,
1454 view
->writeonly_storage_surface_state
);
1456 vk_free2(&device
->alloc
, pAllocator
, view
);
1459 const struct anv_surface
*
1460 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1461 VkImageAspectFlags aspect_mask
)
1463 VkImageAspectFlags sanitized_mask
;
1465 switch (aspect_mask
) {
1466 case VK_IMAGE_ASPECT_COLOR_BIT
:
1467 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1468 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1470 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1471 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1472 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1474 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1475 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1476 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1478 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1479 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1480 * combined depth stencil formats. Specifically, it states:
1482 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1483 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1485 * Image views with both depth and stencil aspects are only valid for
1486 * render target attachments, in which case
1487 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1488 * stencil surfaces from the underlying surface.
1490 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1491 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1493 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1494 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1497 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1498 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1499 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1501 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1502 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1503 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1505 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1506 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1507 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1510 unreachable("image does not have aspect");
1514 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1515 return &image
->planes
[plane
].surface
;