8db77b1fdcc03548c6dfa7918a28cfd0d355761e
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29 #include <sys/mman.h>
30 #include "drm-uapi/drm_fourcc.h"
31
32 #include "anv_private.h"
33 #include "util/debug.h"
34 #include "vk_util.h"
35 #include "util/u_math.h"
36
37 #include "vk_format_info.h"
38
39 static isl_surf_usage_flags_t
40 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
41 VkImageUsageFlags vk_usage,
42 isl_surf_usage_flags_t isl_extra_usage,
43 VkImageAspectFlagBits aspect)
44 {
45 isl_surf_usage_flags_t isl_usage = isl_extra_usage;
46
47 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
48 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
49
50 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
51 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
52
53 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
54 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
55
56 if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
57 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
58
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
62 */
63 switch (aspect) {
64 case VK_IMAGE_ASPECT_DEPTH_BIT:
65 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
66 break;
67 case VK_IMAGE_ASPECT_STENCIL_BIT:
68 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
69 break;
70 case VK_IMAGE_ASPECT_COLOR_BIT:
71 case VK_IMAGE_ASPECT_PLANE_0_BIT:
72 case VK_IMAGE_ASPECT_PLANE_1_BIT:
73 case VK_IMAGE_ASPECT_PLANE_2_BIT:
74 break;
75 default:
76 unreachable("bad VkImageAspect");
77 }
78
79 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
80 /* blorp implements transfers by sampling from the source image. */
81 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
82 }
83
84 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
85 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
86 /* blorp implements transfers by rendering into the destination image.
87 * Only request this with color images, as we deal with depth/stencil
88 * formats differently. */
89 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
90 }
91
92 return isl_usage;
93 }
94
95 static isl_tiling_flags_t
96 choose_isl_tiling_flags(const struct anv_image_create_info *anv_info,
97 const struct isl_drm_modifier_info *isl_mod_info,
98 bool legacy_scanout)
99 {
100 const VkImageCreateInfo *base_info = anv_info->vk_info;
101 isl_tiling_flags_t flags = 0;
102
103 switch (base_info->tiling) {
104 default:
105 unreachable("bad VkImageTiling");
106 case VK_IMAGE_TILING_OPTIMAL:
107 flags = ISL_TILING_ANY_MASK;
108 break;
109 case VK_IMAGE_TILING_LINEAR:
110 flags = ISL_TILING_LINEAR_BIT;
111 break;
112 case VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT:
113 assert(isl_mod_info);
114 flags = 1 << isl_mod_info->tiling;
115 }
116
117 if (anv_info->isl_tiling_flags)
118 flags &= anv_info->isl_tiling_flags;
119
120 if (legacy_scanout)
121 flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT;
122
123 assert(flags);
124
125 return flags;
126 }
127
128 static void
129 add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
130 {
131 assert(surf->isl.size_B > 0); /* isl surface must be initialized */
132
133 if (image->disjoint) {
134 surf->offset = align_u32(image->planes[plane].size,
135 surf->isl.alignment_B);
136 /* Plane offset is always 0 when it's disjoint. */
137 } else {
138 surf->offset = align_u32(image->size, surf->isl.alignment_B);
139 /* Determine plane's offset only once when the first surface is added. */
140 if (image->planes[plane].size == 0)
141 image->planes[plane].offset = image->size;
142 }
143
144 image->size = surf->offset + surf->isl.size_B;
145 image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
146
147 image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
148 image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
149 surf->isl.alignment_B);
150 }
151
152 /**
153 * Do hardware limitations require the image plane to use a shadow surface?
154 *
155 * If hardware limitations force us to use a shadow surface, then the same
156 * limitations may also constrain the tiling of the primary surface; therefore
157 * paramater @a inout_primary_tiling_flags.
158 *
159 * If the image plane is a separate stencil plane and if the user provided
160 * VkImageStencilUsageCreateInfoEXT, then @a usage must be stencilUsage.
161 *
162 * @see anv_image::planes[]::shadow_surface
163 */
164 static bool
165 anv_image_plane_needs_shadow_surface(const struct gen_device_info *devinfo,
166 struct anv_format_plane plane_format,
167 VkImageTiling vk_tiling,
168 VkImageUsageFlags vk_plane_usage,
169 VkImageCreateFlags vk_create_flags,
170 isl_tiling_flags_t *inout_primary_tiling_flags)
171 {
172 if (devinfo->gen <= 8 &&
173 (vk_create_flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
174 vk_tiling == VK_IMAGE_TILING_OPTIMAL) {
175 /* We must fallback to a linear surface because we may not be able to
176 * correctly handle the offsets if tiled. (On gen9,
177 * RENDER_SURFACE_STATE::X/Y Offset are sufficient). To prevent garbage
178 * performance while texturing, we maintain a tiled shadow surface.
179 */
180 assert(isl_format_is_compressed(plane_format.isl_format));
181
182 if (inout_primary_tiling_flags) {
183 *inout_primary_tiling_flags = ISL_TILING_LINEAR_BIT;
184 }
185
186 return true;
187 }
188
189 if (devinfo->gen <= 7 &&
190 plane_format.aspect == VK_IMAGE_ASPECT_STENCIL_BIT &&
191 (vk_plane_usage & VK_IMAGE_USAGE_SAMPLED_BIT)) {
192 /* gen7 can't sample from W-tiled surfaces. */
193 return true;
194 }
195
196 return false;
197 }
198
199 bool
200 anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
201 VkImageCreateFlags create_flags,
202 VkFormat vk_format,
203 VkImageTiling vk_tiling,
204 const VkImageFormatListCreateInfoKHR *fmt_list)
205 {
206 enum isl_format format =
207 anv_get_isl_format(devinfo, vk_format,
208 VK_IMAGE_ASPECT_COLOR_BIT, vk_tiling);
209
210 if (!isl_format_supports_ccs_e(devinfo, format))
211 return false;
212
213 if (!(create_flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT))
214 return true;
215
216 if (!fmt_list || fmt_list->viewFormatCount == 0)
217 return false;
218
219 for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) {
220 enum isl_format view_format =
221 anv_get_isl_format(devinfo, fmt_list->pViewFormats[i],
222 VK_IMAGE_ASPECT_COLOR_BIT, vk_tiling);
223
224 if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format))
225 return false;
226 }
227
228 return true;
229 }
230
231 /**
232 * For color images that have an auxiliary surface, request allocation for an
233 * additional buffer that mainly stores fast-clear values. Use of this buffer
234 * allows us to access the image's subresources while being aware of their
235 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
236 * which a fast clear has occurred).
237 *
238 * In order to avoid having multiple clear colors for a single plane of an
239 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
240 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
241 * 2018), there were no known applications which would benefit from fast-
242 * clearing more than just the first slice.
243 *
244 * The fast clear portion of the image is laid out in the following order:
245 *
246 * * 1 or 4 dwords (depending on hardware generation) for the clear color
247 * * 1 dword for the anv_fast_clear_type of the clear color
248 * * On gen9+, 1 dword per level and layer of the image (3D levels count
249 * multiple layers) in level-major order for compression state.
250 *
251 * For the purpose of discoverability, the algorithm used to manage
252 * compression and fast-clears is described here:
253 *
254 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
255 * all of the values in the fast clear portion of the image are initialized
256 * to default values.
257 *
258 * * On fast-clear, the clear value is written into surface state and also
259 * into the buffer and the fast clear type is set appropriately. Both
260 * setting the fast-clear value in the buffer and setting the fast-clear
261 * type happen from the GPU using MI commands.
262 *
263 * * Whenever a render or blorp operation is performed with CCS_E, we call
264 * genX(cmd_buffer_mark_image_written) to set the compression state to
265 * true (which is represented by UINT32_MAX).
266 *
267 * * On pipeline barrier transitions, the worst-case transition is computed
268 * from the image layouts. The command streamer inspects the fast clear
269 * type and compression state dwords and constructs a predicate. The
270 * worst-case resolve is performed with the given predicate and the fast
271 * clear and compression state is set accordingly.
272 *
273 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
274 * details on exactly what is allowed in what layouts.
275 *
276 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
277 * In order to deal with this, we have to do some clear color management.
278 *
279 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
280 * value from the buffer into the surface state with MI commands.
281 *
282 * * For any blorp operations, we pass the address to the clear value into
283 * blorp and it knows to copy the clear color.
284 */
285 static void
286 add_aux_state_tracking_buffer(struct anv_image *image,
287 uint32_t plane,
288 const struct anv_device *device)
289 {
290 assert(image && device);
291 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE &&
292 image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
293
294 /* Compressed images must be tiled and therefore everything should be 4K
295 * aligned. The CCS has the same alignment requirements. This is good
296 * because we need at least dword-alignment for MI_LOAD/STORE operations.
297 */
298 assert(image->alignment % 4 == 0);
299 assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0);
300
301 /* This buffer should be at the very end of the plane. */
302 if (image->disjoint) {
303 assert(image->planes[plane].size ==
304 (image->planes[plane].offset + image->planes[plane].size));
305 } else {
306 assert(image->size ==
307 (image->planes[plane].offset + image->planes[plane].size));
308 }
309
310 const unsigned clear_color_state_size = device->info.gen >= 10 ?
311 device->isl_dev.ss.clear_color_state_size :
312 device->isl_dev.ss.clear_value_size;
313
314 /* Clear color and fast clear type */
315 unsigned state_size = clear_color_state_size + 4;
316
317 /* We only need to track compression on CCS_E surfaces. */
318 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
319 if (image->type == VK_IMAGE_TYPE_3D) {
320 for (uint32_t l = 0; l < image->levels; l++)
321 state_size += anv_minify(image->extent.depth, l) * 4;
322 } else {
323 state_size += image->levels * image->array_size * 4;
324 }
325 }
326
327 /* Add some padding to make sure the fast clear color state buffer starts at
328 * a 4K alignment. We believe that 256B might be enough, but due to lack of
329 * testing we will leave this as 4K for now.
330 */
331 image->planes[plane].size = ALIGN(image->planes[plane].size, 4096);
332 image->size = ALIGN(image->size, 4096);
333
334 assert(image->planes[plane].offset % 4096 == 0);
335
336 image->planes[plane].fast_clear_state_offset =
337 image->planes[plane].offset + image->planes[plane].size;
338
339 image->planes[plane].size += state_size;
340 image->size += state_size;
341 }
342
343 /**
344 * The return code indicates whether creation of the VkImage should continue
345 * or fail, not whether the creation of the aux surface succeeded. If the aux
346 * surface is not required (for example, by neither hardware nor DRM format
347 * modifier), then this may return VK_SUCCESS when creation of the aux surface
348 * fails.
349 */
350 static VkResult
351 add_aux_surface_if_supported(struct anv_device *device,
352 struct anv_image *image,
353 uint32_t plane,
354 struct anv_format_plane plane_format,
355 const VkImageFormatListCreateInfoKHR *fmt_list,
356 isl_surf_usage_flags_t isl_extra_usage_flags)
357 {
358 VkImageAspectFlags aspect = plane_format.aspect;
359 bool ok;
360
361 /* The aux surface must not be already added. */
362 assert(image->planes[plane].aux_surface.isl.size_B == 0);
363
364 if ((isl_extra_usage_flags & ISL_SURF_USAGE_DISABLE_AUX_BIT)) {
365 /* Nevermind. No aux surface. */
366 } else if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
367 /* We don't advertise that depth buffers could be used as storage
368 * images.
369 */
370 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
371
372 /* Allow the user to control HiZ enabling. Disable by default on gen7
373 * because resolves are not currently implemented pre-BDW.
374 */
375 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
376 /* It will never be used as an attachment, HiZ is pointless. */
377 } else if (device->info.gen == 7) {
378 anv_perf_warn(device, image, "Implement gen7 HiZ");
379 } else if (image->levels > 1) {
380 anv_perf_warn(device, image, "Enable multi-LOD HiZ");
381 } else if (image->array_size > 1) {
382 anv_perf_warn(device, image,
383 "Implement multi-arrayLayer HiZ clears and resolves");
384 } else if (device->info.gen == 8 && image->samples > 1) {
385 anv_perf_warn(device, image, "Enable gen8 multisampled HiZ");
386 } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
387 ok = isl_surf_get_hiz_surf(&device->isl_dev,
388 &image->planes[plane].surface.isl,
389 &image->planes[plane].aux_surface.isl);
390 assert(ok);
391 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
392 add_surface(image, &image->planes[plane].aux_surface, plane);
393 }
394 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples == 1) {
395 /* TODO: Disallow compression with :
396 *
397 * 1) non multiplanar images (We appear to hit a sampler bug with
398 * CCS & R16G16 format. Putting the clear state a page/4096bytes
399 * further fixes the issue).
400 *
401 * 2) alias images, because they might be aliases of images
402 * described in 1)
403 *
404 * 3) compression disabled by debug
405 */
406 const bool allow_compression =
407 image->n_planes == 1 &&
408 (image->create_flags & VK_IMAGE_CREATE_ALIAS_BIT) == 0 &&
409 likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
410
411 if (allow_compression) {
412 ok = isl_surf_get_ccs_surf(&device->isl_dev,
413 &image->planes[plane].surface.isl,
414 &image->planes[plane].aux_surface.isl,
415 NULL, 0);
416 if (ok) {
417
418 /* Disable CCS when it is not useful (i.e., when you can't render
419 * to the image with CCS enabled).
420 */
421 if (!isl_format_supports_rendering(&device->info,
422 plane_format.isl_format)) {
423 /* While it may be technically possible to enable CCS for this
424 * image, we currently don't have things hooked up to get it
425 * working.
426 */
427 anv_perf_warn(device, image,
428 "This image format doesn't support rendering. "
429 "Not allocating an CCS buffer.");
430 image->planes[plane].aux_surface.isl.size_B = 0;
431 return VK_SUCCESS;
432 }
433
434 /* For images created without MUTABLE_FORMAT_BIT set, we know that
435 * they will always be used with the original format. In
436 * particular, they will always be used with a format that
437 * supports color compression. If it's never used as a storage
438 * image, then it will only be used through the sampler or the as
439 * a render target. This means that it's safe to just leave
440 * compression on at all times for these formats.
441 */
442 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
443 anv_formats_ccs_e_compatible(&device->info,
444 image->create_flags,
445 image->vk_format,
446 image->tiling,
447 fmt_list)) {
448 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E;
449 } else if (device->info.gen >= 12) {
450 anv_perf_warn(device, image,
451 "The CCS_D aux mode is not yet handled on "
452 "Gen12+. Not allocating a CCS buffer.");
453 image->planes[plane].aux_surface.isl.size_B = 0;
454 return VK_SUCCESS;
455 } else {
456 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_D;
457 }
458
459 if (!device->physical->has_implicit_ccs)
460 add_surface(image, &image->planes[plane].aux_surface, plane);
461
462 add_aux_state_tracking_buffer(image, plane, device);
463 }
464 }
465 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples > 1) {
466 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
467 ok = isl_surf_get_mcs_surf(&device->isl_dev,
468 &image->planes[plane].surface.isl,
469 &image->planes[plane].aux_surface.isl);
470 if (ok) {
471 image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
472 add_surface(image, &image->planes[plane].aux_surface, plane);
473 add_aux_state_tracking_buffer(image, plane, device);
474 }
475 }
476
477 return VK_SUCCESS;
478 }
479
480 /**
481 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
482 * image's memory requirements (that is, the image's size and alignment).
483 */
484 static VkResult
485 make_surface(struct anv_device *device,
486 struct anv_image *image,
487 const VkImageFormatListCreateInfoKHR *fmt_list,
488 uint32_t stride,
489 isl_tiling_flags_t tiling_flags,
490 isl_surf_usage_flags_t isl_extra_usage_flags,
491 VkImageAspectFlagBits aspect)
492 {
493 VkResult result;
494 bool ok;
495
496 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
497 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
498 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
499 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
500 };
501
502 image->extent = anv_sanitize_image_extent(image->type, image->extent);
503
504 const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect);
505 const struct anv_format_plane plane_format =
506 anv_get_format_plane(&device->info, image->vk_format, aspect, image->tiling);
507 struct anv_surface *anv_surf = &image->planes[plane].surface;
508
509 const isl_surf_usage_flags_t usage =
510 choose_isl_surf_usage(image->create_flags, image->usage,
511 isl_extra_usage_flags, aspect);
512
513 VkImageUsageFlags plane_vk_usage =
514 aspect == VK_IMAGE_ASPECT_STENCIL_BIT ?
515 image->stencil_usage : image->usage;
516
517 bool needs_shadow =
518 anv_image_plane_needs_shadow_surface(&device->info,
519 plane_format,
520 image->tiling,
521 plane_vk_usage,
522 image->create_flags,
523 &tiling_flags);
524
525 ok = isl_surf_init(&device->isl_dev, &anv_surf->isl,
526 .dim = vk_to_isl_surf_dim[image->type],
527 .format = plane_format.isl_format,
528 .width = image->extent.width / plane_format.denominator_scales[0],
529 .height = image->extent.height / plane_format.denominator_scales[1],
530 .depth = image->extent.depth,
531 .levels = image->levels,
532 .array_len = image->array_size,
533 .samples = image->samples,
534 .min_alignment_B = 0,
535 .row_pitch_B = stride,
536 .usage = usage,
537 .tiling_flags = tiling_flags);
538
539 if (!ok)
540 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
541
542 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
543
544 add_surface(image, anv_surf, plane);
545
546 if (needs_shadow) {
547 ok = isl_surf_init(&device->isl_dev, &image->planes[plane].shadow_surface.isl,
548 .dim = vk_to_isl_surf_dim[image->type],
549 .format = plane_format.isl_format,
550 .width = image->extent.width,
551 .height = image->extent.height,
552 .depth = image->extent.depth,
553 .levels = image->levels,
554 .array_len = image->array_size,
555 .samples = image->samples,
556 .min_alignment_B = 0,
557 .row_pitch_B = stride,
558 .usage = ISL_SURF_USAGE_TEXTURE_BIT |
559 (usage & ISL_SURF_USAGE_CUBE_BIT),
560 .tiling_flags = ISL_TILING_ANY_MASK);
561
562 /* isl_surf_init() will fail only if provided invalid input. Invalid input
563 * is illegal in Vulkan.
564 */
565 assert(ok);
566
567 add_surface(image, &image->planes[plane].shadow_surface, plane);
568 }
569
570 result = add_aux_surface_if_supported(device, image, plane, plane_format,
571 fmt_list, isl_extra_usage_flags);
572 if (result != VK_SUCCESS)
573 return result;
574
575 assert((image->planes[plane].offset + image->planes[plane].size) == image->size);
576
577 /* Upper bound of the last surface should be smaller than the plane's
578 * size.
579 */
580 assert((MAX2(image->planes[plane].surface.offset,
581 image->planes[plane].aux_surface.offset) +
582 (image->planes[plane].aux_surface.isl.size_B > 0 ?
583 image->planes[plane].aux_surface.isl.size_B :
584 image->planes[plane].surface.isl.size_B)) <=
585 (image->planes[plane].offset + image->planes[plane].size));
586
587 if (image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE) {
588 /* assert(image->planes[plane].fast_clear_state_offset == */
589 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
590 assert(image->planes[plane].fast_clear_state_offset <
591 (image->planes[plane].offset + image->planes[plane].size));
592 }
593
594 return VK_SUCCESS;
595 }
596
597 static uint32_t
598 score_drm_format_mod(uint64_t modifier)
599 {
600 switch (modifier) {
601 case DRM_FORMAT_MOD_LINEAR: return 1;
602 case I915_FORMAT_MOD_X_TILED: return 2;
603 case I915_FORMAT_MOD_Y_TILED: return 3;
604 case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
605 default: unreachable("bad DRM format modifier");
606 }
607 }
608
609 static const struct isl_drm_modifier_info *
610 choose_drm_format_mod(const struct anv_physical_device *device,
611 uint32_t modifier_count, const uint64_t *modifiers)
612 {
613 uint64_t best_mod = UINT64_MAX;
614 uint32_t best_score = 0;
615
616 for (uint32_t i = 0; i < modifier_count; ++i) {
617 uint32_t score = score_drm_format_mod(modifiers[i]);
618 if (score > best_score) {
619 best_mod = modifiers[i];
620 best_score = score;
621 }
622 }
623
624 if (best_score > 0)
625 return isl_drm_modifier_get_info(best_mod);
626 else
627 return NULL;
628 }
629
630 VkResult
631 anv_image_create(VkDevice _device,
632 const struct anv_image_create_info *create_info,
633 const VkAllocationCallbacks* alloc,
634 VkImage *pImage)
635 {
636 ANV_FROM_HANDLE(anv_device, device, _device);
637 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
638 const struct isl_drm_modifier_info *isl_mod_info = NULL;
639 struct anv_image *image = NULL;
640 VkResult r;
641
642 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
643
644 const struct wsi_image_create_info *wsi_info =
645 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
646
647 if (pCreateInfo->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
648 const VkImageDrmFormatModifierListCreateInfoEXT *mod_info =
649 vk_find_struct_const(pCreateInfo->pNext,
650 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT);
651 isl_mod_info = choose_drm_format_mod(device->physical,
652 mod_info->drmFormatModifierCount,
653 mod_info->pDrmFormatModifiers);
654 assert(isl_mod_info);
655 }
656
657 anv_assert(pCreateInfo->mipLevels > 0);
658 anv_assert(pCreateInfo->arrayLayers > 0);
659 anv_assert(pCreateInfo->samples > 0);
660 anv_assert(pCreateInfo->extent.width > 0);
661 anv_assert(pCreateInfo->extent.height > 0);
662 anv_assert(pCreateInfo->extent.depth > 0);
663
664 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
665 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
666 if (!image)
667 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
668
669 image->type = pCreateInfo->imageType;
670 image->extent = pCreateInfo->extent;
671 image->vk_format = pCreateInfo->format;
672 image->format = anv_get_format(pCreateInfo->format);
673 image->aspects = vk_format_aspects(image->vk_format);
674 image->levels = pCreateInfo->mipLevels;
675 image->array_size = pCreateInfo->arrayLayers;
676 image->samples = pCreateInfo->samples;
677 image->usage = pCreateInfo->usage;
678 image->create_flags = pCreateInfo->flags;
679 image->tiling = pCreateInfo->tiling;
680 image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT;
681 image->needs_set_tiling = wsi_info && wsi_info->scanout;
682 image->drm_format_mod = isl_mod_info ? isl_mod_info->modifier :
683 DRM_FORMAT_MOD_INVALID;
684
685 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
686 image->stencil_usage = pCreateInfo->usage;
687 const VkImageStencilUsageCreateInfoEXT *stencil_usage_info =
688 vk_find_struct_const(pCreateInfo->pNext,
689 IMAGE_STENCIL_USAGE_CREATE_INFO_EXT);
690 if (stencil_usage_info)
691 image->stencil_usage = stencil_usage_info->stencilUsage;
692 }
693
694 /* In case of external format, We don't know format yet,
695 * so skip the rest for now.
696 */
697 if (create_info->external_format) {
698 image->external_format = true;
699 *pImage = anv_image_to_handle(image);
700 return VK_SUCCESS;
701 }
702
703 const struct anv_format *format = anv_get_format(image->vk_format);
704 assert(format != NULL);
705
706 const isl_tiling_flags_t isl_tiling_flags =
707 choose_isl_tiling_flags(create_info, isl_mod_info,
708 image->needs_set_tiling);
709
710 image->n_planes = format->n_planes;
711
712 const VkImageFormatListCreateInfoKHR *fmt_list =
713 vk_find_struct_const(pCreateInfo->pNext,
714 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
715
716 uint32_t b;
717 for_each_bit(b, image->aspects) {
718 r = make_surface(device, image, fmt_list, create_info->stride,
719 isl_tiling_flags, create_info->isl_extra_usage_flags,
720 (1 << b));
721 if (r != VK_SUCCESS)
722 goto fail;
723 }
724
725 *pImage = anv_image_to_handle(image);
726
727 return VK_SUCCESS;
728
729 fail:
730 if (image)
731 vk_free2(&device->alloc, alloc, image);
732
733 return r;
734 }
735
736 static struct anv_image *
737 anv_swapchain_get_image(VkSwapchainKHR swapchain,
738 uint32_t index)
739 {
740 uint32_t n_images = index + 1;
741 VkImage *images = malloc(sizeof(*images) * n_images);
742 VkResult result = wsi_common_get_images(swapchain, &n_images, images);
743
744 if (result != VK_SUCCESS && result != VK_INCOMPLETE) {
745 free(images);
746 return NULL;
747 }
748
749 ANV_FROM_HANDLE(anv_image, image, images[index]);
750 free(images);
751
752 return image;
753 }
754
755 static VkResult
756 anv_image_from_swapchain(VkDevice device,
757 const VkImageCreateInfo *pCreateInfo,
758 const VkImageSwapchainCreateInfoKHR *swapchain_info,
759 const VkAllocationCallbacks *pAllocator,
760 VkImage *pImage)
761 {
762 struct anv_image *swapchain_image = anv_swapchain_get_image(swapchain_info->swapchain, 0);
763 assert(swapchain_image);
764
765 assert(swapchain_image->type == pCreateInfo->imageType);
766 assert(swapchain_image->vk_format == pCreateInfo->format);
767 assert(swapchain_image->extent.width == pCreateInfo->extent.width);
768 assert(swapchain_image->extent.height == pCreateInfo->extent.height);
769 assert(swapchain_image->extent.depth == pCreateInfo->extent.depth);
770 assert(swapchain_image->array_size == pCreateInfo->arrayLayers);
771 /* Color attachment is added by the wsi code. */
772 assert(swapchain_image->usage == (pCreateInfo->usage | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT));
773
774 VkImageCreateInfo local_create_info;
775 local_create_info = *pCreateInfo;
776 local_create_info.pNext = NULL;
777 /* The following parameters are implictly selected by the wsi code. */
778 local_create_info.tiling = VK_IMAGE_TILING_OPTIMAL;
779 local_create_info.samples = VK_SAMPLE_COUNT_1_BIT;
780 local_create_info.usage |= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
781
782 /* If the image has a particular modifier, specify that modifier. */
783 VkImageDrmFormatModifierListCreateInfoEXT local_modifier_info = {
784 .sType = VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT,
785 .drmFormatModifierCount = 1,
786 .pDrmFormatModifiers = &swapchain_image->drm_format_mod,
787 };
788 if (swapchain_image->drm_format_mod != DRM_FORMAT_MOD_INVALID)
789 __vk_append_struct(&local_create_info, &local_modifier_info);
790
791 return anv_image_create(device,
792 &(struct anv_image_create_info) {
793 .vk_info = &local_create_info,
794 .external_format = swapchain_image->external_format,
795 },
796 pAllocator,
797 pImage);
798 }
799
800 VkResult
801 anv_CreateImage(VkDevice device,
802 const VkImageCreateInfo *pCreateInfo,
803 const VkAllocationCallbacks *pAllocator,
804 VkImage *pImage)
805 {
806 const VkExternalMemoryImageCreateInfo *create_info =
807 vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_MEMORY_IMAGE_CREATE_INFO);
808
809 if (create_info && (create_info->handleTypes &
810 VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))
811 return anv_image_from_external(device, pCreateInfo, create_info,
812 pAllocator, pImage);
813
814 bool use_external_format = false;
815 const VkExternalFormatANDROID *ext_format =
816 vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_FORMAT_ANDROID);
817
818 /* "If externalFormat is zero, the effect is as if the
819 * VkExternalFormatANDROID structure was not present. Otherwise, the image
820 * will have the specified external format."
821 */
822 if (ext_format && ext_format->externalFormat != 0)
823 use_external_format = true;
824
825 const VkNativeBufferANDROID *gralloc_info =
826 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
827 if (gralloc_info)
828 return anv_image_from_gralloc(device, pCreateInfo, gralloc_info,
829 pAllocator, pImage);
830
831 const VkImageSwapchainCreateInfoKHR *swapchain_info =
832 vk_find_struct_const(pCreateInfo->pNext, IMAGE_SWAPCHAIN_CREATE_INFO_KHR);
833 if (swapchain_info && swapchain_info->swapchain != VK_NULL_HANDLE)
834 return anv_image_from_swapchain(device, pCreateInfo, swapchain_info,
835 pAllocator, pImage);
836
837 return anv_image_create(device,
838 &(struct anv_image_create_info) {
839 .vk_info = pCreateInfo,
840 .external_format = use_external_format,
841 },
842 pAllocator,
843 pImage);
844 }
845
846 void
847 anv_DestroyImage(VkDevice _device, VkImage _image,
848 const VkAllocationCallbacks *pAllocator)
849 {
850 ANV_FROM_HANDLE(anv_device, device, _device);
851 ANV_FROM_HANDLE(anv_image, image, _image);
852
853 if (!image)
854 return;
855
856 for (uint32_t p = 0; p < image->n_planes; ++p) {
857 if (image->planes[p].bo_is_owned) {
858 assert(image->planes[p].address.bo != NULL);
859 anv_device_release_bo(device, image->planes[p].address.bo);
860 }
861 }
862
863 vk_free2(&device->alloc, pAllocator, image);
864 }
865
866 static void anv_image_bind_memory_plane(struct anv_device *device,
867 struct anv_image *image,
868 uint32_t plane,
869 struct anv_device_memory *memory,
870 uint32_t memory_offset)
871 {
872 assert(!image->planes[plane].bo_is_owned);
873
874 if (!memory) {
875 image->planes[plane].address = ANV_NULL_ADDRESS;
876 return;
877 }
878
879 image->planes[plane].address = (struct anv_address) {
880 .bo = memory->bo,
881 .offset = memory_offset,
882 };
883
884 /* If we're on a platform that uses implicit CCS and our buffer does not
885 * have any implicit CCS data, disable compression on that image.
886 */
887 if (device->physical->has_implicit_ccs && !memory->bo->has_implicit_ccs)
888 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
889 }
890
891 /* We are binding AHardwareBuffer. Get a description, resolve the
892 * format and prepare anv_image properly.
893 */
894 static void
895 resolve_ahw_image(struct anv_device *device,
896 struct anv_image *image,
897 struct anv_device_memory *mem)
898 {
899 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
900 assert(mem->ahw);
901 AHardwareBuffer_Desc desc;
902 AHardwareBuffer_describe(mem->ahw, &desc);
903
904 /* Check tiling. */
905 int i915_tiling = anv_gem_get_tiling(device, mem->bo->gem_handle);
906 VkImageTiling vk_tiling;
907 isl_tiling_flags_t isl_tiling_flags = 0;
908
909 switch (i915_tiling) {
910 case I915_TILING_NONE:
911 vk_tiling = VK_IMAGE_TILING_LINEAR;
912 isl_tiling_flags = ISL_TILING_LINEAR_BIT;
913 break;
914 case I915_TILING_X:
915 vk_tiling = VK_IMAGE_TILING_OPTIMAL;
916 isl_tiling_flags = ISL_TILING_X_BIT;
917 break;
918 case I915_TILING_Y:
919 vk_tiling = VK_IMAGE_TILING_OPTIMAL;
920 isl_tiling_flags = ISL_TILING_Y0_BIT;
921 break;
922 case -1:
923 default:
924 unreachable("Invalid tiling flags.");
925 }
926
927 assert(vk_tiling == VK_IMAGE_TILING_LINEAR ||
928 vk_tiling == VK_IMAGE_TILING_OPTIMAL);
929
930 /* Check format. */
931 VkFormat vk_format = vk_format_from_android(desc.format, desc.usage);
932 enum isl_format isl_fmt = anv_get_isl_format(&device->info,
933 vk_format,
934 VK_IMAGE_ASPECT_COLOR_BIT,
935 vk_tiling);
936 assert(isl_fmt != ISL_FORMAT_UNSUPPORTED);
937
938 /* Handle RGB(X)->RGBA fallback. */
939 switch (desc.format) {
940 case AHARDWAREBUFFER_FORMAT_R8G8B8_UNORM:
941 case AHARDWAREBUFFER_FORMAT_R8G8B8X8_UNORM:
942 if (isl_format_is_rgb(isl_fmt))
943 isl_fmt = isl_format_rgb_to_rgba(isl_fmt);
944 break;
945 }
946
947 /* Now we are able to fill anv_image fields properly and create
948 * isl_surface for it.
949 */
950 image->vk_format = vk_format;
951 image->format = anv_get_format(vk_format);
952 image->aspects = vk_format_aspects(image->vk_format);
953 image->n_planes = image->format->n_planes;
954
955 uint32_t stride = desc.stride *
956 (isl_format_get_layout(isl_fmt)->bpb / 8);
957
958 uint32_t b;
959 for_each_bit(b, image->aspects) {
960 VkResult r = make_surface(device, image, NULL, stride, isl_tiling_flags,
961 ISL_SURF_USAGE_DISABLE_AUX_BIT, (1 << b));
962 assert(r == VK_SUCCESS);
963 }
964 #endif
965 }
966
967 VkResult anv_BindImageMemory(
968 VkDevice _device,
969 VkImage _image,
970 VkDeviceMemory _memory,
971 VkDeviceSize memoryOffset)
972 {
973 ANV_FROM_HANDLE(anv_device, device, _device);
974 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
975 ANV_FROM_HANDLE(anv_image, image, _image);
976
977 if (mem->ahw)
978 resolve_ahw_image(device, image, mem);
979
980 uint32_t aspect_bit;
981 anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) {
982 uint32_t plane =
983 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
984 anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset);
985 }
986
987 return VK_SUCCESS;
988 }
989
990 VkResult anv_BindImageMemory2(
991 VkDevice _device,
992 uint32_t bindInfoCount,
993 const VkBindImageMemoryInfo* pBindInfos)
994 {
995 ANV_FROM_HANDLE(anv_device, device, _device);
996
997 for (uint32_t i = 0; i < bindInfoCount; i++) {
998 const VkBindImageMemoryInfo *bind_info = &pBindInfos[i];
999 ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory);
1000 ANV_FROM_HANDLE(anv_image, image, bind_info->image);
1001
1002 /* Resolve will alter the image's aspects, do this first. */
1003 if (mem && mem->ahw)
1004 resolve_ahw_image(device, image, mem);
1005
1006 VkImageAspectFlags aspects = image->aspects;
1007 vk_foreach_struct_const(s, bind_info->pNext) {
1008 switch (s->sType) {
1009 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO: {
1010 const VkBindImagePlaneMemoryInfo *plane_info =
1011 (const VkBindImagePlaneMemoryInfo *) s;
1012
1013 aspects = plane_info->planeAspect;
1014 break;
1015 }
1016 case VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_SWAPCHAIN_INFO_KHR: {
1017 const VkBindImageMemorySwapchainInfoKHR *swapchain_info =
1018 (const VkBindImageMemorySwapchainInfoKHR *) s;
1019 struct anv_image *swapchain_image =
1020 anv_swapchain_get_image(swapchain_info->swapchain,
1021 swapchain_info->imageIndex);
1022 assert(swapchain_image);
1023 assert(image->aspects == swapchain_image->aspects);
1024 assert(mem == NULL);
1025
1026 uint32_t aspect_bit;
1027 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
1028 uint32_t plane =
1029 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
1030 struct anv_device_memory mem = {
1031 .bo = swapchain_image->planes[plane].address.bo,
1032 };
1033 anv_image_bind_memory_plane(device, image, plane,
1034 &mem, bind_info->memoryOffset);
1035 }
1036 break;
1037 }
1038 default:
1039 anv_debug_ignored_stype(s->sType);
1040 break;
1041 }
1042 }
1043
1044 /* VkBindImageMemorySwapchainInfoKHR requires memory to be
1045 * VK_NULL_HANDLE. In such case, just carry one with the next bind
1046 * item.
1047 */
1048 if (!mem)
1049 continue;
1050
1051 uint32_t aspect_bit;
1052 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
1053 uint32_t plane =
1054 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
1055 anv_image_bind_memory_plane(device, image, plane,
1056 mem, bind_info->memoryOffset);
1057 }
1058 }
1059
1060 return VK_SUCCESS;
1061 }
1062
1063 void anv_GetImageSubresourceLayout(
1064 VkDevice device,
1065 VkImage _image,
1066 const VkImageSubresource* subresource,
1067 VkSubresourceLayout* layout)
1068 {
1069 ANV_FROM_HANDLE(anv_image, image, _image);
1070
1071 const struct anv_surface *surface;
1072 if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT &&
1073 image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
1074 isl_drm_modifier_has_aux(image->drm_format_mod)) {
1075 surface = &image->planes[0].aux_surface;
1076 } else {
1077 uint32_t plane = anv_image_aspect_to_plane(image->aspects,
1078 subresource->aspectMask);
1079 surface = &image->planes[plane].surface;
1080 }
1081
1082 assert(__builtin_popcount(subresource->aspectMask) == 1);
1083
1084 layout->offset = surface->offset;
1085 layout->rowPitch = surface->isl.row_pitch_B;
1086 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
1087 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
1088
1089 if (subresource->mipLevel > 0 || subresource->arrayLayer > 0) {
1090 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1091
1092 uint32_t offset_B;
1093 isl_surf_get_image_offset_B_tile_sa(&surface->isl,
1094 subresource->mipLevel,
1095 subresource->arrayLayer,
1096 0 /* logical_z_offset_px */,
1097 &offset_B, NULL, NULL);
1098 layout->offset += offset_B;
1099 layout->size = layout->rowPitch * anv_minify(image->extent.height,
1100 subresource->mipLevel);
1101 } else {
1102 layout->size = surface->isl.size_B;
1103 }
1104 }
1105
1106 VkResult anv_GetImageDrmFormatModifierPropertiesEXT(
1107 VkDevice device,
1108 VkImage _image,
1109 VkImageDrmFormatModifierPropertiesEXT* pProperties)
1110 {
1111 ANV_FROM_HANDLE(anv_image, image, _image);
1112
1113 assert(pProperties->sType ==
1114 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT);
1115
1116 pProperties->drmFormatModifier = image->drm_format_mod;
1117
1118 return VK_SUCCESS;
1119 }
1120
1121 /**
1122 * This function returns the assumed isl_aux_state for a given VkImageLayout.
1123 * Because Vulkan image layouts don't map directly to isl_aux_state enums, the
1124 * returned enum is the assumed worst case.
1125 *
1126 * @param devinfo The device information of the Intel GPU.
1127 * @param image The image that may contain a collection of buffers.
1128 * @param aspect The aspect of the image to be accessed.
1129 * @param layout The current layout of the image aspect(s).
1130 *
1131 * @return The primary buffer that should be used for the given layout.
1132 */
1133 enum isl_aux_state
1134 anv_layout_to_aux_state(const struct gen_device_info * const devinfo,
1135 const struct anv_image * const image,
1136 const VkImageAspectFlagBits aspect,
1137 const VkImageLayout layout)
1138 {
1139 /* Validate the inputs. */
1140
1141 /* The devinfo is needed as the optimal buffer varies across generations. */
1142 assert(devinfo != NULL);
1143
1144 /* The layout of a NULL image is not properly defined. */
1145 assert(image != NULL);
1146
1147 /* The aspect must be exactly one of the image aspects. */
1148 assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
1149
1150 /* Determine the optimal buffer. */
1151
1152 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1153
1154 /* If we don't have an aux buffer then aux state makes no sense */
1155 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE);
1156
1157 /* All images that use an auxiliary surface are required to be tiled. */
1158 assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
1159
1160 /* Stencil has no aux */
1161 assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
1162
1163 switch (layout) {
1164 /* Invalid layouts */
1165 case VK_IMAGE_LAYOUT_RANGE_SIZE:
1166 case VK_IMAGE_LAYOUT_MAX_ENUM:
1167 unreachable("Invalid image layout.");
1168
1169 /* Undefined layouts
1170 *
1171 * The pre-initialized layout is equivalent to the undefined layout for
1172 * optimally-tiled images. We can only do color compression (CCS or HiZ)
1173 * on tiled images.
1174 */
1175 case VK_IMAGE_LAYOUT_UNDEFINED:
1176 case VK_IMAGE_LAYOUT_PREINITIALIZED:
1177 return ISL_AUX_STATE_AUX_INVALID;
1178
1179 /* General layout */
1180 case VK_IMAGE_LAYOUT_GENERAL:
1181 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1182 if (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
1183 /* This buffer could be used as both a depth and input attachment
1184 * at the same time in which case compression could cause issues.
1185 */
1186 return ISL_AUX_STATE_AUX_INVALID;
1187 } else if (anv_can_sample_with_hiz(devinfo, image)) {
1188 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1189 } else {
1190 return ISL_AUX_STATE_AUX_INVALID;
1191 }
1192 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D) {
1193 return ISL_AUX_STATE_PASS_THROUGH;
1194 } else {
1195 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1196 }
1197
1198 /* Transfer layouts */
1199 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
1200 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D) {
1201 return ISL_AUX_STATE_PASS_THROUGH;
1202 } else {
1203 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1204 }
1205
1206 /* Sampling layouts */
1207 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR:
1208 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
1209 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL:
1210 assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
1211 /* Fall-through */
1212 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
1213 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
1214 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1215 if (anv_can_sample_with_hiz(devinfo, image))
1216 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1217 else
1218 return ISL_AUX_STATE_RESOLVED;
1219 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D) {
1220 return ISL_AUX_STATE_PASS_THROUGH;
1221 } else {
1222 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1223 }
1224
1225 case VK_IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL_KHR:
1226 return ISL_AUX_STATE_RESOLVED;
1227
1228 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
1229 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1230
1231 /* When handing the image off to the presentation engine, we need to
1232 * ensure that things are properly resolved. For images with no
1233 * modifier, we assume that they follow the old rules and always need
1234 * a full resolve because the PE doesn't understand any form of
1235 * compression. For images with modifiers, we use the aux usage from
1236 * the modifier.
1237 */
1238 const struct isl_drm_modifier_info *mod_info =
1239 isl_drm_modifier_get_info(image->drm_format_mod);
1240 if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
1241 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1242 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
1243 /* We do not yet support any modifiers which support clear color so
1244 * we just always return COMPRESSED_NO_CLEAR. One day, this will
1245 * change.
1246 */
1247 assert(!mod_info->supports_clear_color);
1248 return ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1249 } else {
1250 return ISL_AUX_STATE_PASS_THROUGH;
1251 }
1252 }
1253
1254 /* Rendering layouts */
1255 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
1256 assert(aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1257 /* fall-through */
1258 case VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR:
1259 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D) {
1260 return ISL_AUX_STATE_PARTIAL_CLEAR;
1261 } else {
1262 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1263 }
1264
1265 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR:
1266 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
1267 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL:
1268 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
1269 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1270
1271 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
1272 unreachable("VK_KHR_shared_presentable_image is unsupported");
1273
1274 case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT:
1275 unreachable("VK_EXT_fragment_density_map is unsupported");
1276
1277 case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV:
1278 unreachable("VK_NV_shading_rate_image is unsupported");
1279 }
1280
1281 unreachable("layout is not a VkImageLayout enumeration member.");
1282 }
1283
1284 ASSERTED static bool
1285 vk_image_layout_is_read_only(VkImageLayout layout,
1286 VkImageAspectFlagBits aspect)
1287 {
1288 assert(util_bitcount(aspect) == 1);
1289
1290 switch (layout) {
1291 case VK_IMAGE_LAYOUT_UNDEFINED:
1292 case VK_IMAGE_LAYOUT_PREINITIALIZED:
1293 return true; /* These are only used for layout transitions */
1294
1295 case VK_IMAGE_LAYOUT_GENERAL:
1296 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
1297 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
1298 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
1299 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
1300 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR:
1301 case VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR:
1302 return false;
1303
1304 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
1305 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
1306 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
1307 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
1308 case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV:
1309 case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT:
1310 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR:
1311 case VK_IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL_KHR:
1312 return true;
1313
1314 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL:
1315 return aspect == VK_IMAGE_ASPECT_DEPTH_BIT;
1316
1317 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL:
1318 return aspect == VK_IMAGE_ASPECT_STENCIL_BIT;
1319
1320 case VK_IMAGE_LAYOUT_RANGE_SIZE:
1321 case VK_IMAGE_LAYOUT_MAX_ENUM:
1322 unreachable("Invalid image layout.");
1323 }
1324
1325 unreachable("Invalid image layout.");
1326 }
1327
1328 /**
1329 * This function determines the optimal buffer to use for a given
1330 * VkImageLayout and other pieces of information needed to make that
1331 * determination. This does not determine the optimal buffer to use
1332 * during a resolve operation.
1333 *
1334 * @param devinfo The device information of the Intel GPU.
1335 * @param image The image that may contain a collection of buffers.
1336 * @param aspect The aspect of the image to be accessed.
1337 * @param usage The usage which describes how the image will be accessed.
1338 * @param layout The current layout of the image aspect(s).
1339 *
1340 * @return The primary buffer that should be used for the given layout.
1341 */
1342 enum isl_aux_usage
1343 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
1344 const struct anv_image * const image,
1345 const VkImageAspectFlagBits aspect,
1346 const VkImageUsageFlagBits usage,
1347 const VkImageLayout layout)
1348 {
1349 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1350
1351 /* If there is no auxiliary surface allocated, we must use the one and only
1352 * main buffer.
1353 */
1354 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
1355 return ISL_AUX_USAGE_NONE;
1356
1357 enum isl_aux_state aux_state =
1358 anv_layout_to_aux_state(devinfo, image, aspect, layout);
1359
1360 switch (aux_state) {
1361 case ISL_AUX_STATE_CLEAR:
1362 unreachable("We never use this state");
1363
1364 case ISL_AUX_STATE_PARTIAL_CLEAR:
1365 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1366 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_D);
1367 assert(image->samples == 1);
1368 return ISL_AUX_USAGE_CCS_D;
1369
1370 case ISL_AUX_STATE_COMPRESSED_CLEAR:
1371 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
1372 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1373 return ISL_AUX_USAGE_HIZ;
1374 } else {
1375 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE);
1376 return image->planes[plane].aux_usage;
1377 }
1378
1379 case ISL_AUX_STATE_RESOLVED:
1380 /* We can only use RESOLVED in read-only layouts because any write will
1381 * either land us in AUX_INVALID or COMPRESSED_NO_CLEAR. We can do
1382 * writes in PASS_THROUGH without destroying it so that is allowed.
1383 */
1384 assert(vk_image_layout_is_read_only(layout, aspect));
1385 assert(util_is_power_of_two_or_zero(usage));
1386 if (usage == VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT) {
1387 /* If we have valid HiZ data and are using the image as a read-only
1388 * depth/stencil attachment, we should enable HiZ so that we can get
1389 * faster depth testing.
1390 */
1391 return ISL_AUX_USAGE_HIZ;
1392 } else {
1393 return ISL_AUX_USAGE_NONE;
1394 }
1395
1396 case ISL_AUX_STATE_PASS_THROUGH:
1397 case ISL_AUX_STATE_AUX_INVALID:
1398 return ISL_AUX_USAGE_NONE;
1399 }
1400
1401 unreachable("Invalid isl_aux_state");
1402 }
1403
1404 /**
1405 * This function returns the level of unresolved fast-clear support of the
1406 * given image in the given VkImageLayout.
1407 *
1408 * @param devinfo The device information of the Intel GPU.
1409 * @param image The image that may contain a collection of buffers.
1410 * @param aspect The aspect of the image to be accessed.
1411 * @param usage The usage which describes how the image will be accessed.
1412 * @param layout The current layout of the image aspect(s).
1413 */
1414 enum anv_fast_clear_type
1415 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
1416 const struct anv_image * const image,
1417 const VkImageAspectFlagBits aspect,
1418 const VkImageLayout layout)
1419 {
1420 if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
1421 return ANV_FAST_CLEAR_NONE;
1422
1423 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1424
1425 /* If there is no auxiliary surface allocated, there are no fast-clears */
1426 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
1427 return ANV_FAST_CLEAR_NONE;
1428
1429 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
1430 * lack the MI ALU which we need to determine the predicates.
1431 */
1432 if (devinfo->gen == 7 && !devinfo->is_haswell && image->samples > 1)
1433 return ANV_FAST_CLEAR_NONE;
1434
1435 enum isl_aux_state aux_state =
1436 anv_layout_to_aux_state(devinfo, image, aspect, layout);
1437
1438 switch (aux_state) {
1439 case ISL_AUX_STATE_CLEAR:
1440 unreachable("We never use this state");
1441
1442 case ISL_AUX_STATE_PARTIAL_CLEAR:
1443 case ISL_AUX_STATE_COMPRESSED_CLEAR:
1444 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1445 return ANV_FAST_CLEAR_DEFAULT_VALUE;
1446 } else if (layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
1447 /* When we're in a render pass we have the clear color data from the
1448 * VkRenderPassBeginInfo and we can use arbitrary clear colors. They
1449 * must get partially resolved before we leave the render pass.
1450 */
1451 return ANV_FAST_CLEAR_ANY;
1452 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
1453 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1454 /* If the image has MCS or CCS_E enabled all the time then we can use
1455 * fast-clear as long as the clear color is the default value of zero
1456 * since this is the default value we program into every surface
1457 * state used for texturing.
1458 */
1459 return ANV_FAST_CLEAR_DEFAULT_VALUE;
1460 } else {
1461 return ANV_FAST_CLEAR_NONE;
1462 }
1463
1464 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
1465 case ISL_AUX_STATE_RESOLVED:
1466 case ISL_AUX_STATE_PASS_THROUGH:
1467 case ISL_AUX_STATE_AUX_INVALID:
1468 return ANV_FAST_CLEAR_NONE;
1469 }
1470
1471 unreachable("Invalid isl_aux_state");
1472 }
1473
1474
1475 static struct anv_state
1476 alloc_surface_state(struct anv_device *device)
1477 {
1478 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
1479 }
1480
1481 static enum isl_channel_select
1482 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
1483 struct isl_swizzle format_swizzle)
1484 {
1485 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
1486 swizzle = component;
1487
1488 switch (swizzle) {
1489 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
1490 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
1491 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
1492 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
1493 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
1494 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
1495 default:
1496 unreachable("Invalid swizzle");
1497 }
1498 }
1499
1500 void
1501 anv_image_fill_surface_state(struct anv_device *device,
1502 const struct anv_image *image,
1503 VkImageAspectFlagBits aspect,
1504 const struct isl_view *view_in,
1505 isl_surf_usage_flags_t view_usage,
1506 enum isl_aux_usage aux_usage,
1507 const union isl_color_value *clear_color,
1508 enum anv_image_view_state_flags flags,
1509 struct anv_surface_state *state_inout,
1510 struct brw_image_param *image_param_out)
1511 {
1512 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1513
1514 const struct anv_surface *surface = &image->planes[plane].surface,
1515 *aux_surface = &image->planes[plane].aux_surface;
1516
1517 struct isl_view view = *view_in;
1518 view.usage |= view_usage;
1519
1520 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1521 * compressed surface with a shadow surface, we use the shadow instead of
1522 * the primary surface. The shadow surface will be tiled, unlike the main
1523 * surface, so it should get significantly better performance.
1524 */
1525 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
1526 isl_format_is_compressed(view.format) &&
1527 (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
1528 assert(isl_format_is_compressed(surface->isl.format));
1529 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1530 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
1531 surface = &image->planes[plane].shadow_surface;
1532 }
1533
1534 /* For texturing from stencil on gen7, we have to sample from a shadow
1535 * surface because we don't support W-tiling in the sampler.
1536 */
1537 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
1538 aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
1539 assert(device->info.gen == 7);
1540 assert(view_usage & ISL_SURF_USAGE_TEXTURE_BIT);
1541 surface = &image->planes[plane].shadow_surface;
1542 }
1543
1544 if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
1545 view.swizzle = anv_swizzle_for_render(view.swizzle);
1546
1547 /* On Ivy Bridge and Bay Trail we do the swizzle in the shader */
1548 if (device->info.gen == 7 && !device->info.is_haswell)
1549 view.swizzle = ISL_SWIZZLE_IDENTITY;
1550
1551 /* If this is a HiZ buffer we can sample from with a programmable clear
1552 * value (SKL+), define the clear value to the optimal constant.
1553 */
1554 union isl_color_value default_clear_color = { .u32 = { 0, } };
1555 if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ)
1556 default_clear_color.f32[0] = ANV_HZ_FC_VAL;
1557 if (!clear_color)
1558 clear_color = &default_clear_color;
1559
1560 const struct anv_address address =
1561 anv_address_add(image->planes[plane].address, surface->offset);
1562
1563 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1564 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
1565 !isl_has_matching_typed_storage_image_format(&device->info,
1566 view.format)) {
1567 /* In this case, we are a writeable storage buffer which needs to be
1568 * lowered to linear. All tiling and offset calculations will be done in
1569 * the shader.
1570 */
1571 assert(aux_usage == ISL_AUX_USAGE_NONE);
1572 isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
1573 .address = anv_address_physical(address),
1574 .size_B = surface->isl.size_B,
1575 .format = ISL_FORMAT_RAW,
1576 .swizzle = ISL_SWIZZLE_IDENTITY,
1577 .stride_B = 1,
1578 .mocs = anv_mocs_for_bo(device, address.bo));
1579 state_inout->address = address,
1580 state_inout->aux_address = ANV_NULL_ADDRESS;
1581 state_inout->clear_address = ANV_NULL_ADDRESS;
1582 } else {
1583 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1584 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
1585 /* Typed surface reads support a very limited subset of the shader
1586 * image formats. Translate it into the closest format the hardware
1587 * supports.
1588 */
1589 assert(aux_usage == ISL_AUX_USAGE_NONE);
1590 view.format = isl_lower_storage_image_format(&device->info,
1591 view.format);
1592 }
1593
1594 const struct isl_surf *isl_surf = &surface->isl;
1595
1596 struct isl_surf tmp_surf;
1597 uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
1598 if (isl_format_is_compressed(surface->isl.format) &&
1599 !isl_format_is_compressed(view.format)) {
1600 /* We're creating an uncompressed view of a compressed surface. This
1601 * is allowed but only for a single level/layer.
1602 */
1603 assert(surface->isl.samples == 1);
1604 assert(view.levels == 1);
1605 assert(view.array_len == 1);
1606
1607 isl_surf_get_image_surf(&device->isl_dev, isl_surf,
1608 view.base_level,
1609 surface->isl.dim == ISL_SURF_DIM_3D ?
1610 0 : view.base_array_layer,
1611 surface->isl.dim == ISL_SURF_DIM_3D ?
1612 view.base_array_layer : 0,
1613 &tmp_surf,
1614 &offset_B, &tile_x_sa, &tile_y_sa);
1615
1616 /* The newly created image represents the one subimage we're
1617 * referencing with this view so it only has one array slice and
1618 * miplevel.
1619 */
1620 view.base_array_layer = 0;
1621 view.base_level = 0;
1622
1623 /* We're making an uncompressed view here. The image dimensions need
1624 * to be scaled down by the block size.
1625 */
1626 const struct isl_format_layout *fmtl =
1627 isl_format_get_layout(surface->isl.format);
1628 tmp_surf.logical_level0_px =
1629 isl_surf_get_logical_level0_el(&tmp_surf);
1630 tmp_surf.phys_level0_sa = isl_surf_get_phys_level0_el(&tmp_surf);
1631 tmp_surf.format = view.format;
1632 tile_x_sa /= fmtl->bw;
1633 tile_y_sa /= fmtl->bh;
1634
1635 isl_surf = &tmp_surf;
1636
1637 if (device->info.gen <= 8) {
1638 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1639 assert(tile_x_sa == 0);
1640 assert(tile_y_sa == 0);
1641 }
1642 }
1643
1644 state_inout->address = anv_address_add(address, offset_B);
1645
1646 struct anv_address aux_address = ANV_NULL_ADDRESS;
1647 if (aux_usage != ISL_AUX_USAGE_NONE) {
1648 aux_address = anv_address_add(image->planes[plane].address,
1649 aux_surface->offset);
1650 }
1651 state_inout->aux_address = aux_address;
1652
1653 struct anv_address clear_address = ANV_NULL_ADDRESS;
1654 if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
1655 if (aux_usage == ISL_AUX_USAGE_HIZ) {
1656 clear_address = (struct anv_address) {
1657 .bo = device->hiz_clear_bo,
1658 .offset = 0,
1659 };
1660 } else {
1661 clear_address = anv_image_get_clear_color_addr(device, image, aspect);
1662 }
1663 }
1664 state_inout->clear_address = clear_address;
1665
1666 isl_surf_fill_state(&device->isl_dev, state_inout->state.map,
1667 .surf = isl_surf,
1668 .view = &view,
1669 .address = anv_address_physical(state_inout->address),
1670 .clear_color = *clear_color,
1671 .aux_surf = &aux_surface->isl,
1672 .aux_usage = aux_usage,
1673 .aux_address = anv_address_physical(aux_address),
1674 .clear_address = anv_address_physical(clear_address),
1675 .use_clear_address = !anv_address_is_null(clear_address),
1676 .mocs = anv_mocs_for_bo(device,
1677 state_inout->address.bo),
1678 .x_offset_sa = tile_x_sa,
1679 .y_offset_sa = tile_y_sa);
1680
1681 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1682 * are used to store other information. This should be ok, however,
1683 * because the surface buffer addresses are always 4K page aligned.
1684 */
1685 uint32_t *aux_addr_dw = state_inout->state.map +
1686 device->isl_dev.ss.aux_addr_offset;
1687 assert((aux_address.offset & 0xfff) == 0);
1688 state_inout->aux_address.offset |= *aux_addr_dw & 0xfff;
1689
1690 if (device->info.gen >= 10 && clear_address.bo) {
1691 uint32_t *clear_addr_dw = state_inout->state.map +
1692 device->isl_dev.ss.clear_color_state_offset;
1693 assert((clear_address.offset & 0x3f) == 0);
1694 state_inout->clear_address.offset |= *clear_addr_dw & 0x3f;
1695 }
1696 }
1697
1698 if (image_param_out) {
1699 assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT);
1700 isl_surf_fill_image_param(&device->isl_dev, image_param_out,
1701 &surface->isl, &view);
1702 }
1703 }
1704
1705 static VkImageAspectFlags
1706 remap_aspect_flags(VkImageAspectFlags view_aspects)
1707 {
1708 if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1709 if (util_bitcount(view_aspects) == 1)
1710 return VK_IMAGE_ASPECT_COLOR_BIT;
1711
1712 VkImageAspectFlags color_aspects = 0;
1713 for (uint32_t i = 0; i < util_bitcount(view_aspects); i++)
1714 color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT << i;
1715 return color_aspects;
1716 }
1717 /* No special remapping needed for depth & stencil aspects. */
1718 return view_aspects;
1719 }
1720
1721 static uint32_t
1722 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
1723 {
1724 uint32_t planes = 0;
1725
1726 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
1727 VK_IMAGE_ASPECT_DEPTH_BIT |
1728 VK_IMAGE_ASPECT_STENCIL_BIT |
1729 VK_IMAGE_ASPECT_PLANE_0_BIT))
1730 planes++;
1731 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
1732 planes++;
1733 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
1734 planes++;
1735
1736 if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
1737 (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
1738 planes++;
1739
1740 return planes;
1741 }
1742
1743 VkResult
1744 anv_CreateImageView(VkDevice _device,
1745 const VkImageViewCreateInfo *pCreateInfo,
1746 const VkAllocationCallbacks *pAllocator,
1747 VkImageView *pView)
1748 {
1749 ANV_FROM_HANDLE(anv_device, device, _device);
1750 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
1751 struct anv_image_view *iview;
1752
1753 iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
1754 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1755 if (iview == NULL)
1756 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1757
1758 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1759
1760 assert(range->layerCount > 0);
1761 assert(range->baseMipLevel < image->levels);
1762
1763 /* Check if a conversion info was passed. */
1764 const struct anv_format *conv_format = NULL;
1765 const VkSamplerYcbcrConversionInfo *conv_info =
1766 vk_find_struct_const(pCreateInfo->pNext, SAMPLER_YCBCR_CONVERSION_INFO);
1767
1768 /* If image has an external format, the pNext chain must contain an instance of
1769 * VKSamplerYcbcrConversionInfo with a conversion object created with the same
1770 * external format as image."
1771 */
1772 assert(!image->external_format || conv_info);
1773
1774 if (conv_info) {
1775 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion, conv_info->conversion);
1776 conv_format = conversion->format;
1777 }
1778
1779 VkImageUsageFlags image_usage = 0;
1780 if (range->aspectMask & ~VK_IMAGE_ASPECT_STENCIL_BIT)
1781 image_usage |= image->usage;
1782 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT)
1783 image_usage |= image->stencil_usage;
1784
1785 const VkImageViewUsageCreateInfo *usage_info =
1786 vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO);
1787 VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image_usage;
1788
1789 /* View usage should be a subset of image usage */
1790 assert((view_usage & ~image_usage) == 0);
1791 assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
1792 VK_IMAGE_USAGE_STORAGE_BIT |
1793 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
1794 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
1795 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
1796
1797 switch (image->type) {
1798 default:
1799 unreachable("bad VkImageType");
1800 case VK_IMAGE_TYPE_1D:
1801 case VK_IMAGE_TYPE_2D:
1802 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
1803 break;
1804 case VK_IMAGE_TYPE_3D:
1805 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
1806 <= anv_minify(image->extent.depth, range->baseMipLevel));
1807 break;
1808 }
1809
1810 /* First expand aspects to the image's ones (for example
1811 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1812 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1813 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1814 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.
1815 */
1816 VkImageAspectFlags expanded_aspects =
1817 anv_image_expand_aspects(image, range->aspectMask);
1818
1819 iview->image = image;
1820
1821 /* Remap the expanded aspects for the image view. For example if only
1822 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1823 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1824 * the image view, it only has a single plane.
1825 */
1826 iview->aspect_mask = remap_aspect_flags(expanded_aspects);
1827 iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask);
1828 iview->vk_format = pCreateInfo->format;
1829
1830 /* "If image has an external format, format must be VK_FORMAT_UNDEFINED." */
1831 assert(!image->external_format || pCreateInfo->format == VK_FORMAT_UNDEFINED);
1832
1833 /* Format is undefined, this can happen when using external formats. Set
1834 * view format from the passed conversion info.
1835 */
1836 if (iview->vk_format == VK_FORMAT_UNDEFINED && conv_format)
1837 iview->vk_format = conv_format->vk_format;
1838
1839 iview->extent = (VkExtent3D) {
1840 .width = anv_minify(image->extent.width , range->baseMipLevel),
1841 .height = anv_minify(image->extent.height, range->baseMipLevel),
1842 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
1843 };
1844
1845 /* Now go through the underlying image selected planes (computed in
1846 * expanded_aspects) and map them to planes in the image view.
1847 */
1848 uint32_t iaspect_bit, vplane = 0;
1849 anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) {
1850 uint32_t iplane =
1851 anv_image_aspect_to_plane(image->aspects, 1UL << iaspect_bit);
1852 VkImageAspectFlags vplane_aspect =
1853 anv_plane_to_aspect(iview->aspect_mask, vplane);
1854 struct anv_format_plane format =
1855 anv_get_format_plane(&device->info, iview->vk_format,
1856 vplane_aspect, image->tiling);
1857
1858 iview->planes[vplane].image_plane = iplane;
1859
1860 iview->planes[vplane].isl = (struct isl_view) {
1861 .format = format.isl_format,
1862 .base_level = range->baseMipLevel,
1863 .levels = anv_get_levelCount(image, range),
1864 .base_array_layer = range->baseArrayLayer,
1865 .array_len = anv_get_layerCount(image, range),
1866 .swizzle = {
1867 .r = remap_swizzle(pCreateInfo->components.r,
1868 VK_COMPONENT_SWIZZLE_R, format.swizzle),
1869 .g = remap_swizzle(pCreateInfo->components.g,
1870 VK_COMPONENT_SWIZZLE_G, format.swizzle),
1871 .b = remap_swizzle(pCreateInfo->components.b,
1872 VK_COMPONENT_SWIZZLE_B, format.swizzle),
1873 .a = remap_swizzle(pCreateInfo->components.a,
1874 VK_COMPONENT_SWIZZLE_A, format.swizzle),
1875 },
1876 };
1877
1878 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
1879 iview->planes[vplane].isl.base_array_layer = 0;
1880 iview->planes[vplane].isl.array_len = iview->extent.depth;
1881 }
1882
1883 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
1884 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
1885 iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT;
1886 } else {
1887 iview->planes[vplane].isl.usage = 0;
1888 }
1889
1890 if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
1891 (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
1892 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
1893 iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device);
1894 iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device);
1895
1896 enum isl_aux_usage general_aux_usage =
1897 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1898 VK_IMAGE_USAGE_SAMPLED_BIT,
1899 VK_IMAGE_LAYOUT_GENERAL);
1900 enum isl_aux_usage optimal_aux_usage =
1901 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1902 VK_IMAGE_USAGE_SAMPLED_BIT,
1903 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
1904
1905 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1906 &iview->planes[vplane].isl,
1907 ISL_SURF_USAGE_TEXTURE_BIT,
1908 optimal_aux_usage, NULL,
1909 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL,
1910 &iview->planes[vplane].optimal_sampler_surface_state,
1911 NULL);
1912
1913 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1914 &iview->planes[vplane].isl,
1915 ISL_SURF_USAGE_TEXTURE_BIT,
1916 general_aux_usage, NULL,
1917 0,
1918 &iview->planes[vplane].general_sampler_surface_state,
1919 NULL);
1920 }
1921
1922 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1923 if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
1924 iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device);
1925 iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device);
1926
1927 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1928 &iview->planes[vplane].isl,
1929 ISL_SURF_USAGE_STORAGE_BIT,
1930 ISL_AUX_USAGE_NONE, NULL,
1931 0,
1932 &iview->planes[vplane].storage_surface_state,
1933 &iview->planes[vplane].storage_image_param);
1934
1935 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1936 &iview->planes[vplane].isl,
1937 ISL_SURF_USAGE_STORAGE_BIT,
1938 ISL_AUX_USAGE_NONE, NULL,
1939 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY,
1940 &iview->planes[vplane].writeonly_storage_surface_state,
1941 NULL);
1942 }
1943
1944 vplane++;
1945 }
1946
1947 *pView = anv_image_view_to_handle(iview);
1948
1949 return VK_SUCCESS;
1950 }
1951
1952 void
1953 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
1954 const VkAllocationCallbacks *pAllocator)
1955 {
1956 ANV_FROM_HANDLE(anv_device, device, _device);
1957 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
1958
1959 if (!iview)
1960 return;
1961
1962 for (uint32_t plane = 0; plane < iview->n_planes; plane++) {
1963 if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) {
1964 anv_state_pool_free(&device->surface_state_pool,
1965 iview->planes[plane].optimal_sampler_surface_state.state);
1966 }
1967
1968 if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) {
1969 anv_state_pool_free(&device->surface_state_pool,
1970 iview->planes[plane].general_sampler_surface_state.state);
1971 }
1972
1973 if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) {
1974 anv_state_pool_free(&device->surface_state_pool,
1975 iview->planes[plane].storage_surface_state.state);
1976 }
1977
1978 if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) {
1979 anv_state_pool_free(&device->surface_state_pool,
1980 iview->planes[plane].writeonly_storage_surface_state.state);
1981 }
1982 }
1983
1984 vk_free2(&device->alloc, pAllocator, iview);
1985 }
1986
1987
1988 VkResult
1989 anv_CreateBufferView(VkDevice _device,
1990 const VkBufferViewCreateInfo *pCreateInfo,
1991 const VkAllocationCallbacks *pAllocator,
1992 VkBufferView *pView)
1993 {
1994 ANV_FROM_HANDLE(anv_device, device, _device);
1995 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
1996 struct anv_buffer_view *view;
1997
1998 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1999 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2000 if (!view)
2001 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2002
2003 /* TODO: Handle the format swizzle? */
2004
2005 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
2006 VK_IMAGE_ASPECT_COLOR_BIT,
2007 VK_IMAGE_TILING_LINEAR);
2008 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
2009 view->range = anv_buffer_get_range(buffer, pCreateInfo->offset,
2010 pCreateInfo->range);
2011 view->range = align_down_npot_u32(view->range, format_bs);
2012
2013 view->address = anv_address_add(buffer->address, pCreateInfo->offset);
2014
2015 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
2016 view->surface_state = alloc_surface_state(device);
2017
2018 anv_fill_buffer_surface_state(device, view->surface_state,
2019 view->format,
2020 view->address, view->range, format_bs);
2021 } else {
2022 view->surface_state = (struct anv_state){ 0 };
2023 }
2024
2025 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
2026 view->storage_surface_state = alloc_surface_state(device);
2027 view->writeonly_storage_surface_state = alloc_surface_state(device);
2028
2029 enum isl_format storage_format =
2030 isl_has_matching_typed_storage_image_format(&device->info,
2031 view->format) ?
2032 isl_lower_storage_image_format(&device->info, view->format) :
2033 ISL_FORMAT_RAW;
2034
2035 anv_fill_buffer_surface_state(device, view->storage_surface_state,
2036 storage_format,
2037 view->address, view->range,
2038 (storage_format == ISL_FORMAT_RAW ? 1 :
2039 isl_format_get_layout(storage_format)->bpb / 8));
2040
2041 /* Write-only accesses should use the original format. */
2042 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
2043 view->format,
2044 view->address, view->range,
2045 isl_format_get_layout(view->format)->bpb / 8);
2046
2047 isl_buffer_fill_image_param(&device->isl_dev,
2048 &view->storage_image_param,
2049 view->format, view->range);
2050 } else {
2051 view->storage_surface_state = (struct anv_state){ 0 };
2052 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
2053 }
2054
2055 *pView = anv_buffer_view_to_handle(view);
2056
2057 return VK_SUCCESS;
2058 }
2059
2060 void
2061 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
2062 const VkAllocationCallbacks *pAllocator)
2063 {
2064 ANV_FROM_HANDLE(anv_device, device, _device);
2065 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
2066
2067 if (!view)
2068 return;
2069
2070 if (view->surface_state.alloc_size > 0)
2071 anv_state_pool_free(&device->surface_state_pool,
2072 view->surface_state);
2073
2074 if (view->storage_surface_state.alloc_size > 0)
2075 anv_state_pool_free(&device->surface_state_pool,
2076 view->storage_surface_state);
2077
2078 if (view->writeonly_storage_surface_state.alloc_size > 0)
2079 anv_state_pool_free(&device->surface_state_pool,
2080 view->writeonly_storage_surface_state);
2081
2082 vk_free2(&device->alloc, pAllocator, view);
2083 }