anv: Rename clflush_range and state_clflush
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "util/debug.h"
32
33 #include "vk_format_info.h"
34
35 /**
36 * Exactly one bit must be set in \a aspect.
37 */
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageUsageFlags vk_usage,
40 VkImageAspectFlags aspect)
41 {
42 isl_surf_usage_flags_t isl_usage = 0;
43
44 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
45 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
46
47 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
48 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
49
50 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
51 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
52
53 if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
54 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
55
56 /* Even if we're only using it for transfer operations, clears to depth and
57 * stencil images happen as depth and stencil so they need the right ISL
58 * usage bits or else things will fall apart.
59 */
60 switch (aspect) {
61 case VK_IMAGE_ASPECT_DEPTH_BIT:
62 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
63 break;
64 case VK_IMAGE_ASPECT_STENCIL_BIT:
65 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
66 break;
67 case VK_IMAGE_ASPECT_COLOR_BIT:
68 break;
69 default:
70 unreachable("bad VkImageAspect");
71 }
72
73 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
74 /* blorp implements transfers by sampling from the source image. */
75 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
76 }
77
78 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
79 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
80 /* blorp implements transfers by rendering into the destination image.
81 * Only request this with color images, as we deal with depth/stencil
82 * formats differently. */
83 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
84 }
85
86 return isl_usage;
87 }
88
89 /**
90 * Exactly one bit must be set in \a aspect.
91 */
92 static struct anv_surface *
93 get_surface(struct anv_image *image, VkImageAspectFlags aspect)
94 {
95 switch (aspect) {
96 default:
97 unreachable("bad VkImageAspect");
98 case VK_IMAGE_ASPECT_COLOR_BIT:
99 return &image->color_surface;
100 case VK_IMAGE_ASPECT_DEPTH_BIT:
101 return &image->depth_surface;
102 case VK_IMAGE_ASPECT_STENCIL_BIT:
103 return &image->stencil_surface;
104 }
105 }
106
107 static void
108 add_surface(struct anv_image *image, struct anv_surface *surf)
109 {
110 assert(surf->isl.size > 0); /* isl surface must be initialized */
111
112 surf->offset = align_u32(image->size, surf->isl.alignment);
113 image->size = surf->offset + surf->isl.size;
114 image->alignment = MAX2(image->alignment, surf->isl.alignment);
115 }
116
117 /**
118 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
119 * image's memory requirements (that is, the image's size and alignment).
120 *
121 * Exactly one bit must be set in \a aspect.
122 */
123 static VkResult
124 make_surface(const struct anv_device *dev,
125 struct anv_image *image,
126 const struct anv_image_create_info *anv_info,
127 VkImageAspectFlags aspect)
128 {
129 const VkImageCreateInfo *vk_info = anv_info->vk_info;
130 bool ok UNUSED;
131
132 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
133 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
134 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
135 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
136 };
137
138 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
139 * result with an optionally provided ISL tiling argument.
140 */
141 isl_tiling_flags_t tiling_flags =
142 (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
143 ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
144
145 if (anv_info->isl_tiling_flags)
146 tiling_flags &= anv_info->isl_tiling_flags;
147
148 assert(tiling_flags);
149
150 struct anv_surface *anv_surf = get_surface(image, aspect);
151
152 image->extent = anv_sanitize_image_extent(vk_info->imageType,
153 vk_info->extent);
154
155 enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
156 aspect, vk_info->tiling);
157 assert(format != ISL_FORMAT_UNSUPPORTED);
158
159 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
160 .dim = vk_to_isl_surf_dim[vk_info->imageType],
161 .format = format,
162 .width = image->extent.width,
163 .height = image->extent.height,
164 .depth = image->extent.depth,
165 .levels = vk_info->mipLevels,
166 .array_len = vk_info->arrayLayers,
167 .samples = vk_info->samples,
168 .min_alignment = 0,
169 .min_pitch = anv_info->stride,
170 .usage = choose_isl_surf_usage(image->usage, aspect),
171 .tiling_flags = tiling_flags);
172
173 /* isl_surf_init() will fail only if provided invalid input. Invalid input
174 * is illegal in Vulkan.
175 */
176 assert(ok);
177
178 add_surface(image, anv_surf);
179
180 /* Add a HiZ surface to a depth buffer that will be used for rendering.
181 */
182 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
183 /* Allow the user to control HiZ enabling. Disable by default on gen7
184 * because resolves are not currently implemented pre-BDW.
185 */
186 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
187 /* It will never be used as an attachment, HiZ is pointless. */
188 } else if (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
189 /* From the 1.0.37 spec:
190 *
191 * "An attachment used as an input attachment and depth/stencil
192 * attachment must be in either VK_IMAGE_LAYOUT_GENERAL or
193 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL."
194 *
195 * It will never have a layout of
196 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL, so HiZ is
197 * currently pointless. If transfer operations learn to use the HiZ
198 * buffer, we can enable HiZ for VK_IMAGE_LAYOUT_GENERAL and support
199 * input attachments.
200 */
201 anv_finishme("Implement HiZ for input attachments");
202 } else if (!env_var_as_boolean("INTEL_VK_HIZ", dev->info.gen >= 8)) {
203 anv_finishme("Implement gen7 HiZ");
204 } else if (vk_info->mipLevels > 1) {
205 anv_finishme("Test multi-LOD HiZ");
206 } else if (vk_info->arrayLayers > 1) {
207 anv_finishme("Implement multi-arrayLayer HiZ clears and resolves");
208 } else if (dev->info.gen == 8 && vk_info->samples > 1) {
209 anv_finishme("Test gen8 multisampled HiZ");
210 } else {
211 assert(image->aux_surface.isl.size == 0);
212 isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
213 &image->aux_surface.isl);
214 add_surface(image, &image->aux_surface);
215 image->aux_usage = ISL_AUX_USAGE_HIZ;
216 }
217 } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples == 1) {
218 if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
219 assert(image->aux_surface.isl.size == 0);
220 ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
221 &image->aux_surface.isl);
222 if (ok) {
223 add_surface(image, &image->aux_surface);
224
225 /* For images created without MUTABLE_FORMAT_BIT set, we know that
226 * they will always be used with the original format. In
227 * particular, they will always be used with a format that
228 * supports color compression. If it's never used as a storage
229 * image, then it will only be used through the sampler or the as
230 * a render target. This means that it's safe to just leave
231 * compression on at all times for these formats.
232 */
233 if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
234 !(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
235 isl_format_supports_ccs_e(&dev->info, format)) {
236 image->aux_usage = ISL_AUX_USAGE_CCS_E;
237 }
238 }
239 }
240 }
241
242 return VK_SUCCESS;
243 }
244
245 VkResult
246 anv_image_create(VkDevice _device,
247 const struct anv_image_create_info *create_info,
248 const VkAllocationCallbacks* alloc,
249 VkImage *pImage)
250 {
251 ANV_FROM_HANDLE(anv_device, device, _device);
252 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
253 struct anv_image *image = NULL;
254 VkResult r;
255
256 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
257
258 anv_assert(pCreateInfo->mipLevels > 0);
259 anv_assert(pCreateInfo->arrayLayers > 0);
260 anv_assert(pCreateInfo->samples > 0);
261 anv_assert(pCreateInfo->extent.width > 0);
262 anv_assert(pCreateInfo->extent.height > 0);
263 anv_assert(pCreateInfo->extent.depth > 0);
264
265 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
266 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
267 if (!image)
268 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
269
270 memset(image, 0, sizeof(*image));
271 image->type = pCreateInfo->imageType;
272 image->extent = pCreateInfo->extent;
273 image->vk_format = pCreateInfo->format;
274 image->aspects = vk_format_aspects(image->vk_format);
275 image->levels = pCreateInfo->mipLevels;
276 image->array_size = pCreateInfo->arrayLayers;
277 image->samples = pCreateInfo->samples;
278 image->usage = pCreateInfo->usage;
279 image->tiling = pCreateInfo->tiling;
280 image->aux_usage = ISL_AUX_USAGE_NONE;
281
282 uint32_t b;
283 for_each_bit(b, image->aspects) {
284 r = make_surface(device, image, create_info, (1 << b));
285 if (r != VK_SUCCESS)
286 goto fail;
287 }
288
289 *pImage = anv_image_to_handle(image);
290
291 return VK_SUCCESS;
292
293 fail:
294 if (image)
295 vk_free2(&device->alloc, alloc, image);
296
297 return r;
298 }
299
300 VkResult
301 anv_CreateImage(VkDevice device,
302 const VkImageCreateInfo *pCreateInfo,
303 const VkAllocationCallbacks *pAllocator,
304 VkImage *pImage)
305 {
306 return anv_image_create(device,
307 &(struct anv_image_create_info) {
308 .vk_info = pCreateInfo,
309 },
310 pAllocator,
311 pImage);
312 }
313
314 void
315 anv_DestroyImage(VkDevice _device, VkImage _image,
316 const VkAllocationCallbacks *pAllocator)
317 {
318 ANV_FROM_HANDLE(anv_device, device, _device);
319 ANV_FROM_HANDLE(anv_image, image, _image);
320
321 if (!image)
322 return;
323
324 vk_free2(&device->alloc, pAllocator, image);
325 }
326
327 VkResult anv_BindImageMemory(
328 VkDevice _device,
329 VkImage _image,
330 VkDeviceMemory _memory,
331 VkDeviceSize memoryOffset)
332 {
333 ANV_FROM_HANDLE(anv_device, device, _device);
334 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
335 ANV_FROM_HANDLE(anv_image, image, _image);
336
337 if (mem) {
338 image->bo = &mem->bo;
339 image->offset = memoryOffset;
340 } else {
341 image->bo = NULL;
342 image->offset = 0;
343 }
344
345 if (image->aux_surface.isl.size > 0) {
346
347 /* The offset and size must be a multiple of 4K or else the
348 * anv_gem_mmap call below will return NULL.
349 */
350 assert((image->offset + image->aux_surface.offset) % 4096 == 0);
351 assert(image->aux_surface.isl.size % 4096 == 0);
352
353 /* Auxiliary surfaces need to have their memory cleared to 0 before they
354 * can be used. For CCS surfaces, this puts them in the "resolved"
355 * state so they can be used with CCS enabled before we ever touch it
356 * from the GPU. For HiZ, we need something valid or else we may get
357 * GPU hangs on some hardware and 0 works fine.
358 */
359 void *map = anv_gem_mmap(device, image->bo->gem_handle,
360 image->offset + image->aux_surface.offset,
361 image->aux_surface.isl.size,
362 device->info.has_llc ? 0 : I915_MMAP_WC);
363
364 /* If anv_gem_mmap returns NULL, it's likely that the kernel was
365 * not able to find space on the host to create a proper mapping.
366 */
367 if (map == NULL)
368 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
369
370 memset(map, 0, image->aux_surface.isl.size);
371
372 anv_gem_munmap(map, image->aux_surface.isl.size);
373 }
374
375 return VK_SUCCESS;
376 }
377
378 static void
379 anv_surface_get_subresource_layout(struct anv_image *image,
380 struct anv_surface *surface,
381 const VkImageSubresource *subresource,
382 VkSubresourceLayout *layout)
383 {
384 /* If we are on a non-zero mip level or array slice, we need to
385 * calculate a real offset.
386 */
387 anv_assert(subresource->mipLevel == 0);
388 anv_assert(subresource->arrayLayer == 0);
389
390 layout->offset = surface->offset;
391 layout->rowPitch = surface->isl.row_pitch;
392 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
393 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
394 layout->size = surface->isl.size;
395 }
396
397 void anv_GetImageSubresourceLayout(
398 VkDevice device,
399 VkImage _image,
400 const VkImageSubresource* pSubresource,
401 VkSubresourceLayout* pLayout)
402 {
403 ANV_FROM_HANDLE(anv_image, image, _image);
404
405 assert(__builtin_popcount(pSubresource->aspectMask) == 1);
406
407 switch (pSubresource->aspectMask) {
408 case VK_IMAGE_ASPECT_COLOR_BIT:
409 anv_surface_get_subresource_layout(image, &image->color_surface,
410 pSubresource, pLayout);
411 break;
412 case VK_IMAGE_ASPECT_DEPTH_BIT:
413 anv_surface_get_subresource_layout(image, &image->depth_surface,
414 pSubresource, pLayout);
415 break;
416 case VK_IMAGE_ASPECT_STENCIL_BIT:
417 anv_surface_get_subresource_layout(image, &image->stencil_surface,
418 pSubresource, pLayout);
419 break;
420 default:
421 assert(!"Invalid image aspect");
422 }
423 }
424
425 static struct anv_state
426 alloc_surface_state(struct anv_device *device)
427 {
428 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
429 }
430
431 static enum isl_channel_select
432 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
433 struct isl_swizzle format_swizzle)
434 {
435 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
436 swizzle = component;
437
438 switch (swizzle) {
439 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
440 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
441 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
442 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
443 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
444 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
445 default:
446 unreachable("Invalid swizzle");
447 }
448 }
449
450
451 VkResult
452 anv_CreateImageView(VkDevice _device,
453 const VkImageViewCreateInfo *pCreateInfo,
454 const VkAllocationCallbacks *pAllocator,
455 VkImageView *pView)
456 {
457 ANV_FROM_HANDLE(anv_device, device, _device);
458 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
459 struct anv_image_view *iview;
460
461 iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
462 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
463 if (iview == NULL)
464 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
465
466 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
467
468 assert(range->layerCount > 0);
469 assert(range->baseMipLevel < image->levels);
470 assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
471 VK_IMAGE_USAGE_STORAGE_BIT |
472 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
473 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
474
475 switch (image->type) {
476 default:
477 unreachable("bad VkImageType");
478 case VK_IMAGE_TYPE_1D:
479 case VK_IMAGE_TYPE_2D:
480 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
481 break;
482 case VK_IMAGE_TYPE_3D:
483 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
484 <= anv_minify(image->extent.depth, range->baseMipLevel));
485 break;
486 }
487
488 const struct anv_surface *surface =
489 anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
490
491 iview->image = image;
492 iview->bo = image->bo;
493 iview->offset = image->offset + surface->offset;
494
495 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
496 iview->vk_format = pCreateInfo->format;
497
498 struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
499 range->aspectMask, image->tiling);
500
501 iview->isl = (struct isl_view) {
502 .format = format.isl_format,
503 .base_level = range->baseMipLevel,
504 .levels = anv_get_levelCount(image, range),
505 .base_array_layer = range->baseArrayLayer,
506 .array_len = anv_get_layerCount(image, range),
507 .swizzle = {
508 .r = remap_swizzle(pCreateInfo->components.r,
509 VK_COMPONENT_SWIZZLE_R, format.swizzle),
510 .g = remap_swizzle(pCreateInfo->components.g,
511 VK_COMPONENT_SWIZZLE_G, format.swizzle),
512 .b = remap_swizzle(pCreateInfo->components.b,
513 VK_COMPONENT_SWIZZLE_B, format.swizzle),
514 .a = remap_swizzle(pCreateInfo->components.a,
515 VK_COMPONENT_SWIZZLE_A, format.swizzle),
516 },
517 };
518
519 iview->extent = (VkExtent3D) {
520 .width = anv_minify(image->extent.width , range->baseMipLevel),
521 .height = anv_minify(image->extent.height, range->baseMipLevel),
522 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
523 };
524
525 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
526 iview->isl.base_array_layer = 0;
527 iview->isl.array_len = iview->extent.depth;
528 }
529
530 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
531 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
532 iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
533 } else {
534 iview->isl.usage = 0;
535 }
536
537 /* If the HiZ buffer can be sampled from, set the constant clear color.
538 * If it cannot, disable the isl aux usage flag.
539 */
540 float red_clear_color = 0.0f;
541 enum isl_aux_usage surf_usage = image->aux_usage;
542 if (image->aux_usage == ISL_AUX_USAGE_HIZ) {
543 if (iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT &&
544 anv_can_sample_with_hiz(device->info.gen, image->samples)) {
545 /* When a HiZ buffer is sampled on gen9+, ensure that
546 * the constant fast clear value is set in the surface state.
547 */
548 if (device->info.gen >= 9)
549 red_clear_color = ANV_HZ_FC_VAL;
550 } else {
551 surf_usage = ISL_AUX_USAGE_NONE;
552 }
553 }
554
555 /* Input attachment surfaces for color are allocated and filled
556 * out at BeginRenderPass time because they need compression information.
557 * Compression is not yet enabled for depth textures and stencil doesn't
558 * allow compression so we can just use the texture surface state from the
559 * view.
560 */
561 if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
562 (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
563 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
564 iview->sampler_surface_state = alloc_surface_state(device);
565
566 struct isl_view view = iview->isl;
567 view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
568 isl_surf_fill_state(&device->isl_dev,
569 iview->sampler_surface_state.map,
570 .surf = &surface->isl,
571 .view = &view,
572 .clear_color.f32 = { red_clear_color,},
573 .aux_surf = &image->aux_surface.isl,
574 .aux_usage = surf_usage,
575 .mocs = device->default_mocs);
576
577 if (!device->info.has_llc)
578 anv_state_flush(iview->sampler_surface_state);
579 } else {
580 iview->sampler_surface_state.alloc_size = 0;
581 }
582
583 /* NOTE: This one needs to go last since it may stomp isl_view.format */
584 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
585 iview->storage_surface_state = alloc_surface_state(device);
586 iview->writeonly_storage_surface_state = alloc_surface_state(device);
587
588 struct isl_view view = iview->isl;
589 view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
590
591 /* Write-only accesses always used a typed write instruction and should
592 * therefore use the real format.
593 */
594 isl_surf_fill_state(&device->isl_dev,
595 iview->writeonly_storage_surface_state.map,
596 .surf = &surface->isl,
597 .view = &view,
598 .aux_surf = &image->aux_surface.isl,
599 .aux_usage = surf_usage,
600 .mocs = device->default_mocs);
601
602 if (isl_has_matching_typed_storage_image_format(&device->info,
603 format.isl_format)) {
604 /* Typed surface reads support a very limited subset of the shader
605 * image formats. Translate it into the closest format the hardware
606 * supports.
607 */
608 view.format = isl_lower_storage_image_format(&device->info,
609 format.isl_format);
610
611 isl_surf_fill_state(&device->isl_dev,
612 iview->storage_surface_state.map,
613 .surf = &surface->isl,
614 .view = &view,
615 .aux_surf = &image->aux_surface.isl,
616 .aux_usage = surf_usage,
617 .mocs = device->default_mocs);
618 } else {
619 anv_fill_buffer_surface_state(device, iview->storage_surface_state,
620 ISL_FORMAT_RAW,
621 iview->offset,
622 iview->bo->size - iview->offset, 1);
623 }
624
625 isl_surf_fill_image_param(&device->isl_dev,
626 &iview->storage_image_param,
627 &surface->isl, &iview->isl);
628
629 if (!device->info.has_llc) {
630 anv_state_flush(iview->storage_surface_state);
631 anv_state_flush(iview->writeonly_storage_surface_state);
632 }
633 } else {
634 iview->storage_surface_state.alloc_size = 0;
635 iview->writeonly_storage_surface_state.alloc_size = 0;
636 }
637
638 *pView = anv_image_view_to_handle(iview);
639
640 return VK_SUCCESS;
641 }
642
643 void
644 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
645 const VkAllocationCallbacks *pAllocator)
646 {
647 ANV_FROM_HANDLE(anv_device, device, _device);
648 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
649
650 if (!iview)
651 return;
652
653 if (iview->sampler_surface_state.alloc_size > 0) {
654 anv_state_pool_free(&device->surface_state_pool,
655 iview->sampler_surface_state);
656 }
657
658 if (iview->storage_surface_state.alloc_size > 0) {
659 anv_state_pool_free(&device->surface_state_pool,
660 iview->storage_surface_state);
661 }
662
663 if (iview->writeonly_storage_surface_state.alloc_size > 0) {
664 anv_state_pool_free(&device->surface_state_pool,
665 iview->writeonly_storage_surface_state);
666 }
667
668 vk_free2(&device->alloc, pAllocator, iview);
669 }
670
671
672 VkResult
673 anv_CreateBufferView(VkDevice _device,
674 const VkBufferViewCreateInfo *pCreateInfo,
675 const VkAllocationCallbacks *pAllocator,
676 VkBufferView *pView)
677 {
678 ANV_FROM_HANDLE(anv_device, device, _device);
679 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
680 struct anv_buffer_view *view;
681
682 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
683 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
684 if (!view)
685 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
686
687 /* TODO: Handle the format swizzle? */
688
689 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
690 VK_IMAGE_ASPECT_COLOR_BIT,
691 VK_IMAGE_TILING_LINEAR);
692 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
693 view->bo = buffer->bo;
694 view->offset = buffer->offset + pCreateInfo->offset;
695 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
696 buffer->size - pCreateInfo->offset : pCreateInfo->range;
697 view->range = align_down_npot_u32(view->range, format_bs);
698
699 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
700 view->surface_state = alloc_surface_state(device);
701
702 anv_fill_buffer_surface_state(device, view->surface_state,
703 view->format,
704 view->offset, view->range, format_bs);
705 } else {
706 view->surface_state = (struct anv_state){ 0 };
707 }
708
709 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
710 view->storage_surface_state = alloc_surface_state(device);
711 view->writeonly_storage_surface_state = alloc_surface_state(device);
712
713 enum isl_format storage_format =
714 isl_has_matching_typed_storage_image_format(&device->info,
715 view->format) ?
716 isl_lower_storage_image_format(&device->info, view->format) :
717 ISL_FORMAT_RAW;
718
719 anv_fill_buffer_surface_state(device, view->storage_surface_state,
720 storage_format,
721 view->offset, view->range,
722 (storage_format == ISL_FORMAT_RAW ? 1 :
723 isl_format_get_layout(storage_format)->bpb / 8));
724
725 /* Write-only accesses should use the original format. */
726 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
727 view->format,
728 view->offset, view->range,
729 isl_format_get_layout(view->format)->bpb / 8);
730
731 isl_buffer_fill_image_param(&device->isl_dev,
732 &view->storage_image_param,
733 view->format, view->range);
734 } else {
735 view->storage_surface_state = (struct anv_state){ 0 };
736 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
737 }
738
739 *pView = anv_buffer_view_to_handle(view);
740
741 return VK_SUCCESS;
742 }
743
744 void
745 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
746 const VkAllocationCallbacks *pAllocator)
747 {
748 ANV_FROM_HANDLE(anv_device, device, _device);
749 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
750
751 if (!view)
752 return;
753
754 if (view->surface_state.alloc_size > 0)
755 anv_state_pool_free(&device->surface_state_pool,
756 view->surface_state);
757
758 if (view->storage_surface_state.alloc_size > 0)
759 anv_state_pool_free(&device->surface_state_pool,
760 view->storage_surface_state);
761
762 if (view->writeonly_storage_surface_state.alloc_size > 0)
763 anv_state_pool_free(&device->surface_state_pool,
764 view->writeonly_storage_surface_state);
765
766 vk_free2(&device->alloc, pAllocator, view);
767 }
768
769 const struct anv_surface *
770 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
771 VkImageAspectFlags aspect_mask)
772 {
773 switch (aspect_mask) {
774 case VK_IMAGE_ASPECT_COLOR_BIT:
775 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
776 return &image->color_surface;
777 case VK_IMAGE_ASPECT_DEPTH_BIT:
778 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
779 return &image->depth_surface;
780 case VK_IMAGE_ASPECT_STENCIL_BIT:
781 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
782 return &image->stencil_surface;
783 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
784 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
785 * combined depth stencil formats. Specifically, it states:
786 *
787 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
788 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
789 *
790 * Image views with both depth and stencil aspects are only valid for
791 * render target attachments, in which case
792 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
793 * stencil surfaces from the underlying surface.
794 */
795 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
796 return &image->depth_surface;
797 } else {
798 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
799 return &image->stencil_surface;
800 }
801 default:
802 unreachable("image does not have aspect");
803 return NULL;
804 }
805 }