intel/isl: Return surface creation success from aux helpers
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "anv_private.h"
31 #include "util/debug.h"
32
33 #include "vk_format_info.h"
34
35 /**
36 * Exactly one bit must be set in \a aspect.
37 */
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageUsageFlags vk_usage,
40 VkImageAspectFlags aspect)
41 {
42 isl_surf_usage_flags_t isl_usage = 0;
43
44 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
45 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
46
47 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
48 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
49
50 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
51 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
52
53 if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
54 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
55
56 /* Even if we're only using it for transfer operations, clears to depth and
57 * stencil images happen as depth and stencil so they need the right ISL
58 * usage bits or else things will fall apart.
59 */
60 switch (aspect) {
61 case VK_IMAGE_ASPECT_DEPTH_BIT:
62 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
63 break;
64 case VK_IMAGE_ASPECT_STENCIL_BIT:
65 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
66 break;
67 case VK_IMAGE_ASPECT_COLOR_BIT:
68 break;
69 default:
70 unreachable("bad VkImageAspect");
71 }
72
73 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
74 /* blorp implements transfers by sampling from the source image. */
75 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
76 }
77
78 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
79 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
80 /* blorp implements transfers by rendering into the destination image.
81 * Only request this with color images, as we deal with depth/stencil
82 * formats differently. */
83 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
84 }
85
86 return isl_usage;
87 }
88
89 /**
90 * Exactly one bit must be set in \a aspect.
91 */
92 static struct anv_surface *
93 get_surface(struct anv_image *image, VkImageAspectFlags aspect)
94 {
95 switch (aspect) {
96 default:
97 unreachable("bad VkImageAspect");
98 case VK_IMAGE_ASPECT_COLOR_BIT:
99 return &image->color_surface;
100 case VK_IMAGE_ASPECT_DEPTH_BIT:
101 return &image->depth_surface;
102 case VK_IMAGE_ASPECT_STENCIL_BIT:
103 return &image->stencil_surface;
104 }
105 }
106
107 static void
108 add_surface(struct anv_image *image, struct anv_surface *surf)
109 {
110 assert(surf->isl.size > 0); /* isl surface must be initialized */
111
112 surf->offset = align_u32(image->size, surf->isl.alignment);
113 image->size = surf->offset + surf->isl.size;
114 image->alignment = MAX2(image->alignment, surf->isl.alignment);
115 }
116
117 /**
118 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
119 * image's memory requirements (that is, the image's size and alignment).
120 *
121 * Exactly one bit must be set in \a aspect.
122 */
123 static VkResult
124 make_surface(const struct anv_device *dev,
125 struct anv_image *image,
126 const struct anv_image_create_info *anv_info,
127 VkImageAspectFlags aspect)
128 {
129 const VkImageCreateInfo *vk_info = anv_info->vk_info;
130 bool ok UNUSED;
131
132 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
133 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
134 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
135 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
136 };
137
138 /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
139 * result with an optionally provided ISL tiling argument.
140 */
141 isl_tiling_flags_t tiling_flags =
142 (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
143 ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
144
145 if (anv_info->isl_tiling_flags)
146 tiling_flags &= anv_info->isl_tiling_flags;
147
148 assert(tiling_flags);
149
150 struct anv_surface *anv_surf = get_surface(image, aspect);
151
152 image->extent = anv_sanitize_image_extent(vk_info->imageType,
153 vk_info->extent);
154
155 enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
156 aspect, vk_info->tiling);
157 assert(format != ISL_FORMAT_UNSUPPORTED);
158
159 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
160 .dim = vk_to_isl_surf_dim[vk_info->imageType],
161 .format = format,
162 .width = image->extent.width,
163 .height = image->extent.height,
164 .depth = image->extent.depth,
165 .levels = vk_info->mipLevels,
166 .array_len = vk_info->arrayLayers,
167 .samples = vk_info->samples,
168 .min_alignment = 0,
169 .min_pitch = anv_info->stride,
170 .usage = choose_isl_surf_usage(image->usage, aspect),
171 .tiling_flags = tiling_flags);
172
173 /* isl_surf_init() will fail only if provided invalid input. Invalid input
174 * is illegal in Vulkan.
175 */
176 assert(ok);
177
178 add_surface(image, anv_surf);
179
180 /* Add a HiZ surface to a depth buffer that will be used for rendering.
181 */
182 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
183 /* Allow the user to control HiZ enabling. Disable by default on gen7
184 * because resolves are not currently implemented pre-BDW.
185 */
186 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
187 /* It will never be used as an attachment, HiZ is pointless. */
188 } else if (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT) {
189 /* From the 1.0.37 spec:
190 *
191 * "An attachment used as an input attachment and depth/stencil
192 * attachment must be in either VK_IMAGE_LAYOUT_GENERAL or
193 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL."
194 *
195 * It will never have a layout of
196 * VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL, so HiZ is
197 * currently pointless. If transfer operations learn to use the HiZ
198 * buffer, we can enable HiZ for VK_IMAGE_LAYOUT_GENERAL and support
199 * input attachments.
200 */
201 anv_finishme("Implement HiZ for input attachments");
202 } else if (!env_var_as_boolean("INTEL_VK_HIZ", dev->info.gen >= 8)) {
203 anv_finishme("Implement gen7 HiZ");
204 } else if (vk_info->mipLevels > 1) {
205 anv_finishme("Test multi-LOD HiZ");
206 } else if (vk_info->arrayLayers > 1) {
207 anv_finishme("Implement multi-arrayLayer HiZ clears and resolves");
208 } else if (dev->info.gen == 8 && vk_info->samples > 1) {
209 anv_finishme("Test gen8 multisampled HiZ");
210 } else {
211 assert(image->aux_surface.isl.size == 0);
212 ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
213 &image->aux_surface.isl);
214 assert(ok);
215 add_surface(image, &image->aux_surface);
216 image->aux_usage = ISL_AUX_USAGE_HIZ;
217 }
218 } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples == 1) {
219 if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
220 assert(image->aux_surface.isl.size == 0);
221 ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
222 &image->aux_surface.isl);
223 if (ok) {
224 add_surface(image, &image->aux_surface);
225
226 /* For images created without MUTABLE_FORMAT_BIT set, we know that
227 * they will always be used with the original format. In
228 * particular, they will always be used with a format that
229 * supports color compression. If it's never used as a storage
230 * image, then it will only be used through the sampler or the as
231 * a render target. This means that it's safe to just leave
232 * compression on at all times for these formats.
233 */
234 if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
235 !(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
236 isl_format_supports_ccs_e(&dev->info, format)) {
237 image->aux_usage = ISL_AUX_USAGE_CCS_E;
238 }
239 }
240 }
241 }
242
243 return VK_SUCCESS;
244 }
245
246 VkResult
247 anv_image_create(VkDevice _device,
248 const struct anv_image_create_info *create_info,
249 const VkAllocationCallbacks* alloc,
250 VkImage *pImage)
251 {
252 ANV_FROM_HANDLE(anv_device, device, _device);
253 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
254 struct anv_image *image = NULL;
255 VkResult r;
256
257 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
258
259 anv_assert(pCreateInfo->mipLevels > 0);
260 anv_assert(pCreateInfo->arrayLayers > 0);
261 anv_assert(pCreateInfo->samples > 0);
262 anv_assert(pCreateInfo->extent.width > 0);
263 anv_assert(pCreateInfo->extent.height > 0);
264 anv_assert(pCreateInfo->extent.depth > 0);
265
266 image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
267 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
268 if (!image)
269 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
270
271 memset(image, 0, sizeof(*image));
272 image->type = pCreateInfo->imageType;
273 image->extent = pCreateInfo->extent;
274 image->vk_format = pCreateInfo->format;
275 image->aspects = vk_format_aspects(image->vk_format);
276 image->levels = pCreateInfo->mipLevels;
277 image->array_size = pCreateInfo->arrayLayers;
278 image->samples = pCreateInfo->samples;
279 image->usage = pCreateInfo->usage;
280 image->tiling = pCreateInfo->tiling;
281 image->aux_usage = ISL_AUX_USAGE_NONE;
282
283 uint32_t b;
284 for_each_bit(b, image->aspects) {
285 r = make_surface(device, image, create_info, (1 << b));
286 if (r != VK_SUCCESS)
287 goto fail;
288 }
289
290 *pImage = anv_image_to_handle(image);
291
292 return VK_SUCCESS;
293
294 fail:
295 if (image)
296 vk_free2(&device->alloc, alloc, image);
297
298 return r;
299 }
300
301 VkResult
302 anv_CreateImage(VkDevice device,
303 const VkImageCreateInfo *pCreateInfo,
304 const VkAllocationCallbacks *pAllocator,
305 VkImage *pImage)
306 {
307 return anv_image_create(device,
308 &(struct anv_image_create_info) {
309 .vk_info = pCreateInfo,
310 },
311 pAllocator,
312 pImage);
313 }
314
315 void
316 anv_DestroyImage(VkDevice _device, VkImage _image,
317 const VkAllocationCallbacks *pAllocator)
318 {
319 ANV_FROM_HANDLE(anv_device, device, _device);
320 ANV_FROM_HANDLE(anv_image, image, _image);
321
322 if (!image)
323 return;
324
325 vk_free2(&device->alloc, pAllocator, image);
326 }
327
328 VkResult anv_BindImageMemory(
329 VkDevice _device,
330 VkImage _image,
331 VkDeviceMemory _memory,
332 VkDeviceSize memoryOffset)
333 {
334 ANV_FROM_HANDLE(anv_device, device, _device);
335 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
336 ANV_FROM_HANDLE(anv_image, image, _image);
337
338 if (mem) {
339 image->bo = &mem->bo;
340 image->offset = memoryOffset;
341 } else {
342 image->bo = NULL;
343 image->offset = 0;
344 }
345
346 if (image->aux_surface.isl.size > 0) {
347
348 /* The offset and size must be a multiple of 4K or else the
349 * anv_gem_mmap call below will return NULL.
350 */
351 assert((image->offset + image->aux_surface.offset) % 4096 == 0);
352 assert(image->aux_surface.isl.size % 4096 == 0);
353
354 /* Auxiliary surfaces need to have their memory cleared to 0 before they
355 * can be used. For CCS surfaces, this puts them in the "resolved"
356 * state so they can be used with CCS enabled before we ever touch it
357 * from the GPU. For HiZ, we need something valid or else we may get
358 * GPU hangs on some hardware and 0 works fine.
359 */
360 void *map = anv_gem_mmap(device, image->bo->gem_handle,
361 image->offset + image->aux_surface.offset,
362 image->aux_surface.isl.size,
363 device->info.has_llc ? 0 : I915_MMAP_WC);
364
365 /* If anv_gem_mmap returns NULL, it's likely that the kernel was
366 * not able to find space on the host to create a proper mapping.
367 */
368 if (map == NULL)
369 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
370
371 memset(map, 0, image->aux_surface.isl.size);
372
373 anv_gem_munmap(map, image->aux_surface.isl.size);
374 }
375
376 return VK_SUCCESS;
377 }
378
379 static void
380 anv_surface_get_subresource_layout(struct anv_image *image,
381 struct anv_surface *surface,
382 const VkImageSubresource *subresource,
383 VkSubresourceLayout *layout)
384 {
385 /* If we are on a non-zero mip level or array slice, we need to
386 * calculate a real offset.
387 */
388 anv_assert(subresource->mipLevel == 0);
389 anv_assert(subresource->arrayLayer == 0);
390
391 layout->offset = surface->offset;
392 layout->rowPitch = surface->isl.row_pitch;
393 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
394 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
395 layout->size = surface->isl.size;
396 }
397
398 void anv_GetImageSubresourceLayout(
399 VkDevice device,
400 VkImage _image,
401 const VkImageSubresource* pSubresource,
402 VkSubresourceLayout* pLayout)
403 {
404 ANV_FROM_HANDLE(anv_image, image, _image);
405
406 assert(__builtin_popcount(pSubresource->aspectMask) == 1);
407
408 switch (pSubresource->aspectMask) {
409 case VK_IMAGE_ASPECT_COLOR_BIT:
410 anv_surface_get_subresource_layout(image, &image->color_surface,
411 pSubresource, pLayout);
412 break;
413 case VK_IMAGE_ASPECT_DEPTH_BIT:
414 anv_surface_get_subresource_layout(image, &image->depth_surface,
415 pSubresource, pLayout);
416 break;
417 case VK_IMAGE_ASPECT_STENCIL_BIT:
418 anv_surface_get_subresource_layout(image, &image->stencil_surface,
419 pSubresource, pLayout);
420 break;
421 default:
422 assert(!"Invalid image aspect");
423 }
424 }
425
426 static struct anv_state
427 alloc_surface_state(struct anv_device *device)
428 {
429 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
430 }
431
432 static enum isl_channel_select
433 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
434 struct isl_swizzle format_swizzle)
435 {
436 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
437 swizzle = component;
438
439 switch (swizzle) {
440 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
441 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
442 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
443 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
444 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
445 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
446 default:
447 unreachable("Invalid swizzle");
448 }
449 }
450
451
452 VkResult
453 anv_CreateImageView(VkDevice _device,
454 const VkImageViewCreateInfo *pCreateInfo,
455 const VkAllocationCallbacks *pAllocator,
456 VkImageView *pView)
457 {
458 ANV_FROM_HANDLE(anv_device, device, _device);
459 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
460 struct anv_image_view *iview;
461
462 iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
463 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
464 if (iview == NULL)
465 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
466
467 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
468
469 assert(range->layerCount > 0);
470 assert(range->baseMipLevel < image->levels);
471 assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
472 VK_IMAGE_USAGE_STORAGE_BIT |
473 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
474 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
475
476 switch (image->type) {
477 default:
478 unreachable("bad VkImageType");
479 case VK_IMAGE_TYPE_1D:
480 case VK_IMAGE_TYPE_2D:
481 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
482 break;
483 case VK_IMAGE_TYPE_3D:
484 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
485 <= anv_minify(image->extent.depth, range->baseMipLevel));
486 break;
487 }
488
489 const struct anv_surface *surface =
490 anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
491
492 iview->image = image;
493 iview->bo = image->bo;
494 iview->offset = image->offset + surface->offset;
495
496 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
497 iview->vk_format = pCreateInfo->format;
498
499 struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
500 range->aspectMask, image->tiling);
501
502 iview->isl = (struct isl_view) {
503 .format = format.isl_format,
504 .base_level = range->baseMipLevel,
505 .levels = anv_get_levelCount(image, range),
506 .base_array_layer = range->baseArrayLayer,
507 .array_len = anv_get_layerCount(image, range),
508 .swizzle = {
509 .r = remap_swizzle(pCreateInfo->components.r,
510 VK_COMPONENT_SWIZZLE_R, format.swizzle),
511 .g = remap_swizzle(pCreateInfo->components.g,
512 VK_COMPONENT_SWIZZLE_G, format.swizzle),
513 .b = remap_swizzle(pCreateInfo->components.b,
514 VK_COMPONENT_SWIZZLE_B, format.swizzle),
515 .a = remap_swizzle(pCreateInfo->components.a,
516 VK_COMPONENT_SWIZZLE_A, format.swizzle),
517 },
518 };
519
520 iview->extent = (VkExtent3D) {
521 .width = anv_minify(image->extent.width , range->baseMipLevel),
522 .height = anv_minify(image->extent.height, range->baseMipLevel),
523 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
524 };
525
526 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
527 iview->isl.base_array_layer = 0;
528 iview->isl.array_len = iview->extent.depth;
529 }
530
531 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
532 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
533 iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
534 } else {
535 iview->isl.usage = 0;
536 }
537
538 /* If the HiZ buffer can be sampled from, set the constant clear color.
539 * If it cannot, disable the isl aux usage flag.
540 */
541 float red_clear_color = 0.0f;
542 enum isl_aux_usage surf_usage = image->aux_usage;
543 if (image->aux_usage == ISL_AUX_USAGE_HIZ) {
544 if (iview->aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT &&
545 anv_can_sample_with_hiz(device->info.gen, image->samples)) {
546 /* When a HiZ buffer is sampled on gen9+, ensure that
547 * the constant fast clear value is set in the surface state.
548 */
549 if (device->info.gen >= 9)
550 red_clear_color = ANV_HZ_FC_VAL;
551 } else {
552 surf_usage = ISL_AUX_USAGE_NONE;
553 }
554 }
555
556 /* Input attachment surfaces for color are allocated and filled
557 * out at BeginRenderPass time because they need compression information.
558 * Compression is not yet enabled for depth textures and stencil doesn't
559 * allow compression so we can just use the texture surface state from the
560 * view.
561 */
562 if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
563 (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
564 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
565 iview->sampler_surface_state = alloc_surface_state(device);
566
567 struct isl_view view = iview->isl;
568 view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
569 isl_surf_fill_state(&device->isl_dev,
570 iview->sampler_surface_state.map,
571 .surf = &surface->isl,
572 .view = &view,
573 .clear_color.f32 = { red_clear_color,},
574 .aux_surf = &image->aux_surface.isl,
575 .aux_usage = surf_usage,
576 .mocs = device->default_mocs);
577
578 anv_state_flush(device, iview->sampler_surface_state);
579 } else {
580 iview->sampler_surface_state.alloc_size = 0;
581 }
582
583 /* NOTE: This one needs to go last since it may stomp isl_view.format */
584 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
585 iview->storage_surface_state = alloc_surface_state(device);
586 iview->writeonly_storage_surface_state = alloc_surface_state(device);
587
588 struct isl_view view = iview->isl;
589 view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
590
591 /* Write-only accesses always used a typed write instruction and should
592 * therefore use the real format.
593 */
594 isl_surf_fill_state(&device->isl_dev,
595 iview->writeonly_storage_surface_state.map,
596 .surf = &surface->isl,
597 .view = &view,
598 .aux_surf = &image->aux_surface.isl,
599 .aux_usage = surf_usage,
600 .mocs = device->default_mocs);
601
602 if (isl_has_matching_typed_storage_image_format(&device->info,
603 format.isl_format)) {
604 /* Typed surface reads support a very limited subset of the shader
605 * image formats. Translate it into the closest format the hardware
606 * supports.
607 */
608 view.format = isl_lower_storage_image_format(&device->info,
609 format.isl_format);
610
611 isl_surf_fill_state(&device->isl_dev,
612 iview->storage_surface_state.map,
613 .surf = &surface->isl,
614 .view = &view,
615 .aux_surf = &image->aux_surface.isl,
616 .aux_usage = surf_usage,
617 .mocs = device->default_mocs);
618 } else {
619 anv_fill_buffer_surface_state(device, iview->storage_surface_state,
620 ISL_FORMAT_RAW,
621 iview->offset,
622 iview->bo->size - iview->offset, 1);
623 }
624
625 isl_surf_fill_image_param(&device->isl_dev,
626 &iview->storage_image_param,
627 &surface->isl, &iview->isl);
628
629 anv_state_flush(device, iview->storage_surface_state);
630 anv_state_flush(device, iview->writeonly_storage_surface_state);
631 } else {
632 iview->storage_surface_state.alloc_size = 0;
633 iview->writeonly_storage_surface_state.alloc_size = 0;
634 }
635
636 *pView = anv_image_view_to_handle(iview);
637
638 return VK_SUCCESS;
639 }
640
641 void
642 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
643 const VkAllocationCallbacks *pAllocator)
644 {
645 ANV_FROM_HANDLE(anv_device, device, _device);
646 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
647
648 if (!iview)
649 return;
650
651 if (iview->sampler_surface_state.alloc_size > 0) {
652 anv_state_pool_free(&device->surface_state_pool,
653 iview->sampler_surface_state);
654 }
655
656 if (iview->storage_surface_state.alloc_size > 0) {
657 anv_state_pool_free(&device->surface_state_pool,
658 iview->storage_surface_state);
659 }
660
661 if (iview->writeonly_storage_surface_state.alloc_size > 0) {
662 anv_state_pool_free(&device->surface_state_pool,
663 iview->writeonly_storage_surface_state);
664 }
665
666 vk_free2(&device->alloc, pAllocator, iview);
667 }
668
669
670 VkResult
671 anv_CreateBufferView(VkDevice _device,
672 const VkBufferViewCreateInfo *pCreateInfo,
673 const VkAllocationCallbacks *pAllocator,
674 VkBufferView *pView)
675 {
676 ANV_FROM_HANDLE(anv_device, device, _device);
677 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
678 struct anv_buffer_view *view;
679
680 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
681 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
682 if (!view)
683 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
684
685 /* TODO: Handle the format swizzle? */
686
687 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
688 VK_IMAGE_ASPECT_COLOR_BIT,
689 VK_IMAGE_TILING_LINEAR);
690 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
691 view->bo = buffer->bo;
692 view->offset = buffer->offset + pCreateInfo->offset;
693 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
694 buffer->size - pCreateInfo->offset : pCreateInfo->range;
695 view->range = align_down_npot_u32(view->range, format_bs);
696
697 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
698 view->surface_state = alloc_surface_state(device);
699
700 anv_fill_buffer_surface_state(device, view->surface_state,
701 view->format,
702 view->offset, view->range, format_bs);
703 } else {
704 view->surface_state = (struct anv_state){ 0 };
705 }
706
707 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
708 view->storage_surface_state = alloc_surface_state(device);
709 view->writeonly_storage_surface_state = alloc_surface_state(device);
710
711 enum isl_format storage_format =
712 isl_has_matching_typed_storage_image_format(&device->info,
713 view->format) ?
714 isl_lower_storage_image_format(&device->info, view->format) :
715 ISL_FORMAT_RAW;
716
717 anv_fill_buffer_surface_state(device, view->storage_surface_state,
718 storage_format,
719 view->offset, view->range,
720 (storage_format == ISL_FORMAT_RAW ? 1 :
721 isl_format_get_layout(storage_format)->bpb / 8));
722
723 /* Write-only accesses should use the original format. */
724 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
725 view->format,
726 view->offset, view->range,
727 isl_format_get_layout(view->format)->bpb / 8);
728
729 isl_buffer_fill_image_param(&device->isl_dev,
730 &view->storage_image_param,
731 view->format, view->range);
732 } else {
733 view->storage_surface_state = (struct anv_state){ 0 };
734 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
735 }
736
737 *pView = anv_buffer_view_to_handle(view);
738
739 return VK_SUCCESS;
740 }
741
742 void
743 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
744 const VkAllocationCallbacks *pAllocator)
745 {
746 ANV_FROM_HANDLE(anv_device, device, _device);
747 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
748
749 if (!view)
750 return;
751
752 if (view->surface_state.alloc_size > 0)
753 anv_state_pool_free(&device->surface_state_pool,
754 view->surface_state);
755
756 if (view->storage_surface_state.alloc_size > 0)
757 anv_state_pool_free(&device->surface_state_pool,
758 view->storage_surface_state);
759
760 if (view->writeonly_storage_surface_state.alloc_size > 0)
761 anv_state_pool_free(&device->surface_state_pool,
762 view->writeonly_storage_surface_state);
763
764 vk_free2(&device->alloc, pAllocator, view);
765 }
766
767 const struct anv_surface *
768 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
769 VkImageAspectFlags aspect_mask)
770 {
771 switch (aspect_mask) {
772 case VK_IMAGE_ASPECT_COLOR_BIT:
773 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
774 return &image->color_surface;
775 case VK_IMAGE_ASPECT_DEPTH_BIT:
776 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
777 return &image->depth_surface;
778 case VK_IMAGE_ASPECT_STENCIL_BIT:
779 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
780 return &image->stencil_surface;
781 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
782 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
783 * combined depth stencil formats. Specifically, it states:
784 *
785 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
786 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
787 *
788 * Image views with both depth and stencil aspects are only valid for
789 * render target attachments, in which case
790 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
791 * stencil surfaces from the underlying surface.
792 */
793 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
794 return &image->depth_surface;
795 } else {
796 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
797 return &image->stencil_surface;
798 }
799 default:
800 unreachable("image does not have aspect");
801 return NULL;
802 }
803 }