2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
35 #include "util/u_math.h"
37 #include "vk_format_info.h"
39 static isl_surf_usage_flags_t
40 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
41 VkImageUsageFlags vk_usage
,
42 isl_surf_usage_flags_t isl_extra_usage
,
43 VkImageAspectFlagBits aspect
)
45 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
47 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
48 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
50 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
51 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
53 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
54 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
56 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
57 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
64 case VK_IMAGE_ASPECT_DEPTH_BIT
:
65 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
67 case VK_IMAGE_ASPECT_STENCIL_BIT
:
68 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
70 case VK_IMAGE_ASPECT_COLOR_BIT
:
71 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
72 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
73 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
76 unreachable("bad VkImageAspect");
79 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
80 /* blorp implements transfers by sampling from the source image. */
81 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
84 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
85 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
86 /* blorp implements transfers by rendering into the destination image.
87 * Only request this with color images, as we deal with depth/stencil
88 * formats differently. */
89 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
95 static isl_tiling_flags_t
96 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
97 const struct isl_drm_modifier_info
*isl_mod_info
,
100 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
101 isl_tiling_flags_t flags
= 0;
103 switch (base_info
->tiling
) {
105 unreachable("bad VkImageTiling");
106 case VK_IMAGE_TILING_OPTIMAL
:
107 flags
= ISL_TILING_ANY_MASK
;
109 case VK_IMAGE_TILING_LINEAR
:
110 flags
= ISL_TILING_LINEAR_BIT
;
114 if (anv_info
->isl_tiling_flags
)
115 flags
&= anv_info
->isl_tiling_flags
;
118 flags
&= ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
;
121 flags
&= 1 << isl_mod_info
->tiling
;
128 static struct anv_surface
*
129 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
131 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
132 return &image
->planes
[plane
].surface
;
136 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
138 assert(surf
->isl
.size_B
> 0); /* isl surface must be initialized */
140 if (image
->disjoint
) {
141 surf
->offset
= align_u32(image
->planes
[plane
].size
,
142 surf
->isl
.alignment_B
);
143 /* Plane offset is always 0 when it's disjoint. */
145 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment_B
);
146 /* Determine plane's offset only once when the first surface is added. */
147 if (image
->planes
[plane
].size
== 0)
148 image
->planes
[plane
].offset
= image
->size
;
151 image
->size
= surf
->offset
+ surf
->isl
.size_B
;
152 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size_B
) - image
->planes
[plane
].offset
;
154 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment_B
);
155 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
156 surf
->isl
.alignment_B
);
161 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
162 const VkImageFormatListCreateInfoKHR
*fmt_list
,
163 struct anv_image
*image
)
165 enum isl_format format
=
166 anv_get_isl_format(devinfo
, image
->vk_format
,
167 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
169 if (!isl_format_supports_ccs_e(devinfo
, format
))
172 if (!(image
->create_flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
175 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
178 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
179 enum isl_format view_format
=
180 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
181 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
183 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
191 * For color images that have an auxiliary surface, request allocation for an
192 * additional buffer that mainly stores fast-clear values. Use of this buffer
193 * allows us to access the image's subresources while being aware of their
194 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
195 * which a fast clear has occurred).
197 * In order to avoid having multiple clear colors for a single plane of an
198 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
199 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
200 * 2018), there were no known applications which would benefit from fast-
201 * clearing more than just the first slice.
203 * The fast clear portion of the image is laid out in the following order:
205 * * 1 or 4 dwords (depending on hardware generation) for the clear color
206 * * 1 dword for the anv_fast_clear_type of the clear color
207 * * On gen9+, 1 dword per level and layer of the image (3D levels count
208 * multiple layers) in level-major order for compression state.
210 * For the purpose of discoverability, the algorithm used to manage
211 * compression and fast-clears is described here:
213 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
214 * all of the values in the fast clear portion of the image are initialized
217 * * On fast-clear, the clear value is written into surface state and also
218 * into the buffer and the fast clear type is set appropriately. Both
219 * setting the fast-clear value in the buffer and setting the fast-clear
220 * type happen from the GPU using MI commands.
222 * * Whenever a render or blorp operation is performed with CCS_E, we call
223 * genX(cmd_buffer_mark_image_written) to set the compression state to
224 * true (which is represented by UINT32_MAX).
226 * * On pipeline barrier transitions, the worst-case transition is computed
227 * from the image layouts. The command streamer inspects the fast clear
228 * type and compression state dwords and constructs a predicate. The
229 * worst-case resolve is performed with the given predicate and the fast
230 * clear and compression state is set accordingly.
232 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
233 * details on exactly what is allowed in what layouts.
235 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
236 * In order to deal with this, we have to do some clear color management.
238 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
239 * value from the buffer into the surface state with MI commands.
241 * * For any blorp operations, we pass the address to the clear value into
242 * blorp and it knows to copy the clear color.
245 add_aux_state_tracking_buffer(struct anv_image
*image
,
247 const struct anv_device
*device
)
249 assert(image
&& device
);
250 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 &&
251 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
253 /* Compressed images must be tiled and therefore everything should be 4K
254 * aligned. The CCS has the same alignment requirements. This is good
255 * because we need at least dword-alignment for MI_LOAD/STORE operations.
257 assert(image
->alignment
% 4 == 0);
258 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
260 /* This buffer should be at the very end of the plane. */
261 if (image
->disjoint
) {
262 assert(image
->planes
[plane
].size
==
263 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
265 assert(image
->size
==
266 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
269 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
270 device
->isl_dev
.ss
.clear_color_state_size
:
271 device
->isl_dev
.ss
.clear_value_size
;
273 /* Clear color and fast clear type */
274 unsigned state_size
= clear_color_state_size
+ 4;
276 /* We only need to track compression on CCS_E surfaces. */
277 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
278 if (image
->type
== VK_IMAGE_TYPE_3D
) {
279 for (uint32_t l
= 0; l
< image
->levels
; l
++)
280 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
282 state_size
+= image
->levels
* image
->array_size
* 4;
286 image
->planes
[plane
].fast_clear_state_offset
=
287 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
289 image
->planes
[plane
].size
+= state_size
;
290 image
->size
+= state_size
;
294 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
295 * image's memory requirements (that is, the image's size and alignment).
298 make_surface(const struct anv_device
*dev
,
299 struct anv_image
*image
,
301 isl_tiling_flags_t tiling_flags
,
302 isl_surf_usage_flags_t isl_extra_usage_flags
,
303 VkImageAspectFlagBits aspect
)
307 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
308 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
309 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
310 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
313 image
->extent
= anv_sanitize_image_extent(image
->type
, image
->extent
);
315 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
316 const struct anv_format_plane plane_format
=
317 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
318 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
320 const isl_surf_usage_flags_t usage
=
321 choose_isl_surf_usage(image
->create_flags
, image
->usage
,
322 isl_extra_usage_flags
, aspect
);
324 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
325 * fall back to linear on Broadwell and earlier because we aren't
326 * guaranteed that we can handle offsets correctly. On Sky Lake, the
327 * horizontal and vertical alignments are sufficiently high that we can
328 * just use RENDER_SURFACE_STATE::X/Y Offset.
330 bool needs_shadow
= false;
331 if (dev
->info
.gen
<= 8 &&
332 (image
->create_flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT
) &&
333 image
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
334 assert(isl_format_is_compressed(plane_format
.isl_format
));
335 tiling_flags
= ISL_TILING_LINEAR_BIT
;
339 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
340 .dim
= vk_to_isl_surf_dim
[image
->type
],
341 .format
= plane_format
.isl_format
,
342 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
343 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
344 .depth
= image
->extent
.depth
,
345 .levels
= image
->levels
,
346 .array_len
= image
->array_size
,
347 .samples
= image
->samples
,
348 .min_alignment_B
= 0,
349 .row_pitch_B
= stride
,
351 .tiling_flags
= tiling_flags
);
354 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
356 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
358 add_surface(image
, anv_surf
, plane
);
360 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
361 * create an identical tiled shadow surface for use while texturing so we
362 * don't get garbage performance.
365 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
366 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
368 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
369 .dim
= vk_to_isl_surf_dim
[image
->type
],
370 .format
= plane_format
.isl_format
,
371 .width
= image
->extent
.width
,
372 .height
= image
->extent
.height
,
373 .depth
= image
->extent
.depth
,
374 .levels
= image
->levels
,
375 .array_len
= image
->array_size
,
376 .samples
= image
->samples
,
377 .min_alignment_B
= 0,
378 .row_pitch_B
= stride
,
380 .tiling_flags
= ISL_TILING_ANY_MASK
);
382 /* isl_surf_init() will fail only if provided invalid input. Invalid input
383 * is illegal in Vulkan.
387 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
390 /* Add a HiZ surface to a depth buffer that will be used for rendering.
392 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
393 /* We don't advertise that depth buffers could be used as storage
396 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
398 /* Allow the user to control HiZ enabling. Disable by default on gen7
399 * because resolves are not currently implemented pre-BDW.
401 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
402 /* It will never be used as an attachment, HiZ is pointless. */
403 } else if (dev
->info
.gen
== 7) {
404 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
405 } else if (image
->levels
> 1) {
406 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
407 } else if (image
->array_size
> 1) {
408 anv_perf_warn(dev
->instance
, image
,
409 "Implement multi-arrayLayer HiZ clears and resolves");
410 } else if (dev
->info
.gen
== 8 && image
->samples
> 1) {
411 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
412 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
413 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
414 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
415 &image
->planes
[plane
].surface
.isl
,
416 &image
->planes
[plane
].aux_surface
.isl
);
418 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
419 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
421 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && image
->samples
== 1) {
422 /* TODO: Disallow compression with :
424 * 1) non multiplanar images (We appear to hit a sampler bug with
425 * CCS & R16G16 format. Putting the clear state a page/4096bytes
426 * further fixes the issue).
428 * 2) alias images, because they might be aliases of images
431 * 3) compression disabled by debug
433 const bool allow_compression
=
434 image
->n_planes
== 1 &&
435 (image
->create_flags
& VK_IMAGE_CREATE_ALIAS_BIT
) == 0 &&
436 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
438 if (allow_compression
) {
439 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
440 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
441 &image
->planes
[plane
].surface
.isl
,
442 &image
->planes
[plane
].aux_surface
.isl
, 0);
445 /* Disable CCS when it is not useful (i.e., when you can't render
446 * to the image with CCS enabled).
448 if (!isl_format_supports_rendering(&dev
->info
,
449 plane_format
.isl_format
)) {
450 /* While it may be technically possible to enable CCS for this
451 * image, we currently don't have things hooked up to get it
454 anv_perf_warn(dev
->instance
, image
,
455 "This image format doesn't support rendering. "
456 "Not allocating an CCS buffer.");
457 image
->planes
[plane
].aux_surface
.isl
.size_B
= 0;
461 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
462 add_aux_state_tracking_buffer(image
, plane
, dev
);
464 /* For images created without MUTABLE_FORMAT_BIT set, we know that
465 * they will always be used with the original format. In
466 * particular, they will always be used with a format that
467 * supports color compression. If it's never used as a storage
468 * image, then it will only be used through the sampler or the as
469 * a render target. This means that it's safe to just leave
470 * compression on at all times for these formats.
472 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
473 image
->ccs_e_compatible
) {
474 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
478 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && image
->samples
> 1) {
479 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
480 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
481 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
482 &image
->planes
[plane
].surface
.isl
,
483 &image
->planes
[plane
].aux_surface
.isl
);
485 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
486 add_aux_state_tracking_buffer(image
, plane
, dev
);
487 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
491 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
493 /* Upper bound of the last surface should be smaller than the plane's
496 assert((MAX2(image
->planes
[plane
].surface
.offset
,
497 image
->planes
[plane
].aux_surface
.offset
) +
498 (image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
499 image
->planes
[plane
].aux_surface
.isl
.size_B
:
500 image
->planes
[plane
].surface
.isl
.size_B
)) <=
501 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
503 if (image
->planes
[plane
].aux_surface
.isl
.size_B
) {
504 /* assert(image->planes[plane].fast_clear_state_offset == */
505 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
506 assert(image
->planes
[plane
].fast_clear_state_offset
<
507 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
514 score_drm_format_mod(uint64_t modifier
)
517 case DRM_FORMAT_MOD_LINEAR
: return 1;
518 case I915_FORMAT_MOD_X_TILED
: return 2;
519 case I915_FORMAT_MOD_Y_TILED
: return 3;
520 case I915_FORMAT_MOD_Y_TILED_CCS
: return 4;
521 default: unreachable("bad DRM format modifier");
525 static const struct isl_drm_modifier_info
*
526 choose_drm_format_mod(const struct anv_physical_device
*device
,
527 uint32_t modifier_count
, const uint64_t *modifiers
)
529 uint64_t best_mod
= UINT64_MAX
;
530 uint32_t best_score
= 0;
532 for (uint32_t i
= 0; i
< modifier_count
; ++i
) {
533 uint32_t score
= score_drm_format_mod(modifiers
[i
]);
534 if (score
> best_score
) {
535 best_mod
= modifiers
[i
];
541 return isl_drm_modifier_get_info(best_mod
);
547 anv_image_create(VkDevice _device
,
548 const struct anv_image_create_info
*create_info
,
549 const VkAllocationCallbacks
* alloc
,
552 ANV_FROM_HANDLE(anv_device
, device
, _device
);
553 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
554 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
555 struct anv_image
*image
= NULL
;
558 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
560 const struct wsi_image_create_info
*wsi_info
=
561 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
562 if (wsi_info
&& wsi_info
->modifier_count
> 0) {
563 isl_mod_info
= choose_drm_format_mod(&device
->instance
->physicalDevice
,
564 wsi_info
->modifier_count
,
565 wsi_info
->modifiers
);
566 assert(isl_mod_info
);
569 anv_assert(pCreateInfo
->mipLevels
> 0);
570 anv_assert(pCreateInfo
->arrayLayers
> 0);
571 anv_assert(pCreateInfo
->samples
> 0);
572 anv_assert(pCreateInfo
->extent
.width
> 0);
573 anv_assert(pCreateInfo
->extent
.height
> 0);
574 anv_assert(pCreateInfo
->extent
.depth
> 0);
576 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
577 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
579 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
581 image
->type
= pCreateInfo
->imageType
;
582 image
->extent
= pCreateInfo
->extent
;
583 image
->vk_format
= pCreateInfo
->format
;
584 image
->format
= anv_get_format(pCreateInfo
->format
);
585 image
->aspects
= vk_format_aspects(image
->vk_format
);
586 image
->levels
= pCreateInfo
->mipLevels
;
587 image
->array_size
= pCreateInfo
->arrayLayers
;
588 image
->samples
= pCreateInfo
->samples
;
589 image
->usage
= pCreateInfo
->usage
;
590 image
->create_flags
= pCreateInfo
->flags
;
591 image
->tiling
= pCreateInfo
->tiling
;
592 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT
;
593 image
->needs_set_tiling
= wsi_info
&& wsi_info
->scanout
;
594 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
595 DRM_FORMAT_MOD_INVALID
;
597 /* In case of external format, We don't know format yet,
598 * so skip the rest for now.
600 if (create_info
->external_format
) {
601 image
->external_format
= true;
602 *pImage
= anv_image_to_handle(image
);
606 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
607 assert(format
!= NULL
);
609 const isl_tiling_flags_t isl_tiling_flags
=
610 choose_isl_tiling_flags(create_info
, isl_mod_info
,
611 image
->needs_set_tiling
);
613 image
->n_planes
= format
->n_planes
;
615 const VkImageFormatListCreateInfoKHR
*fmt_list
=
616 vk_find_struct_const(pCreateInfo
->pNext
,
617 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
619 image
->ccs_e_compatible
=
620 all_formats_ccs_e_compatible(&device
->info
, fmt_list
, image
);
623 for_each_bit(b
, image
->aspects
) {
624 r
= make_surface(device
, image
, create_info
->stride
, isl_tiling_flags
,
625 create_info
->isl_extra_usage_flags
, (1 << b
));
630 *pImage
= anv_image_to_handle(image
);
636 vk_free2(&device
->alloc
, alloc
, image
);
642 anv_CreateImage(VkDevice device
,
643 const VkImageCreateInfo
*pCreateInfo
,
644 const VkAllocationCallbacks
*pAllocator
,
647 const struct VkExternalMemoryImageCreateInfo
*create_info
=
648 vk_find_struct_const(pCreateInfo
->pNext
, EXTERNAL_MEMORY_IMAGE_CREATE_INFO
);
650 if (create_info
&& (create_info
->handleTypes
&
651 VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))
652 return anv_image_from_external(device
, pCreateInfo
, create_info
,
655 const VkNativeBufferANDROID
*gralloc_info
=
656 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
658 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
661 return anv_image_create(device
,
662 &(struct anv_image_create_info
) {
663 .vk_info
= pCreateInfo
,
670 anv_DestroyImage(VkDevice _device
, VkImage _image
,
671 const VkAllocationCallbacks
*pAllocator
)
673 ANV_FROM_HANDLE(anv_device
, device
, _device
);
674 ANV_FROM_HANDLE(anv_image
, image
, _image
);
679 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
680 if (image
->planes
[p
].bo_is_owned
) {
681 assert(image
->planes
[p
].address
.bo
!= NULL
);
682 anv_bo_cache_release(device
, &device
->bo_cache
,
683 image
->planes
[p
].address
.bo
);
687 vk_free2(&device
->alloc
, pAllocator
, image
);
690 static void anv_image_bind_memory_plane(struct anv_device
*device
,
691 struct anv_image
*image
,
693 struct anv_device_memory
*memory
,
694 uint32_t memory_offset
)
696 assert(!image
->planes
[plane
].bo_is_owned
);
699 image
->planes
[plane
].address
= ANV_NULL_ADDRESS
;
703 image
->planes
[plane
].address
= (struct anv_address
) {
705 .offset
= memory_offset
,
709 /* We are binding AHardwareBuffer. Get a description, resolve the
710 * format and prepare anv_image properly.
713 resolve_ahw_image(struct anv_device
*device
,
714 struct anv_image
*image
,
715 struct anv_device_memory
*mem
)
719 AHardwareBuffer_Desc desc
;
720 AHardwareBuffer_describe(mem
->ahw
, &desc
);
723 int i915_tiling
= anv_gem_get_tiling(device
, mem
->bo
->gem_handle
);
724 VkImageTiling vk_tiling
;
725 isl_tiling_flags_t isl_tiling_flags
= 0;
727 switch (i915_tiling
) {
728 case I915_TILING_NONE
:
729 vk_tiling
= VK_IMAGE_TILING_LINEAR
;
730 isl_tiling_flags
= ISL_TILING_LINEAR_BIT
;
733 vk_tiling
= VK_IMAGE_TILING_OPTIMAL
;
734 isl_tiling_flags
= ISL_TILING_X_BIT
;
737 vk_tiling
= VK_IMAGE_TILING_OPTIMAL
;
738 isl_tiling_flags
= ISL_TILING_Y0_BIT
;
742 unreachable("Invalid tiling flags.");
745 assert(vk_tiling
== VK_IMAGE_TILING_LINEAR
||
746 vk_tiling
== VK_IMAGE_TILING_OPTIMAL
);
749 VkFormat vk_format
= vk_format_from_android(desc
.format
);
750 enum isl_format isl_fmt
= anv_get_isl_format(&device
->info
,
752 VK_IMAGE_ASPECT_COLOR_BIT
,
754 assert(format
!= ISL_FORMAT_UNSUPPORTED
);
756 /* Handle RGB(X)->RGBA fallback. */
757 switch (desc
.format
) {
758 case AHARDWAREBUFFER_FORMAT_R8G8B8_UNORM
:
759 case AHARDWAREBUFFER_FORMAT_R8G8B8X8_UNORM
:
760 if (isl_format_is_rgb(isl_fmt
))
761 isl_fmt
= isl_format_rgb_to_rgba(isl_fmt
);
765 /* Now we are able to fill anv_image fields properly and create
766 * isl_surface for it.
768 image
->vk_format
= vk_format
;
769 image
->format
= anv_get_format(vk_format
);
770 image
->aspects
= vk_format_aspects(image
->vk_format
);
771 image
->n_planes
= image
->format
->n_planes
;
772 image
->ccs_e_compatible
= false;
774 uint32_t stride
= desc
.stride
*
775 (isl_format_get_layout(isl_fmt
)->bpb
/ 8);
778 for_each_bit(b
, image
->aspects
) {
779 VkResult r
= make_surface(device
, image
, stride
, isl_tiling_flags
,
780 ISL_SURF_USAGE_DISABLE_AUX_BIT
, (1 << b
));
781 assert(r
== VK_SUCCESS
);
786 VkResult
anv_BindImageMemory(
789 VkDeviceMemory _memory
,
790 VkDeviceSize memoryOffset
)
792 ANV_FROM_HANDLE(anv_device
, device
, _device
);
793 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
794 ANV_FROM_HANDLE(anv_image
, image
, _image
);
797 resolve_ahw_image(device
, image
, mem
);
800 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
802 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
803 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
809 VkResult
anv_BindImageMemory2(
811 uint32_t bindInfoCount
,
812 const VkBindImageMemoryInfo
* pBindInfos
)
814 ANV_FROM_HANDLE(anv_device
, device
, _device
);
816 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
817 const VkBindImageMemoryInfo
*bind_info
= &pBindInfos
[i
];
818 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
819 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
822 resolve_ahw_image(device
, image
, mem
);
824 VkImageAspectFlags aspects
= image
->aspects
;
825 vk_foreach_struct_const(s
, bind_info
->pNext
) {
827 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO
: {
828 const VkBindImagePlaneMemoryInfo
*plane_info
=
829 (const VkBindImagePlaneMemoryInfo
*) s
;
831 aspects
= plane_info
->planeAspect
;
835 anv_debug_ignored_stype(s
->sType
);
841 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
843 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
844 anv_image_bind_memory_plane(device
, image
, plane
,
845 mem
, bind_info
->memoryOffset
);
852 void anv_GetImageSubresourceLayout(
855 const VkImageSubresource
* subresource
,
856 VkSubresourceLayout
* layout
)
858 ANV_FROM_HANDLE(anv_image
, image
, _image
);
860 const struct anv_surface
*surface
;
861 if (subresource
->aspectMask
== VK_IMAGE_ASPECT_PLANE_1_BIT
&&
862 image
->drm_format_mod
!= DRM_FORMAT_MOD_INVALID
&&
863 isl_drm_modifier_has_aux(image
->drm_format_mod
))
864 surface
= &image
->planes
[0].aux_surface
;
866 surface
= get_surface(image
, subresource
->aspectMask
);
868 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
870 layout
->offset
= surface
->offset
;
871 layout
->rowPitch
= surface
->isl
.row_pitch_B
;
872 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
873 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
875 if (subresource
->mipLevel
> 0 || subresource
->arrayLayer
> 0) {
876 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
879 isl_surf_get_image_offset_B_tile_sa(&surface
->isl
,
880 subresource
->mipLevel
,
881 subresource
->arrayLayer
,
882 0 /* logical_z_offset_px */,
883 &offset_B
, NULL
, NULL
);
884 layout
->offset
+= offset_B
;
885 layout
->size
= layout
->rowPitch
* anv_minify(image
->extent
.height
,
886 subresource
->mipLevel
);
888 layout
->size
= surface
->isl
.size_B
;
893 * This function determines the optimal buffer to use for a given
894 * VkImageLayout and other pieces of information needed to make that
895 * determination. This does not determine the optimal buffer to use
896 * during a resolve operation.
898 * @param devinfo The device information of the Intel GPU.
899 * @param image The image that may contain a collection of buffers.
900 * @param aspect The aspect of the image to be accessed.
901 * @param layout The current layout of the image aspect(s).
903 * @return The primary buffer that should be used for the given layout.
906 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
907 const struct anv_image
* const image
,
908 const VkImageAspectFlagBits aspect
,
909 const VkImageLayout layout
)
911 /* Validate the inputs. */
913 /* The devinfo is needed as the optimal buffer varies across generations. */
914 assert(devinfo
!= NULL
);
916 /* The layout of a NULL image is not properly defined. */
917 assert(image
!= NULL
);
919 /* The aspect must be exactly one of the image aspects. */
920 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
922 /* Determine the optimal buffer. */
924 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
926 /* If there is no auxiliary surface allocated, we must use the one and only
929 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
930 return ISL_AUX_USAGE_NONE
;
932 /* All images that use an auxiliary surface are required to be tiled. */
933 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
935 /* Stencil has no aux */
936 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
940 /* Invalid Layouts */
941 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
942 case VK_IMAGE_LAYOUT_MAX_ENUM
:
943 unreachable("Invalid image layout.");
947 * The pre-initialized layout is equivalent to the undefined layout for
948 * optimally-tiled images. We can only do color compression (CCS or HiZ)
951 case VK_IMAGE_LAYOUT_UNDEFINED
:
952 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
953 return ISL_AUX_USAGE_NONE
;
958 case VK_IMAGE_LAYOUT_GENERAL
:
959 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
960 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
961 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
962 /* This buffer could be a depth buffer used in a transfer operation.
963 * BLORP currently doesn't use HiZ for transfer operations so we must
964 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
966 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
967 return ISL_AUX_USAGE_NONE
;
969 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
970 return image
->planes
[plane
].aux_usage
;
974 /* Sampling Layouts */
975 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
976 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
:
977 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
979 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
980 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
981 if (anv_can_sample_with_hiz(devinfo
, image
))
982 return ISL_AUX_USAGE_HIZ
;
984 return ISL_AUX_USAGE_NONE
;
986 return image
->planes
[plane
].aux_usage
;
990 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
991 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
993 /* When handing the image off to the presentation engine, we need to
994 * ensure that things are properly resolved. For images with no
995 * modifier, we assume that they follow the old rules and always need
996 * a full resolve because the PE doesn't understand any form of
997 * compression. For images with modifiers, we use the aux usage from
1000 const struct isl_drm_modifier_info
*mod_info
=
1001 isl_drm_modifier_get_info(image
->drm_format_mod
);
1002 return mod_info
? mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
1006 /* Rendering Layouts */
1007 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
1008 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1009 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
1010 assert(image
->samples
== 1);
1011 return ISL_AUX_USAGE_CCS_D
;
1013 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
1014 return image
->planes
[plane
].aux_usage
;
1017 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
1018 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
:
1019 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
1020 return ISL_AUX_USAGE_HIZ
;
1022 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
1023 unreachable("VK_KHR_shared_presentable_image is unsupported");
1025 case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
:
1026 unreachable("VK_EXT_fragment_density_map is unsupported");
1028 case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV
:
1029 unreachable("VK_NV_shading_rate_image is unsupported");
1032 /* If the layout isn't recognized in the exhaustive switch above, the
1033 * VkImageLayout value is not defined in vulkan.h.
1035 unreachable("layout is not a VkImageLayout enumeration member.");
1039 * This function returns the level of unresolved fast-clear support of the
1040 * given image in the given VkImageLayout.
1042 * @param devinfo The device information of the Intel GPU.
1043 * @param image The image that may contain a collection of buffers.
1044 * @param aspect The aspect of the image to be accessed.
1045 * @param layout The current layout of the image aspect(s).
1047 enum anv_fast_clear_type
1048 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
1049 const struct anv_image
* const image
,
1050 const VkImageAspectFlagBits aspect
,
1051 const VkImageLayout layout
)
1053 /* The aspect must be exactly one of the image aspects. */
1054 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
1056 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1058 /* If there is no auxiliary surface allocated, there are no fast-clears */
1059 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
1060 return ANV_FAST_CLEAR_NONE
;
1062 /* All images that use an auxiliary surface are required to be tiled. */
1063 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1065 /* Stencil has no aux */
1066 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
1068 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1069 /* For depth images (with HiZ), the layout supports fast-clears if and
1070 * only if it supports HiZ. However, we only support fast-clears to the
1071 * default depth value.
1073 enum isl_aux_usage aux_usage
=
1074 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
1075 return aux_usage
== ISL_AUX_USAGE_HIZ
?
1076 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
1079 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1081 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
1082 * lack the MI ALU which we need to determine the predicates.
1084 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& image
->samples
> 1)
1085 return ANV_FAST_CLEAR_NONE
;
1088 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
1089 return ANV_FAST_CLEAR_ANY
;
1091 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
1092 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1094 /* We do not yet support any modifiers which support clear color so we
1095 * just always return NONE. One day, this will change.
1097 const struct isl_drm_modifier_info
*mod_info
=
1098 isl_drm_modifier_get_info(image
->drm_format_mod
);
1099 assert(!mod_info
|| !mod_info
->supports_clear_color
);
1101 return ANV_FAST_CLEAR_NONE
;
1105 /* If the image has MCS or CCS_E enabled all the time then we can use
1106 * fast-clear as long as the clear color is the default value of zero
1107 * since this is the default value we program into every surface state
1108 * used for texturing.
1110 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_MCS
||
1111 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
1112 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
1114 return ANV_FAST_CLEAR_NONE
;
1119 static struct anv_state
1120 alloc_surface_state(struct anv_device
*device
)
1122 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
1125 static enum isl_channel_select
1126 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
1127 struct isl_swizzle format_swizzle
)
1129 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
1130 swizzle
= component
;
1133 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
1134 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
1135 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
1136 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
1137 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
1138 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
1140 unreachable("Invalid swizzle");
1145 anv_image_fill_surface_state(struct anv_device
*device
,
1146 const struct anv_image
*image
,
1147 VkImageAspectFlagBits aspect
,
1148 const struct isl_view
*view_in
,
1149 isl_surf_usage_flags_t view_usage
,
1150 enum isl_aux_usage aux_usage
,
1151 const union isl_color_value
*clear_color
,
1152 enum anv_image_view_state_flags flags
,
1153 struct anv_surface_state
*state_inout
,
1154 struct brw_image_param
*image_param_out
)
1156 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1158 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
1159 *aux_surface
= &image
->planes
[plane
].aux_surface
;
1161 struct isl_view view
= *view_in
;
1162 view
.usage
|= view_usage
;
1164 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1165 * compressed surface with a shadow surface, we use the shadow instead of
1166 * the primary surface. The shadow surface will be tiled, unlike the main
1167 * surface, so it should get significantly better performance.
1169 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1170 isl_format_is_compressed(view
.format
) &&
1171 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
1172 assert(isl_format_is_compressed(surface
->isl
.format
));
1173 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1174 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1175 surface
= &image
->planes
[plane
].shadow_surface
;
1178 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1179 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1181 /* If this is a HiZ buffer we can sample from with a programmable clear
1182 * value (SKL+), define the clear value to the optimal constant.
1184 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1185 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1186 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1188 clear_color
= &default_clear_color
;
1190 const struct anv_address address
=
1191 anv_address_add(image
->planes
[plane
].address
, surface
->offset
);
1193 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1194 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1195 !isl_has_matching_typed_storage_image_format(&device
->info
,
1197 /* In this case, we are a writeable storage buffer which needs to be
1198 * lowered to linear. All tiling and offset calculations will be done in
1201 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1202 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1203 .address
= anv_address_physical(address
),
1204 .size_B
= surface
->isl
.size_B
,
1205 .format
= ISL_FORMAT_RAW
,
1207 .mocs
= anv_mocs_for_bo(device
, address
.bo
));
1208 state_inout
->address
= address
,
1209 state_inout
->aux_address
= ANV_NULL_ADDRESS
;
1210 state_inout
->clear_address
= ANV_NULL_ADDRESS
;
1212 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1213 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1214 /* Typed surface reads support a very limited subset of the shader
1215 * image formats. Translate it into the closest format the hardware
1218 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1219 view
.format
= isl_lower_storage_image_format(&device
->info
,
1223 const struct isl_surf
*isl_surf
= &surface
->isl
;
1225 struct isl_surf tmp_surf
;
1226 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1227 if (isl_format_is_compressed(surface
->isl
.format
) &&
1228 !isl_format_is_compressed(view
.format
)) {
1229 /* We're creating an uncompressed view of a compressed surface. This
1230 * is allowed but only for a single level/layer.
1232 assert(surface
->isl
.samples
== 1);
1233 assert(view
.levels
== 1);
1234 assert(view
.array_len
== 1);
1236 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1238 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1239 0 : view
.base_array_layer
,
1240 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1241 view
.base_array_layer
: 0,
1243 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1245 /* The newly created image represents the one subimage we're
1246 * referencing with this view so it only has one array slice and
1249 view
.base_array_layer
= 0;
1250 view
.base_level
= 0;
1252 /* We're making an uncompressed view here. The image dimensions need
1253 * to be scaled down by the block size.
1255 const struct isl_format_layout
*fmtl
=
1256 isl_format_get_layout(surface
->isl
.format
);
1257 tmp_surf
.format
= view
.format
;
1258 tmp_surf
.logical_level0_px
.width
=
1259 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1260 tmp_surf
.logical_level0_px
.height
=
1261 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1262 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1263 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1264 tile_x_sa
/= fmtl
->bw
;
1265 tile_y_sa
/= fmtl
->bh
;
1267 isl_surf
= &tmp_surf
;
1269 if (device
->info
.gen
<= 8) {
1270 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1271 assert(tile_x_sa
== 0);
1272 assert(tile_y_sa
== 0);
1276 state_inout
->address
= anv_address_add(address
, offset_B
);
1278 struct anv_address aux_address
= ANV_NULL_ADDRESS
;
1279 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1280 aux_address
= anv_address_add(image
->planes
[plane
].address
,
1281 aux_surface
->offset
);
1283 state_inout
->aux_address
= aux_address
;
1285 struct anv_address clear_address
= ANV_NULL_ADDRESS
;
1286 if (device
->info
.gen
>= 10 && aux_usage
!= ISL_AUX_USAGE_NONE
) {
1287 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1288 clear_address
= (struct anv_address
) {
1289 .bo
= &device
->hiz_clear_bo
,
1293 clear_address
= anv_image_get_clear_color_addr(device
, image
, aspect
);
1296 state_inout
->clear_address
= clear_address
;
1298 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1301 .address
= anv_address_physical(state_inout
->address
),
1302 .clear_color
= *clear_color
,
1303 .aux_surf
= &aux_surface
->isl
,
1304 .aux_usage
= aux_usage
,
1305 .aux_address
= anv_address_physical(aux_address
),
1306 .clear_address
= anv_address_physical(clear_address
),
1307 .use_clear_address
= !anv_address_is_null(clear_address
),
1308 .mocs
= anv_mocs_for_bo(device
,
1309 state_inout
->address
.bo
),
1310 .x_offset_sa
= tile_x_sa
,
1311 .y_offset_sa
= tile_y_sa
);
1313 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1314 * are used to store other information. This should be ok, however,
1315 * because the surface buffer addresses are always 4K page aligned.
1317 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1318 device
->isl_dev
.ss
.aux_addr_offset
;
1319 assert((aux_address
.offset
& 0xfff) == 0);
1320 state_inout
->aux_address
.offset
|= *aux_addr_dw
& 0xfff;
1322 if (device
->info
.gen
>= 10 && clear_address
.bo
) {
1323 uint32_t *clear_addr_dw
= state_inout
->state
.map
+
1324 device
->isl_dev
.ss
.clear_color_state_offset
;
1325 assert((clear_address
.offset
& 0x3f) == 0);
1326 state_inout
->clear_address
.offset
|= *clear_addr_dw
& 0x3f;
1330 anv_state_flush(device
, state_inout
->state
);
1332 if (image_param_out
) {
1333 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1334 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1335 &surface
->isl
, &view
);
1339 static VkImageAspectFlags
1340 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1342 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1343 if (util_bitcount(view_aspects
) == 1)
1344 return VK_IMAGE_ASPECT_COLOR_BIT
;
1346 VkImageAspectFlags color_aspects
= 0;
1347 for (uint32_t i
= 0; i
< util_bitcount(view_aspects
); i
++)
1348 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT
<< i
;
1349 return color_aspects
;
1351 /* No special remapping needed for depth & stencil aspects. */
1352 return view_aspects
;
1356 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
1358 uint32_t planes
= 0;
1360 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
1361 VK_IMAGE_ASPECT_DEPTH_BIT
|
1362 VK_IMAGE_ASPECT_STENCIL_BIT
|
1363 VK_IMAGE_ASPECT_PLANE_0_BIT
))
1365 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
1367 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
1370 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
1371 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
1378 anv_CreateImageView(VkDevice _device
,
1379 const VkImageViewCreateInfo
*pCreateInfo
,
1380 const VkAllocationCallbacks
*pAllocator
,
1383 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1384 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1385 struct anv_image_view
*iview
;
1387 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1388 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1390 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1392 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1394 assert(range
->layerCount
> 0);
1395 assert(range
->baseMipLevel
< image
->levels
);
1397 /* Check if a conversion info was passed. */
1398 const struct anv_format
*conv_format
= NULL
;
1399 const struct VkSamplerYcbcrConversionInfo
*conv_info
=
1400 vk_find_struct_const(pCreateInfo
->pNext
, SAMPLER_YCBCR_CONVERSION_INFO
);
1402 /* If image has an external format, the pNext chain must contain an instance of
1403 * VKSamplerYcbcrConversionInfo with a conversion object created with the same
1404 * external format as image."
1406 assert(!image
->external_format
|| conv_info
);
1409 ANV_FROM_HANDLE(anv_ycbcr_conversion
, conversion
, conv_info
->conversion
);
1410 conv_format
= conversion
->format
;
1413 const VkImageViewUsageCreateInfo
*usage_info
=
1414 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO
);
1415 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1416 /* View usage should be a subset of image usage */
1417 assert((view_usage
& ~image
->usage
) == 0);
1418 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1419 VK_IMAGE_USAGE_STORAGE_BIT
|
1420 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1421 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1422 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1424 switch (image
->type
) {
1426 unreachable("bad VkImageType");
1427 case VK_IMAGE_TYPE_1D
:
1428 case VK_IMAGE_TYPE_2D
:
1429 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1431 case VK_IMAGE_TYPE_3D
:
1432 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1433 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1437 /* First expand aspects to the image's ones (for example
1438 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1439 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1440 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1441 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.
1443 VkImageAspectFlags expanded_aspects
=
1444 anv_image_expand_aspects(image
, range
->aspectMask
);
1446 iview
->image
= image
;
1448 /* Remap the expanded aspects for the image view. For example if only
1449 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1450 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1451 * the image view, it only has a single plane.
1453 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1454 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1455 iview
->vk_format
= pCreateInfo
->format
;
1457 /* "If image has an external format, format must be VK_FORMAT_UNDEFINED." */
1458 assert(!image
->external_format
|| pCreateInfo
->format
== VK_FORMAT_UNDEFINED
);
1460 /* Format is undefined, this can happen when using external formats. Set
1461 * view format from the passed conversion info.
1463 if (iview
->vk_format
== VK_FORMAT_UNDEFINED
&& conv_format
)
1464 iview
->vk_format
= conv_format
->vk_format
;
1466 iview
->extent
= (VkExtent3D
) {
1467 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1468 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1469 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1472 /* Now go through the underlying image selected planes (computed in
1473 * expanded_aspects) and map them to planes in the image view.
1475 uint32_t iaspect_bit
, vplane
= 0;
1476 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1478 anv_image_aspect_to_plane(image
->aspects
, 1UL << iaspect_bit
);
1479 VkImageAspectFlags vplane_aspect
=
1480 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1481 struct anv_format_plane format
=
1482 anv_get_format_plane(&device
->info
, iview
->vk_format
,
1483 vplane_aspect
, image
->tiling
);
1485 iview
->planes
[vplane
].image_plane
= iplane
;
1487 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1488 .format
= format
.isl_format
,
1489 .base_level
= range
->baseMipLevel
,
1490 .levels
= anv_get_levelCount(image
, range
),
1491 .base_array_layer
= range
->baseArrayLayer
,
1492 .array_len
= anv_get_layerCount(image
, range
),
1494 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1495 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1496 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1497 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1498 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1499 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1500 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1501 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1505 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1506 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1507 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1510 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1511 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1512 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1514 iview
->planes
[vplane
].isl
.usage
= 0;
1517 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1518 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1519 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1520 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1521 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1523 enum isl_aux_usage general_aux_usage
=
1524 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1525 VK_IMAGE_LAYOUT_GENERAL
);
1526 enum isl_aux_usage optimal_aux_usage
=
1527 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1528 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1530 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1531 &iview
->planes
[vplane
].isl
,
1532 ISL_SURF_USAGE_TEXTURE_BIT
,
1533 optimal_aux_usage
, NULL
,
1534 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1535 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1538 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1539 &iview
->planes
[vplane
].isl
,
1540 ISL_SURF_USAGE_TEXTURE_BIT
,
1541 general_aux_usage
, NULL
,
1543 &iview
->planes
[vplane
].general_sampler_surface_state
,
1547 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1548 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1549 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1550 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1552 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1553 &iview
->planes
[vplane
].isl
,
1554 ISL_SURF_USAGE_STORAGE_BIT
,
1555 ISL_AUX_USAGE_NONE
, NULL
,
1557 &iview
->planes
[vplane
].storage_surface_state
,
1558 &iview
->planes
[vplane
].storage_image_param
);
1560 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1561 &iview
->planes
[vplane
].isl
,
1562 ISL_SURF_USAGE_STORAGE_BIT
,
1563 ISL_AUX_USAGE_NONE
, NULL
,
1564 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1565 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1572 *pView
= anv_image_view_to_handle(iview
);
1578 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1579 const VkAllocationCallbacks
*pAllocator
)
1581 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1582 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1587 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1588 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1589 anv_state_pool_free(&device
->surface_state_pool
,
1590 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1593 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1594 anv_state_pool_free(&device
->surface_state_pool
,
1595 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1598 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1599 anv_state_pool_free(&device
->surface_state_pool
,
1600 iview
->planes
[plane
].storage_surface_state
.state
);
1603 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1604 anv_state_pool_free(&device
->surface_state_pool
,
1605 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1609 vk_free2(&device
->alloc
, pAllocator
, iview
);
1614 anv_CreateBufferView(VkDevice _device
,
1615 const VkBufferViewCreateInfo
*pCreateInfo
,
1616 const VkAllocationCallbacks
*pAllocator
,
1617 VkBufferView
*pView
)
1619 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1620 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1621 struct anv_buffer_view
*view
;
1623 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1624 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1626 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1628 /* TODO: Handle the format swizzle? */
1630 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1631 VK_IMAGE_ASPECT_COLOR_BIT
,
1632 VK_IMAGE_TILING_LINEAR
);
1633 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1634 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1635 pCreateInfo
->range
);
1636 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1638 view
->address
= anv_address_add(buffer
->address
, pCreateInfo
->offset
);
1640 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1641 view
->surface_state
= alloc_surface_state(device
);
1643 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1645 view
->address
, view
->range
, format_bs
);
1647 view
->surface_state
= (struct anv_state
){ 0 };
1650 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1651 view
->storage_surface_state
= alloc_surface_state(device
);
1652 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1654 enum isl_format storage_format
=
1655 isl_has_matching_typed_storage_image_format(&device
->info
,
1657 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1660 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1662 view
->address
, view
->range
,
1663 (storage_format
== ISL_FORMAT_RAW
? 1 :
1664 isl_format_get_layout(storage_format
)->bpb
/ 8));
1666 /* Write-only accesses should use the original format. */
1667 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1669 view
->address
, view
->range
,
1670 isl_format_get_layout(view
->format
)->bpb
/ 8);
1672 isl_buffer_fill_image_param(&device
->isl_dev
,
1673 &view
->storage_image_param
,
1674 view
->format
, view
->range
);
1676 view
->storage_surface_state
= (struct anv_state
){ 0 };
1677 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1680 *pView
= anv_buffer_view_to_handle(view
);
1686 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1687 const VkAllocationCallbacks
*pAllocator
)
1689 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1690 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1695 if (view
->surface_state
.alloc_size
> 0)
1696 anv_state_pool_free(&device
->surface_state_pool
,
1697 view
->surface_state
);
1699 if (view
->storage_surface_state
.alloc_size
> 0)
1700 anv_state_pool_free(&device
->surface_state_pool
,
1701 view
->storage_surface_state
);
1703 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1704 anv_state_pool_free(&device
->surface_state_pool
,
1705 view
->writeonly_storage_surface_state
);
1707 vk_free2(&device
->alloc
, pAllocator
, view
);
1710 const struct anv_surface
*
1711 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1712 VkImageAspectFlags aspect_mask
)
1714 VkImageAspectFlags sanitized_mask
;
1716 switch (aspect_mask
) {
1717 case VK_IMAGE_ASPECT_COLOR_BIT
:
1718 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1719 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1721 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1722 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1723 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1725 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1726 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1727 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1729 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1730 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1731 * combined depth stencil formats. Specifically, it states:
1733 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1734 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1736 * Image views with both depth and stencil aspects are only valid for
1737 * render target attachments, in which case
1738 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1739 * stencil surfaces from the underlying surface.
1741 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1742 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1744 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1745 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1748 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1749 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1750 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT
;
1752 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1753 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1754 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT
;
1756 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1757 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1758 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT
;
1761 unreachable("image does not have aspect");
1765 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1766 return &image
->planes
[plane
].surface
;