2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include "anv_private.h"
32 #include "util/debug.h"
35 #include "vk_format_info.h"
37 static isl_surf_usage_flags_t
38 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
39 VkImageUsageFlags vk_usage
,
40 isl_surf_usage_flags_t isl_extra_usage
,
41 VkImageAspectFlagBits aspect
)
43 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
45 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
46 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
48 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
49 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
51 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
52 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
54 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
55 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
57 /* Even if we're only using it for transfer operations, clears to depth and
58 * stencil images happen as depth and stencil so they need the right ISL
59 * usage bits or else things will fall apart.
62 case VK_IMAGE_ASPECT_DEPTH_BIT
:
63 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
65 case VK_IMAGE_ASPECT_STENCIL_BIT
:
66 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
68 case VK_IMAGE_ASPECT_COLOR_BIT
:
69 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
70 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
74 unreachable("bad VkImageAspect");
77 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
78 /* blorp implements transfers by sampling from the source image. */
79 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
82 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
83 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
84 /* blorp implements transfers by rendering into the destination image.
85 * Only request this with color images, as we deal with depth/stencil
86 * formats differently. */
87 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
93 static isl_tiling_flags_t
94 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
)
96 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
97 isl_tiling_flags_t flags
= 0;
99 switch (base_info
->tiling
) {
101 unreachable("bad VkImageTiling");
102 case VK_IMAGE_TILING_OPTIMAL
:
103 flags
= ISL_TILING_ANY_MASK
;
105 case VK_IMAGE_TILING_LINEAR
:
106 flags
= ISL_TILING_LINEAR_BIT
;
110 if (anv_info
->isl_tiling_flags
)
111 flags
&= anv_info
->isl_tiling_flags
;
118 static struct anv_surface
*
119 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
121 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
122 return &image
->planes
[plane
].surface
;
126 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
128 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
130 if (image
->disjoint
) {
131 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
132 /* Plane offset is always 0 when it's disjoint. */
134 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
135 /* Determine plane's offset only once when the first surface is added. */
136 if (image
->planes
[plane
].size
== 0)
137 image
->planes
[plane
].offset
= image
->size
;
140 image
->size
= surf
->offset
+ surf
->isl
.size
;
141 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
143 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
144 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
145 surf
->isl
.alignment
);
150 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
151 const struct VkImageCreateInfo
*vk_info
)
153 enum isl_format format
=
154 anv_get_isl_format(devinfo
, vk_info
->format
,
155 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
157 if (!isl_format_supports_ccs_e(devinfo
, format
))
160 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
163 const VkImageFormatListCreateInfoKHR
*fmt_list
=
164 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
166 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
169 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
170 enum isl_format view_format
=
171 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
172 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
174 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
182 * For color images that have an auxiliary surface, request allocation for an
183 * additional buffer that mainly stores fast-clear values. Use of this buffer
184 * allows us to access the image's subresources while being aware of their
185 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
186 * which a fast clear has occurred).
188 * For the purpose of discoverability, the algorithm used to manage this buffer
189 * is described here. A clear value in this buffer is updated when a fast clear
190 * is performed on a subresource. One of two synchronization operations is
191 * performed in order for a following memory access to use the fast-clear
193 * a. Copy the value from the buffer to the surface state object used for
194 * reading. This is done implicitly when the value is the clear value
195 * predetermined to be the default in other surface state objects. This
196 * is currently only done explicitly for the operation below.
197 * b. Do (a) and use the surface state object to resolve the subresource.
198 * This is only done during layout transitions for decent performance.
200 * With the above scheme, we can fast-clear whenever the hardware allows except
201 * for two cases in which synchronization becomes impossible or undesirable:
202 * * The subresource is in the GENERAL layout and is cleared to a value
203 * other than the special default value.
205 * Performing a synchronization operation in order to read from the
206 * subresource is undesirable in this case. Firstly, b) is not an option
207 * because a layout transition isn't required between a write and read of
208 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
209 * explicitly because it would require large infrastructural changes. The
210 * Vulkan API supports us in deciding not to optimize this layout by
211 * stating that using this layout may cause suboptimal performance. NOTE:
212 * the auxiliary buffer must always be enabled to support a) implicitly.
215 * * For the given miplevel, only some of the layers are cleared at once.
217 * If the user clears each layer to a different value, then tries to
218 * render to multiple layers at once, we have no ability to perform a
219 * synchronization operation in between. a) is not helpful because the
220 * object can only hold one clear value. b) is not an option because a
221 * layout transition isn't required in this case.
224 add_fast_clear_state_buffer(struct anv_image
*image
,
225 VkImageAspectFlagBits aspect
,
227 const struct anv_device
*device
)
229 assert(image
&& device
);
230 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
231 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
233 /* The offset to the buffer of clear values must be dword-aligned for GPU
234 * memcpy operations. It is located immediately after the auxiliary surface.
237 /* Tiled images are guaranteed to be 4K aligned, so the image alignment
238 * should also be dword-aligned.
240 assert(image
->alignment
% 4 == 0);
242 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
243 * values buffer should already be dword-aligned.
245 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
247 /* This buffer should be at the very end of the plane. */
248 if (image
->disjoint
) {
249 assert(image
->planes
[plane
].size
==
250 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
252 assert(image
->size
==
253 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
256 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
257 /* There's no padding between entries, so ensure that they're always a
258 * multiple of 32 bits in order to enable GPU memcpy operations.
260 assert(entry_size
% 4 == 0);
262 const unsigned plane_state_size
=
263 entry_size
* anv_image_aux_levels(image
, aspect
);
265 image
->planes
[plane
].fast_clear_state_offset
=
266 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
268 image
->planes
[plane
].size
+= plane_state_size
;
269 image
->size
+= plane_state_size
;
273 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
274 * image's memory requirements (that is, the image's size and alignment).
277 make_surface(const struct anv_device
*dev
,
278 struct anv_image
*image
,
279 const struct anv_image_create_info
*anv_info
,
280 isl_tiling_flags_t tiling_flags
,
281 VkImageAspectFlagBits aspect
)
283 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
286 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
287 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
288 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
289 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
292 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
295 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
296 const struct anv_format_plane plane_format
=
297 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
298 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
300 const isl_surf_usage_flags_t usage
=
301 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
302 anv_info
->isl_extra_usage_flags
, aspect
);
304 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
305 * fall back to linear on Broadwell and earlier because we aren't
306 * guaranteed that we can handle offsets correctly. On Sky Lake, the
307 * horizontal and vertical alignments are sufficiently high that we can
308 * just use RENDER_SURFACE_STATE::X/Y Offset.
310 bool needs_shadow
= false;
311 if (dev
->info
.gen
<= 8 &&
312 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
313 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
314 assert(isl_format_is_compressed(plane_format
.isl_format
));
315 tiling_flags
= ISL_TILING_LINEAR_BIT
;
319 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
320 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
321 .format
= plane_format
.isl_format
,
322 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
323 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
324 .depth
= image
->extent
.depth
,
325 .levels
= vk_info
->mipLevels
,
326 .array_len
= vk_info
->arrayLayers
,
327 .samples
= vk_info
->samples
,
329 .row_pitch
= anv_info
->stride
,
331 .tiling_flags
= tiling_flags
);
333 /* isl_surf_init() will fail only if provided invalid input. Invalid input
334 * is illegal in Vulkan.
338 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
340 add_surface(image
, anv_surf
, plane
);
342 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
343 * create an identical tiled shadow surface for use while texturing so we
344 * don't get garbage performance.
347 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
348 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
350 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
351 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
352 .format
= plane_format
.isl_format
,
353 .width
= image
->extent
.width
,
354 .height
= image
->extent
.height
,
355 .depth
= image
->extent
.depth
,
356 .levels
= vk_info
->mipLevels
,
357 .array_len
= vk_info
->arrayLayers
,
358 .samples
= vk_info
->samples
,
360 .row_pitch
= anv_info
->stride
,
362 .tiling_flags
= ISL_TILING_ANY_MASK
);
364 /* isl_surf_init() will fail only if provided invalid input. Invalid input
365 * is illegal in Vulkan.
369 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
372 /* Add a HiZ surface to a depth buffer that will be used for rendering.
374 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
375 /* We don't advertise that depth buffers could be used as storage
378 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
380 /* Allow the user to control HiZ enabling. Disable by default on gen7
381 * because resolves are not currently implemented pre-BDW.
383 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
384 /* It will never be used as an attachment, HiZ is pointless. */
385 } else if (dev
->info
.gen
== 7) {
386 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
387 } else if (vk_info
->mipLevels
> 1) {
388 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
389 } else if (vk_info
->arrayLayers
> 1) {
390 anv_perf_warn(dev
->instance
, image
,
391 "Implement multi-arrayLayer HiZ clears and resolves");
392 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
393 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
394 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
395 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
396 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
397 &image
->planes
[plane
].surface
.isl
,
398 &image
->planes
[plane
].aux_surface
.isl
);
400 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
401 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
403 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
404 /* TODO: Disallow compression with :
406 * 1) non multiplanar images (We appear to hit a sampler bug with
407 * CCS & R16G16 format. Putting the clear state a page/4096bytes
408 * further fixes the issue).
410 * 2) alias images, because they might be aliases of images
413 * 3) compression disabled by debug
415 const bool allow_compression
=
416 image
->n_planes
== 1 &&
417 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
418 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
420 if (allow_compression
) {
421 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
422 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
423 &image
->planes
[plane
].surface
.isl
,
424 &image
->planes
[plane
].aux_surface
.isl
, 0);
427 /* Disable CCS when it is not useful (i.e., when you can't render
428 * to the image with CCS enabled).
430 if (!isl_format_supports_rendering(&dev
->info
,
431 plane_format
.isl_format
)) {
432 /* While it may be technically possible to enable CCS for this
433 * image, we currently don't have things hooked up to get it
436 anv_perf_warn(dev
->instance
, image
,
437 "This image format doesn't support rendering. "
438 "Not allocating an CCS buffer.");
439 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
443 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
444 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
446 /* For images created without MUTABLE_FORMAT_BIT set, we know that
447 * they will always be used with the original format. In
448 * particular, they will always be used with a format that
449 * supports color compression. If it's never used as a storage
450 * image, then it will only be used through the sampler or the as
451 * a render target. This means that it's safe to just leave
452 * compression on at all times for these formats.
454 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
455 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
456 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
460 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
461 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
462 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
463 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
464 &image
->planes
[plane
].surface
.isl
,
465 &image
->planes
[plane
].aux_surface
.isl
);
467 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
468 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
469 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
473 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
475 /* Upper bound of the last surface should be smaller than the plane's
478 assert((MAX2(image
->planes
[plane
].surface
.offset
,
479 image
->planes
[plane
].aux_surface
.offset
) +
480 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
481 image
->planes
[plane
].aux_surface
.isl
.size
:
482 image
->planes
[plane
].surface
.isl
.size
)) <=
483 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
485 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
486 /* assert(image->planes[plane].fast_clear_state_offset == */
487 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
488 assert(image
->planes
[plane
].fast_clear_state_offset
<
489 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
496 anv_image_create(VkDevice _device
,
497 const struct anv_image_create_info
*create_info
,
498 const VkAllocationCallbacks
* alloc
,
501 ANV_FROM_HANDLE(anv_device
, device
, _device
);
502 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
503 struct anv_image
*image
= NULL
;
506 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
508 anv_assert(pCreateInfo
->mipLevels
> 0);
509 anv_assert(pCreateInfo
->arrayLayers
> 0);
510 anv_assert(pCreateInfo
->samples
> 0);
511 anv_assert(pCreateInfo
->extent
.width
> 0);
512 anv_assert(pCreateInfo
->extent
.height
> 0);
513 anv_assert(pCreateInfo
->extent
.depth
> 0);
515 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
516 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
518 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
520 image
->type
= pCreateInfo
->imageType
;
521 image
->extent
= pCreateInfo
->extent
;
522 image
->vk_format
= pCreateInfo
->format
;
523 image
->format
= anv_get_format(pCreateInfo
->format
);
524 image
->aspects
= vk_format_aspects(image
->vk_format
);
525 image
->levels
= pCreateInfo
->mipLevels
;
526 image
->array_size
= pCreateInfo
->arrayLayers
;
527 image
->samples
= pCreateInfo
->samples
;
528 image
->usage
= pCreateInfo
->usage
;
529 image
->tiling
= pCreateInfo
->tiling
;
530 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
532 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
533 assert(format
!= NULL
);
535 const isl_tiling_flags_t isl_tiling_flags
=
536 choose_isl_tiling_flags(create_info
);
538 image
->n_planes
= format
->n_planes
;
541 for_each_bit(b
, image
->aspects
) {
542 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
548 *pImage
= anv_image_to_handle(image
);
554 vk_free2(&device
->alloc
, alloc
, image
);
560 anv_CreateImage(VkDevice device
,
561 const VkImageCreateInfo
*pCreateInfo
,
562 const VkAllocationCallbacks
*pAllocator
,
566 const VkNativeBufferANDROID
*gralloc_info
=
567 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
570 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
574 return anv_image_create(device
,
575 &(struct anv_image_create_info
) {
576 .vk_info
= pCreateInfo
,
583 anv_DestroyImage(VkDevice _device
, VkImage _image
,
584 const VkAllocationCallbacks
*pAllocator
)
586 ANV_FROM_HANDLE(anv_device
, device
, _device
);
587 ANV_FROM_HANDLE(anv_image
, image
, _image
);
592 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
593 if (image
->planes
[p
].bo_is_owned
) {
594 assert(image
->planes
[p
].bo
!= NULL
);
595 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
599 vk_free2(&device
->alloc
, pAllocator
, image
);
602 static void anv_image_bind_memory_plane(struct anv_device
*device
,
603 struct anv_image
*image
,
605 struct anv_device_memory
*memory
,
606 uint32_t memory_offset
)
608 assert(!image
->planes
[plane
].bo_is_owned
);
611 image
->planes
[plane
].bo
= NULL
;
612 image
->planes
[plane
].bo_offset
= 0;
616 image
->planes
[plane
].bo
= memory
->bo
;
617 image
->planes
[plane
].bo_offset
= memory_offset
;
620 VkResult
anv_BindImageMemory(
623 VkDeviceMemory _memory
,
624 VkDeviceSize memoryOffset
)
626 ANV_FROM_HANDLE(anv_device
, device
, _device
);
627 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
628 ANV_FROM_HANDLE(anv_image
, image
, _image
);
631 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
633 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
634 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
640 VkResult
anv_BindImageMemory2KHR(
642 uint32_t bindInfoCount
,
643 const VkBindImageMemoryInfoKHR
* pBindInfos
)
645 ANV_FROM_HANDLE(anv_device
, device
, _device
);
647 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
648 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
649 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
650 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
651 VkImageAspectFlags aspects
= image
->aspects
;
653 vk_foreach_struct_const(s
, bind_info
->pNext
) {
655 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
656 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
657 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
659 aspects
= plane_info
->planeAspect
;
663 anv_debug_ignored_stype(s
->sType
);
669 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
671 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
672 anv_image_bind_memory_plane(device
, image
, plane
,
673 mem
, bind_info
->memoryOffset
);
681 anv_surface_get_subresource_layout(struct anv_image
*image
,
682 struct anv_surface
*surface
,
683 const VkImageSubresource
*subresource
,
684 VkSubresourceLayout
*layout
)
686 /* If we are on a non-zero mip level or array slice, we need to
687 * calculate a real offset.
689 anv_assert(subresource
->mipLevel
== 0);
690 anv_assert(subresource
->arrayLayer
== 0);
692 layout
->offset
= surface
->offset
;
693 layout
->rowPitch
= surface
->isl
.row_pitch
;
694 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
695 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
696 layout
->size
= surface
->isl
.size
;
699 void anv_GetImageSubresourceLayout(
702 const VkImageSubresource
* pSubresource
,
703 VkSubresourceLayout
* pLayout
)
705 ANV_FROM_HANDLE(anv_image
, image
, _image
);
707 assert(__builtin_popcount(pSubresource
->aspectMask
) == 1);
709 anv_surface_get_subresource_layout(image
,
711 pSubresource
->aspectMask
),
712 pSubresource
, pLayout
);
716 * This function determines the optimal buffer to use for a given
717 * VkImageLayout and other pieces of information needed to make that
718 * determination. This does not determine the optimal buffer to use
719 * during a resolve operation.
721 * @param devinfo The device information of the Intel GPU.
722 * @param image The image that may contain a collection of buffers.
723 * @param plane The plane of the image to be accessed.
724 * @param layout The current layout of the image aspect(s).
726 * @return The primary buffer that should be used for the given layout.
729 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
730 const struct anv_image
* const image
,
731 const VkImageAspectFlagBits aspect
,
732 const VkImageLayout layout
)
734 /* Validate the inputs. */
736 /* The devinfo is needed as the optimal buffer varies across generations. */
737 assert(devinfo
!= NULL
);
739 /* The layout of a NULL image is not properly defined. */
740 assert(image
!= NULL
);
742 /* The aspect must be exactly one of the image aspects. */
743 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
745 /* Determine the optimal buffer. */
747 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
749 /* If there is no auxiliary surface allocated, we must use the one and only
752 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
753 return ISL_AUX_USAGE_NONE
;
755 /* All images that use an auxiliary surface are required to be tiled. */
756 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
758 /* Stencil has no aux */
759 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
761 /* The following switch currently only handles depth stencil aspects.
762 * TODO: Handle the color aspect.
764 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
)
765 return image
->planes
[plane
].aux_usage
;
769 /* Invalid Layouts */
770 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
771 case VK_IMAGE_LAYOUT_MAX_ENUM
:
772 unreachable("Invalid image layout.");
776 * The pre-initialized layout is equivalent to the undefined layout for
777 * optimally-tiled images. We can only do color compression (CCS or HiZ)
780 case VK_IMAGE_LAYOUT_UNDEFINED
:
781 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
782 return ISL_AUX_USAGE_NONE
;
787 * This buffer could be a depth buffer used in a transfer operation. BLORP
788 * currently doesn't use HiZ for transfer operations so we must use the main
789 * buffer for this layout. TODO: Enable HiZ in BLORP.
791 case VK_IMAGE_LAYOUT_GENERAL
:
792 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
793 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
794 return ISL_AUX_USAGE_NONE
;
797 /* Sampling Layouts */
798 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
799 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
801 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
802 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
803 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
804 if (anv_can_sample_with_hiz(devinfo
, image
))
805 return ISL_AUX_USAGE_HIZ
;
807 return ISL_AUX_USAGE_NONE
;
809 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
810 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
812 /* On SKL+, the render buffer can be decompressed by the presentation
813 * engine. Support for this feature has not yet landed in the wider
814 * ecosystem. TODO: Update this code when support lands.
816 * From the BDW PRM, Vol 7, Render Target Resolve:
818 * If the MCS is enabled on a non-multisampled render target, the
819 * render target must be resolved before being used for other
820 * purposes (display, texture, CPU lock) The clear value from
821 * SURFACE_STATE is written into pixels in the render target
822 * indicated as clear in the MCS.
824 * Pre-SKL, the render buffer must be resolved before being used for
825 * presentation. We can infer that the auxiliary buffer is not used.
827 return ISL_AUX_USAGE_NONE
;
830 /* Rendering Layouts */
831 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
832 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
833 unreachable("Color images are not yet supported.");
835 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
836 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
837 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
838 return ISL_AUX_USAGE_HIZ
;
840 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
841 unreachable("VK_KHR_shared_presentable_image is unsupported");
844 /* If the layout isn't recognized in the exhaustive switch above, the
845 * VkImageLayout value is not defined in vulkan.h.
847 unreachable("layout is not a VkImageLayout enumeration member.");
851 static struct anv_state
852 alloc_surface_state(struct anv_device
*device
)
854 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
857 static enum isl_channel_select
858 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
859 struct isl_swizzle format_swizzle
)
861 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
865 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
866 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
867 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
868 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
869 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
870 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
872 unreachable("Invalid swizzle");
877 anv_image_fill_surface_state(struct anv_device
*device
,
878 const struct anv_image
*image
,
879 VkImageAspectFlagBits aspect
,
880 const struct isl_view
*view_in
,
881 isl_surf_usage_flags_t view_usage
,
882 enum isl_aux_usage aux_usage
,
883 const union isl_color_value
*clear_color
,
884 enum anv_image_view_state_flags flags
,
885 struct anv_surface_state
*state_inout
,
886 struct brw_image_param
*image_param_out
)
888 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
890 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
891 *aux_surface
= &image
->planes
[plane
].aux_surface
;
893 struct isl_view view
= *view_in
;
894 view
.usage
|= view_usage
;
896 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
897 * compressed surface with a shadow surface, we use the shadow instead of
898 * the primary surface. The shadow surface will be tiled, unlike the main
899 * surface, so it should get significantly better performance.
901 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
902 isl_format_is_compressed(view
.format
) &&
903 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
904 assert(isl_format_is_compressed(surface
->isl
.format
));
905 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
906 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
907 surface
= &image
->planes
[plane
].shadow_surface
;
910 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
911 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
913 /* If this is a HiZ buffer we can sample from with a programmable clear
914 * value (SKL+), define the clear value to the optimal constant.
916 union isl_color_value default_clear_color
= { .u32
= { 0, } };
917 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
918 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
920 clear_color
= &default_clear_color
;
922 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
923 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
924 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
926 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
927 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
928 !isl_has_matching_typed_storage_image_format(&device
->info
,
930 /* In this case, we are a writeable storage buffer which needs to be
931 * lowered to linear. All tiling and offset calculations will be done in
934 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
935 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
937 .size
= surface
->isl
.size
,
938 .format
= ISL_FORMAT_RAW
,
940 .mocs
= device
->default_mocs
);
941 state_inout
->address
= address
,
942 state_inout
->aux_address
= 0;
944 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
945 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
946 /* Typed surface reads support a very limited subset of the shader
947 * image formats. Translate it into the closest format the hardware
950 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
951 view
.format
= isl_lower_storage_image_format(&device
->info
,
955 const struct isl_surf
*isl_surf
= &surface
->isl
;
957 struct isl_surf tmp_surf
;
958 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
959 if (isl_format_is_compressed(surface
->isl
.format
) &&
960 !isl_format_is_compressed(view
.format
)) {
961 /* We're creating an uncompressed view of a compressed surface. This
962 * is allowed but only for a single level/layer.
964 assert(surface
->isl
.samples
== 1);
965 assert(view
.levels
== 1);
966 assert(view
.array_len
== 1);
968 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
970 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
971 0 : view
.base_array_layer
,
972 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
973 view
.base_array_layer
: 0,
975 &offset_B
, &tile_x_sa
, &tile_y_sa
);
977 /* The newly created image represents the one subimage we're
978 * referencing with this view so it only has one array slice and
981 view
.base_array_layer
= 0;
984 /* We're making an uncompressed view here. The image dimensions need
985 * to be scaled down by the block size.
987 const struct isl_format_layout
*fmtl
=
988 isl_format_get_layout(surface
->isl
.format
);
989 tmp_surf
.format
= view
.format
;
990 tmp_surf
.logical_level0_px
.width
=
991 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
992 tmp_surf
.logical_level0_px
.height
=
993 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
994 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
995 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
996 tile_x_sa
/= fmtl
->bw
;
997 tile_y_sa
/= fmtl
->bh
;
999 isl_surf
= &tmp_surf
;
1001 if (device
->info
.gen
<= 8) {
1002 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1003 assert(tile_x_sa
== 0);
1004 assert(tile_y_sa
== 0);
1008 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1011 .address
= address
+ offset_B
,
1012 .clear_color
= *clear_color
,
1013 .aux_surf
= &aux_surface
->isl
,
1014 .aux_usage
= aux_usage
,
1015 .aux_address
= aux_address
,
1016 .mocs
= device
->default_mocs
,
1017 .x_offset_sa
= tile_x_sa
,
1018 .y_offset_sa
= tile_y_sa
);
1019 state_inout
->address
= address
+ offset_B
;
1020 if (device
->info
.gen
>= 8) {
1021 state_inout
->aux_address
= aux_address
;
1023 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1024 * used to store other information. This should be ok, however,
1025 * because surface buffer addresses are always 4K page alinged.
1027 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1028 device
->isl_dev
.ss
.aux_addr_offset
;
1029 assert((aux_address
& 0xfff) == 0);
1030 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1031 state_inout
->aux_address
= *aux_addr_dw
;
1035 anv_state_flush(device
, state_inout
->state
);
1037 if (image_param_out
) {
1038 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1039 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1040 &surface
->isl
, &view
);
1044 static VkImageAspectFlags
1045 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1047 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1048 if (_mesa_bitcount(view_aspects
) == 1)
1049 return VK_IMAGE_ASPECT_COLOR_BIT
;
1051 VkImageAspectFlags color_aspects
= 0;
1052 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1053 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1054 return color_aspects
;
1056 /* No special remapping needed for depth & stencil aspects. */
1057 return view_aspects
;
1061 anv_CreateImageView(VkDevice _device
,
1062 const VkImageViewCreateInfo
*pCreateInfo
,
1063 const VkAllocationCallbacks
*pAllocator
,
1066 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1067 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1068 struct anv_image_view
*iview
;
1070 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1071 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1073 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1075 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1077 assert(range
->layerCount
> 0);
1078 assert(range
->baseMipLevel
< image
->levels
);
1080 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1081 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1082 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1083 /* View usage should be a subset of image usage */
1084 assert((view_usage
& ~image
->usage
) == 0);
1085 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1086 VK_IMAGE_USAGE_STORAGE_BIT
|
1087 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1088 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1089 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1091 switch (image
->type
) {
1093 unreachable("bad VkImageType");
1094 case VK_IMAGE_TYPE_1D
:
1095 case VK_IMAGE_TYPE_2D
:
1096 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1098 case VK_IMAGE_TYPE_3D
:
1099 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1100 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1104 /* First expand aspects to the image's ones (for example
1105 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1106 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1107 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1108 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1110 VkImageAspectFlags expanded_aspects
=
1111 anv_image_expand_aspects(image
, range
->aspectMask
);
1113 iview
->image
= image
;
1115 /* Remap the expanded aspects for the image view. For example if only
1116 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1117 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1118 * the image view, it only has a single plane.
1120 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1121 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1122 iview
->vk_format
= pCreateInfo
->format
;
1124 iview
->extent
= (VkExtent3D
) {
1125 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1126 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1127 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1130 /* Now go through the underlying image selected planes (computed in
1131 * expanded_aspects) and map them to planes in the image view.
1133 uint32_t iaspect_bit
, vplane
= 0;
1134 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1136 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1137 VkImageAspectFlags vplane_aspect
=
1138 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1139 struct anv_format_plane format
=
1140 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1141 vplane_aspect
, image
->tiling
);
1143 iview
->planes
[vplane
].image_plane
= iplane
;
1145 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1146 .format
= format
.isl_format
,
1147 .base_level
= range
->baseMipLevel
,
1148 .levels
= anv_get_levelCount(image
, range
),
1149 .base_array_layer
= range
->baseArrayLayer
,
1150 .array_len
= anv_get_layerCount(image
, range
),
1152 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1153 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1154 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1155 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1156 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1157 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1158 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1159 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1163 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1164 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1165 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1168 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1169 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1170 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1172 iview
->planes
[vplane
].isl
.usage
= 0;
1175 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1176 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1177 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1178 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1179 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1181 enum isl_aux_usage general_aux_usage
=
1182 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1183 VK_IMAGE_LAYOUT_GENERAL
);
1184 enum isl_aux_usage optimal_aux_usage
=
1185 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1186 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1188 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1189 &iview
->planes
[vplane
].isl
,
1190 ISL_SURF_USAGE_TEXTURE_BIT
,
1191 optimal_aux_usage
, NULL
,
1192 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1193 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1196 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1197 &iview
->planes
[vplane
].isl
,
1198 ISL_SURF_USAGE_TEXTURE_BIT
,
1199 general_aux_usage
, NULL
,
1201 &iview
->planes
[vplane
].general_sampler_surface_state
,
1205 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1206 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1207 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1208 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1210 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1211 &iview
->planes
[vplane
].isl
,
1212 ISL_SURF_USAGE_STORAGE_BIT
,
1213 ISL_AUX_USAGE_NONE
, NULL
,
1215 &iview
->planes
[vplane
].storage_surface_state
,
1216 &iview
->planes
[vplane
].storage_image_param
);
1218 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1219 &iview
->planes
[vplane
].isl
,
1220 ISL_SURF_USAGE_STORAGE_BIT
,
1221 ISL_AUX_USAGE_NONE
, NULL
,
1222 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1223 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1230 *pView
= anv_image_view_to_handle(iview
);
1236 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1237 const VkAllocationCallbacks
*pAllocator
)
1239 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1240 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1245 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1246 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1247 anv_state_pool_free(&device
->surface_state_pool
,
1248 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1251 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1252 anv_state_pool_free(&device
->surface_state_pool
,
1253 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1256 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1257 anv_state_pool_free(&device
->surface_state_pool
,
1258 iview
->planes
[plane
].storage_surface_state
.state
);
1261 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1262 anv_state_pool_free(&device
->surface_state_pool
,
1263 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1267 vk_free2(&device
->alloc
, pAllocator
, iview
);
1272 anv_CreateBufferView(VkDevice _device
,
1273 const VkBufferViewCreateInfo
*pCreateInfo
,
1274 const VkAllocationCallbacks
*pAllocator
,
1275 VkBufferView
*pView
)
1277 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1278 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1279 struct anv_buffer_view
*view
;
1281 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1282 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1284 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1286 /* TODO: Handle the format swizzle? */
1288 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1289 VK_IMAGE_ASPECT_COLOR_BIT
,
1290 VK_IMAGE_TILING_LINEAR
);
1291 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1292 view
->bo
= buffer
->bo
;
1293 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1294 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1295 pCreateInfo
->range
);
1296 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1298 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1299 view
->surface_state
= alloc_surface_state(device
);
1301 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1303 view
->offset
, view
->range
, format_bs
);
1305 view
->surface_state
= (struct anv_state
){ 0 };
1308 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1309 view
->storage_surface_state
= alloc_surface_state(device
);
1310 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1312 enum isl_format storage_format
=
1313 isl_has_matching_typed_storage_image_format(&device
->info
,
1315 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1318 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1320 view
->offset
, view
->range
,
1321 (storage_format
== ISL_FORMAT_RAW
? 1 :
1322 isl_format_get_layout(storage_format
)->bpb
/ 8));
1324 /* Write-only accesses should use the original format. */
1325 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1327 view
->offset
, view
->range
,
1328 isl_format_get_layout(view
->format
)->bpb
/ 8);
1330 isl_buffer_fill_image_param(&device
->isl_dev
,
1331 &view
->storage_image_param
,
1332 view
->format
, view
->range
);
1334 view
->storage_surface_state
= (struct anv_state
){ 0 };
1335 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1338 *pView
= anv_buffer_view_to_handle(view
);
1344 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1345 const VkAllocationCallbacks
*pAllocator
)
1347 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1348 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1353 if (view
->surface_state
.alloc_size
> 0)
1354 anv_state_pool_free(&device
->surface_state_pool
,
1355 view
->surface_state
);
1357 if (view
->storage_surface_state
.alloc_size
> 0)
1358 anv_state_pool_free(&device
->surface_state_pool
,
1359 view
->storage_surface_state
);
1361 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1362 anv_state_pool_free(&device
->surface_state_pool
,
1363 view
->writeonly_storage_surface_state
);
1365 vk_free2(&device
->alloc
, pAllocator
, view
);
1368 const struct anv_surface
*
1369 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1370 VkImageAspectFlags aspect_mask
)
1372 VkImageAspectFlags sanitized_mask
;
1374 switch (aspect_mask
) {
1375 case VK_IMAGE_ASPECT_COLOR_BIT
:
1376 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1377 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1379 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1380 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1381 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1383 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1384 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1385 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1387 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1388 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1389 * combined depth stencil formats. Specifically, it states:
1391 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1392 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1394 * Image views with both depth and stencil aspects are only valid for
1395 * render target attachments, in which case
1396 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1397 * stencil surfaces from the underlying surface.
1399 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1400 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1402 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1403 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1406 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1407 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1408 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1410 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1411 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1412 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1414 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1415 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1416 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1419 unreachable("image does not have aspect");
1423 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1424 return &image
->planes
[plane
].surface
;