2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
)
97 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
98 isl_tiling_flags_t flags
= 0;
100 switch (base_info
->tiling
) {
102 unreachable("bad VkImageTiling");
103 case VK_IMAGE_TILING_OPTIMAL
:
104 flags
= ISL_TILING_ANY_MASK
;
106 case VK_IMAGE_TILING_LINEAR
:
107 flags
= ISL_TILING_LINEAR_BIT
;
111 if (anv_info
->isl_tiling_flags
)
112 flags
&= anv_info
->isl_tiling_flags
;
119 static struct anv_surface
*
120 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
122 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
123 return &image
->planes
[plane
].surface
;
127 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
129 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
131 if (image
->disjoint
) {
132 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
133 /* Plane offset is always 0 when it's disjoint. */
135 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
136 /* Determine plane's offset only once when the first surface is added. */
137 if (image
->planes
[plane
].size
== 0)
138 image
->planes
[plane
].offset
= image
->size
;
141 image
->size
= surf
->offset
+ surf
->isl
.size
;
142 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
144 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
145 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
146 surf
->isl
.alignment
);
151 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
152 const struct VkImageCreateInfo
*vk_info
)
154 enum isl_format format
=
155 anv_get_isl_format(devinfo
, vk_info
->format
,
156 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
158 if (!isl_format_supports_ccs_e(devinfo
, format
))
161 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
164 const VkImageFormatListCreateInfoKHR
*fmt_list
=
165 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
167 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
170 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
171 enum isl_format view_format
=
172 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
173 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
175 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
183 * For color images that have an auxiliary surface, request allocation for an
184 * additional buffer that mainly stores fast-clear values. Use of this buffer
185 * allows us to access the image's subresources while being aware of their
186 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
187 * which a fast clear has occurred).
189 * For the purpose of discoverability, the algorithm used to manage this buffer
190 * is described here. A clear value in this buffer is updated when a fast clear
191 * is performed on a subresource. One of two synchronization operations is
192 * performed in order for a following memory access to use the fast-clear
194 * a. Copy the value from the buffer to the surface state object used for
195 * reading. This is done implicitly when the value is the clear value
196 * predetermined to be the default in other surface state objects. This
197 * is currently only done explicitly for the operation below.
198 * b. Do (a) and use the surface state object to resolve the subresource.
199 * This is only done during layout transitions for decent performance.
201 * With the above scheme, we can fast-clear whenever the hardware allows except
202 * for two cases in which synchronization becomes impossible or undesirable:
203 * * The subresource is in the GENERAL layout and is cleared to a value
204 * other than the special default value.
206 * Performing a synchronization operation in order to read from the
207 * subresource is undesirable in this case. Firstly, b) is not an option
208 * because a layout transition isn't required between a write and read of
209 * an image in the GENERAL layout. Secondly, it's undesirable to do a)
210 * explicitly because it would require large infrastructural changes. The
211 * Vulkan API supports us in deciding not to optimize this layout by
212 * stating that using this layout may cause suboptimal performance. NOTE:
213 * the auxiliary buffer must always be enabled to support a) implicitly.
216 * * For the given miplevel, only some of the layers are cleared at once.
218 * If the user clears each layer to a different value, then tries to
219 * render to multiple layers at once, we have no ability to perform a
220 * synchronization operation in between. a) is not helpful because the
221 * object can only hold one clear value. b) is not an option because a
222 * layout transition isn't required in this case.
225 add_fast_clear_state_buffer(struct anv_image
*image
,
226 VkImageAspectFlagBits aspect
,
228 const struct anv_device
*device
)
230 assert(image
&& device
);
231 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
232 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
234 /* The offset to the buffer of clear values must be dword-aligned for GPU
235 * memcpy operations. It is located immediately after the auxiliary surface.
238 /* Tiled images are guaranteed to be 4K aligned, so the image alignment
239 * should also be dword-aligned.
241 assert(image
->alignment
% 4 == 0);
243 /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
244 * values buffer should already be dword-aligned.
246 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
248 /* This buffer should be at the very end of the plane. */
249 if (image
->disjoint
) {
250 assert(image
->planes
[plane
].size
==
251 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
253 assert(image
->size
==
254 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
257 const unsigned entry_size
= anv_fast_clear_state_entry_size(device
);
258 /* There's no padding between entries, so ensure that they're always a
259 * multiple of 32 bits in order to enable GPU memcpy operations.
261 assert(entry_size
% 4 == 0);
263 const unsigned plane_state_size
=
264 entry_size
* anv_image_aux_levels(image
, aspect
);
266 image
->planes
[plane
].fast_clear_state_offset
=
267 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
269 image
->planes
[plane
].size
+= plane_state_size
;
270 image
->size
+= plane_state_size
;
274 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
275 * image's memory requirements (that is, the image's size and alignment).
278 make_surface(const struct anv_device
*dev
,
279 struct anv_image
*image
,
280 const struct anv_image_create_info
*anv_info
,
281 isl_tiling_flags_t tiling_flags
,
282 VkImageAspectFlagBits aspect
)
284 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
287 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
288 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
289 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
290 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
293 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
296 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
297 const struct anv_format_plane plane_format
=
298 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
299 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
301 const isl_surf_usage_flags_t usage
=
302 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
303 anv_info
->isl_extra_usage_flags
, aspect
);
305 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
306 * fall back to linear on Broadwell and earlier because we aren't
307 * guaranteed that we can handle offsets correctly. On Sky Lake, the
308 * horizontal and vertical alignments are sufficiently high that we can
309 * just use RENDER_SURFACE_STATE::X/Y Offset.
311 bool needs_shadow
= false;
312 if (dev
->info
.gen
<= 8 &&
313 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
314 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
315 assert(isl_format_is_compressed(plane_format
.isl_format
));
316 tiling_flags
= ISL_TILING_LINEAR_BIT
;
320 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
321 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
322 .format
= plane_format
.isl_format
,
323 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
324 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
325 .depth
= image
->extent
.depth
,
326 .levels
= vk_info
->mipLevels
,
327 .array_len
= vk_info
->arrayLayers
,
328 .samples
= vk_info
->samples
,
330 .row_pitch
= anv_info
->stride
,
332 .tiling_flags
= tiling_flags
);
334 /* isl_surf_init() will fail only if provided invalid input. Invalid input
335 * is illegal in Vulkan.
339 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
341 add_surface(image
, anv_surf
, plane
);
343 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
344 * create an identical tiled shadow surface for use while texturing so we
345 * don't get garbage performance.
348 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
349 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
351 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
352 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
353 .format
= plane_format
.isl_format
,
354 .width
= image
->extent
.width
,
355 .height
= image
->extent
.height
,
356 .depth
= image
->extent
.depth
,
357 .levels
= vk_info
->mipLevels
,
358 .array_len
= vk_info
->arrayLayers
,
359 .samples
= vk_info
->samples
,
361 .row_pitch
= anv_info
->stride
,
363 .tiling_flags
= ISL_TILING_ANY_MASK
);
365 /* isl_surf_init() will fail only if provided invalid input. Invalid input
366 * is illegal in Vulkan.
370 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
373 /* Add a HiZ surface to a depth buffer that will be used for rendering.
375 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
376 /* We don't advertise that depth buffers could be used as storage
379 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
381 /* Allow the user to control HiZ enabling. Disable by default on gen7
382 * because resolves are not currently implemented pre-BDW.
384 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
385 /* It will never be used as an attachment, HiZ is pointless. */
386 } else if (dev
->info
.gen
== 7) {
387 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
388 } else if (vk_info
->mipLevels
> 1) {
389 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
390 } else if (vk_info
->arrayLayers
> 1) {
391 anv_perf_warn(dev
->instance
, image
,
392 "Implement multi-arrayLayer HiZ clears and resolves");
393 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
394 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
395 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
396 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
397 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
398 &image
->planes
[plane
].surface
.isl
,
399 &image
->planes
[plane
].aux_surface
.isl
);
401 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
402 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
404 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
405 /* TODO: Disallow compression with :
407 * 1) non multiplanar images (We appear to hit a sampler bug with
408 * CCS & R16G16 format. Putting the clear state a page/4096bytes
409 * further fixes the issue).
411 * 2) alias images, because they might be aliases of images
414 * 3) compression disabled by debug
416 const bool allow_compression
=
417 image
->n_planes
== 1 &&
418 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
419 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
421 if (allow_compression
) {
422 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
423 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
424 &image
->planes
[plane
].surface
.isl
,
425 &image
->planes
[plane
].aux_surface
.isl
, 0);
428 /* Disable CCS when it is not useful (i.e., when you can't render
429 * to the image with CCS enabled).
431 if (!isl_format_supports_rendering(&dev
->info
,
432 plane_format
.isl_format
)) {
433 /* While it may be technically possible to enable CCS for this
434 * image, we currently don't have things hooked up to get it
437 anv_perf_warn(dev
->instance
, image
,
438 "This image format doesn't support rendering. "
439 "Not allocating an CCS buffer.");
440 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
444 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
445 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
447 /* For images created without MUTABLE_FORMAT_BIT set, we know that
448 * they will always be used with the original format. In
449 * particular, they will always be used with a format that
450 * supports color compression. If it's never used as a storage
451 * image, then it will only be used through the sampler or the as
452 * a render target. This means that it's safe to just leave
453 * compression on at all times for these formats.
455 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
456 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
457 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
461 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
462 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
463 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
464 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
465 &image
->planes
[plane
].surface
.isl
,
466 &image
->planes
[plane
].aux_surface
.isl
);
468 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
469 add_fast_clear_state_buffer(image
, aspect
, plane
, dev
);
470 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
474 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
476 /* Upper bound of the last surface should be smaller than the plane's
479 assert((MAX2(image
->planes
[plane
].surface
.offset
,
480 image
->planes
[plane
].aux_surface
.offset
) +
481 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
482 image
->planes
[plane
].aux_surface
.isl
.size
:
483 image
->planes
[plane
].surface
.isl
.size
)) <=
484 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
486 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
487 /* assert(image->planes[plane].fast_clear_state_offset == */
488 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
489 assert(image
->planes
[plane
].fast_clear_state_offset
<
490 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
497 anv_image_create(VkDevice _device
,
498 const struct anv_image_create_info
*create_info
,
499 const VkAllocationCallbacks
* alloc
,
502 ANV_FROM_HANDLE(anv_device
, device
, _device
);
503 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
504 struct anv_image
*image
= NULL
;
507 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
509 anv_assert(pCreateInfo
->mipLevels
> 0);
510 anv_assert(pCreateInfo
->arrayLayers
> 0);
511 anv_assert(pCreateInfo
->samples
> 0);
512 anv_assert(pCreateInfo
->extent
.width
> 0);
513 anv_assert(pCreateInfo
->extent
.height
> 0);
514 anv_assert(pCreateInfo
->extent
.depth
> 0);
516 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
517 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
519 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
521 image
->type
= pCreateInfo
->imageType
;
522 image
->extent
= pCreateInfo
->extent
;
523 image
->vk_format
= pCreateInfo
->format
;
524 image
->format
= anv_get_format(pCreateInfo
->format
);
525 image
->aspects
= vk_format_aspects(image
->vk_format
);
526 image
->levels
= pCreateInfo
->mipLevels
;
527 image
->array_size
= pCreateInfo
->arrayLayers
;
528 image
->samples
= pCreateInfo
->samples
;
529 image
->usage
= pCreateInfo
->usage
;
530 image
->tiling
= pCreateInfo
->tiling
;
531 image
->drm_format_mod
= DRM_FORMAT_MOD_INVALID
;
532 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
534 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
535 assert(format
!= NULL
);
537 const isl_tiling_flags_t isl_tiling_flags
=
538 choose_isl_tiling_flags(create_info
);
540 image
->n_planes
= format
->n_planes
;
543 for_each_bit(b
, image
->aspects
) {
544 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
550 *pImage
= anv_image_to_handle(image
);
556 vk_free2(&device
->alloc
, alloc
, image
);
562 anv_CreateImage(VkDevice device
,
563 const VkImageCreateInfo
*pCreateInfo
,
564 const VkAllocationCallbacks
*pAllocator
,
568 const VkNativeBufferANDROID
*gralloc_info
=
569 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
572 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
576 return anv_image_create(device
,
577 &(struct anv_image_create_info
) {
578 .vk_info
= pCreateInfo
,
585 anv_DestroyImage(VkDevice _device
, VkImage _image
,
586 const VkAllocationCallbacks
*pAllocator
)
588 ANV_FROM_HANDLE(anv_device
, device
, _device
);
589 ANV_FROM_HANDLE(anv_image
, image
, _image
);
594 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
595 if (image
->planes
[p
].bo_is_owned
) {
596 assert(image
->planes
[p
].bo
!= NULL
);
597 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
601 vk_free2(&device
->alloc
, pAllocator
, image
);
604 static void anv_image_bind_memory_plane(struct anv_device
*device
,
605 struct anv_image
*image
,
607 struct anv_device_memory
*memory
,
608 uint32_t memory_offset
)
610 assert(!image
->planes
[plane
].bo_is_owned
);
613 image
->planes
[plane
].bo
= NULL
;
614 image
->planes
[plane
].bo_offset
= 0;
618 image
->planes
[plane
].bo
= memory
->bo
;
619 image
->planes
[plane
].bo_offset
= memory_offset
;
622 VkResult
anv_BindImageMemory(
625 VkDeviceMemory _memory
,
626 VkDeviceSize memoryOffset
)
628 ANV_FROM_HANDLE(anv_device
, device
, _device
);
629 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
630 ANV_FROM_HANDLE(anv_image
, image
, _image
);
633 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
635 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
636 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
642 VkResult
anv_BindImageMemory2KHR(
644 uint32_t bindInfoCount
,
645 const VkBindImageMemoryInfoKHR
* pBindInfos
)
647 ANV_FROM_HANDLE(anv_device
, device
, _device
);
649 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
650 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
651 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
652 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
653 VkImageAspectFlags aspects
= image
->aspects
;
655 vk_foreach_struct_const(s
, bind_info
->pNext
) {
657 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
658 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
659 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
661 aspects
= plane_info
->planeAspect
;
665 anv_debug_ignored_stype(s
->sType
);
671 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
673 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
674 anv_image_bind_memory_plane(device
, image
, plane
,
675 mem
, bind_info
->memoryOffset
);
682 void anv_GetImageSubresourceLayout(
685 const VkImageSubresource
* subresource
,
686 VkSubresourceLayout
* layout
)
688 ANV_FROM_HANDLE(anv_image
, image
, _image
);
689 const struct anv_surface
*surface
=
690 get_surface(image
, subresource
->aspectMask
);
692 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
694 /* If we are on a non-zero mip level or array slice, we need to
695 * calculate a real offset.
697 anv_assert(subresource
->mipLevel
== 0);
698 anv_assert(subresource
->arrayLayer
== 0);
700 layout
->offset
= surface
->offset
;
701 layout
->rowPitch
= surface
->isl
.row_pitch
;
702 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
703 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
704 layout
->size
= surface
->isl
.size
;
708 * This function determines the optimal buffer to use for a given
709 * VkImageLayout and other pieces of information needed to make that
710 * determination. This does not determine the optimal buffer to use
711 * during a resolve operation.
713 * @param devinfo The device information of the Intel GPU.
714 * @param image The image that may contain a collection of buffers.
715 * @param plane The plane of the image to be accessed.
716 * @param layout The current layout of the image aspect(s).
718 * @return The primary buffer that should be used for the given layout.
721 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
722 const struct anv_image
* const image
,
723 const VkImageAspectFlagBits aspect
,
724 const VkImageLayout layout
)
726 /* Validate the inputs. */
728 /* The devinfo is needed as the optimal buffer varies across generations. */
729 assert(devinfo
!= NULL
);
731 /* The layout of a NULL image is not properly defined. */
732 assert(image
!= NULL
);
734 /* The aspect must be exactly one of the image aspects. */
735 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
737 /* Determine the optimal buffer. */
739 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
741 /* If there is no auxiliary surface allocated, we must use the one and only
744 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
745 return ISL_AUX_USAGE_NONE
;
747 /* All images that use an auxiliary surface are required to be tiled. */
748 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
750 /* Stencil has no aux */
751 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
753 /* The following switch currently only handles depth stencil aspects.
754 * TODO: Handle the color aspect.
756 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
)
757 return image
->planes
[plane
].aux_usage
;
761 /* Invalid Layouts */
762 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
763 case VK_IMAGE_LAYOUT_MAX_ENUM
:
764 unreachable("Invalid image layout.");
768 * The pre-initialized layout is equivalent to the undefined layout for
769 * optimally-tiled images. We can only do color compression (CCS or HiZ)
772 case VK_IMAGE_LAYOUT_UNDEFINED
:
773 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
774 return ISL_AUX_USAGE_NONE
;
779 * This buffer could be a depth buffer used in a transfer operation. BLORP
780 * currently doesn't use HiZ for transfer operations so we must use the main
781 * buffer for this layout. TODO: Enable HiZ in BLORP.
783 case VK_IMAGE_LAYOUT_GENERAL
:
784 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
785 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
786 return ISL_AUX_USAGE_NONE
;
789 /* Sampling Layouts */
790 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
791 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
793 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
794 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
795 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
796 if (anv_can_sample_with_hiz(devinfo
, image
))
797 return ISL_AUX_USAGE_HIZ
;
799 return ISL_AUX_USAGE_NONE
;
801 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
802 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
804 /* On SKL+, the render buffer can be decompressed by the presentation
805 * engine. Support for this feature has not yet landed in the wider
806 * ecosystem. TODO: Update this code when support lands.
808 * From the BDW PRM, Vol 7, Render Target Resolve:
810 * If the MCS is enabled on a non-multisampled render target, the
811 * render target must be resolved before being used for other
812 * purposes (display, texture, CPU lock) The clear value from
813 * SURFACE_STATE is written into pixels in the render target
814 * indicated as clear in the MCS.
816 * Pre-SKL, the render buffer must be resolved before being used for
817 * presentation. We can infer that the auxiliary buffer is not used.
819 return ISL_AUX_USAGE_NONE
;
822 /* Rendering Layouts */
823 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
824 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
825 unreachable("Color images are not yet supported.");
827 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
828 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
829 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
830 return ISL_AUX_USAGE_HIZ
;
832 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
833 unreachable("VK_KHR_shared_presentable_image is unsupported");
836 /* If the layout isn't recognized in the exhaustive switch above, the
837 * VkImageLayout value is not defined in vulkan.h.
839 unreachable("layout is not a VkImageLayout enumeration member.");
843 static struct anv_state
844 alloc_surface_state(struct anv_device
*device
)
846 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
849 static enum isl_channel_select
850 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
851 struct isl_swizzle format_swizzle
)
853 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
857 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
858 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
859 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
860 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
861 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
862 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
864 unreachable("Invalid swizzle");
869 anv_image_fill_surface_state(struct anv_device
*device
,
870 const struct anv_image
*image
,
871 VkImageAspectFlagBits aspect
,
872 const struct isl_view
*view_in
,
873 isl_surf_usage_flags_t view_usage
,
874 enum isl_aux_usage aux_usage
,
875 const union isl_color_value
*clear_color
,
876 enum anv_image_view_state_flags flags
,
877 struct anv_surface_state
*state_inout
,
878 struct brw_image_param
*image_param_out
)
880 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
882 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
883 *aux_surface
= &image
->planes
[plane
].aux_surface
;
885 struct isl_view view
= *view_in
;
886 view
.usage
|= view_usage
;
888 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
889 * compressed surface with a shadow surface, we use the shadow instead of
890 * the primary surface. The shadow surface will be tiled, unlike the main
891 * surface, so it should get significantly better performance.
893 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
894 isl_format_is_compressed(view
.format
) &&
895 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
896 assert(isl_format_is_compressed(surface
->isl
.format
));
897 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
898 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
899 surface
= &image
->planes
[plane
].shadow_surface
;
902 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
903 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
905 /* If this is a HiZ buffer we can sample from with a programmable clear
906 * value (SKL+), define the clear value to the optimal constant.
908 union isl_color_value default_clear_color
= { .u32
= { 0, } };
909 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
910 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
912 clear_color
= &default_clear_color
;
914 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
915 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
916 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
918 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
919 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
920 !isl_has_matching_typed_storage_image_format(&device
->info
,
922 /* In this case, we are a writeable storage buffer which needs to be
923 * lowered to linear. All tiling and offset calculations will be done in
926 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
927 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
929 .size
= surface
->isl
.size
,
930 .format
= ISL_FORMAT_RAW
,
932 .mocs
= device
->default_mocs
);
933 state_inout
->address
= address
,
934 state_inout
->aux_address
= 0;
936 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
937 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
938 /* Typed surface reads support a very limited subset of the shader
939 * image formats. Translate it into the closest format the hardware
942 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
943 view
.format
= isl_lower_storage_image_format(&device
->info
,
947 const struct isl_surf
*isl_surf
= &surface
->isl
;
949 struct isl_surf tmp_surf
;
950 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
951 if (isl_format_is_compressed(surface
->isl
.format
) &&
952 !isl_format_is_compressed(view
.format
)) {
953 /* We're creating an uncompressed view of a compressed surface. This
954 * is allowed but only for a single level/layer.
956 assert(surface
->isl
.samples
== 1);
957 assert(view
.levels
== 1);
958 assert(view
.array_len
== 1);
960 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
962 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
963 0 : view
.base_array_layer
,
964 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
965 view
.base_array_layer
: 0,
967 &offset_B
, &tile_x_sa
, &tile_y_sa
);
969 /* The newly created image represents the one subimage we're
970 * referencing with this view so it only has one array slice and
973 view
.base_array_layer
= 0;
976 /* We're making an uncompressed view here. The image dimensions need
977 * to be scaled down by the block size.
979 const struct isl_format_layout
*fmtl
=
980 isl_format_get_layout(surface
->isl
.format
);
981 tmp_surf
.format
= view
.format
;
982 tmp_surf
.logical_level0_px
.width
=
983 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
984 tmp_surf
.logical_level0_px
.height
=
985 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
986 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
987 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
988 tile_x_sa
/= fmtl
->bw
;
989 tile_y_sa
/= fmtl
->bh
;
991 isl_surf
= &tmp_surf
;
993 if (device
->info
.gen
<= 8) {
994 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
995 assert(tile_x_sa
== 0);
996 assert(tile_y_sa
== 0);
1000 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1003 .address
= address
+ offset_B
,
1004 .clear_color
= *clear_color
,
1005 .aux_surf
= &aux_surface
->isl
,
1006 .aux_usage
= aux_usage
,
1007 .aux_address
= aux_address
,
1008 .mocs
= device
->default_mocs
,
1009 .x_offset_sa
= tile_x_sa
,
1010 .y_offset_sa
= tile_y_sa
);
1011 state_inout
->address
= address
+ offset_B
;
1012 if (device
->info
.gen
>= 8) {
1013 state_inout
->aux_address
= aux_address
;
1015 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1016 * used to store other information. This should be ok, however,
1017 * because surface buffer addresses are always 4K page alinged.
1019 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1020 device
->isl_dev
.ss
.aux_addr_offset
;
1021 assert((aux_address
& 0xfff) == 0);
1022 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1023 state_inout
->aux_address
= *aux_addr_dw
;
1027 anv_state_flush(device
, state_inout
->state
);
1029 if (image_param_out
) {
1030 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1031 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1032 &surface
->isl
, &view
);
1036 static VkImageAspectFlags
1037 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1039 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1040 if (_mesa_bitcount(view_aspects
) == 1)
1041 return VK_IMAGE_ASPECT_COLOR_BIT
;
1043 VkImageAspectFlags color_aspects
= 0;
1044 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1045 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1046 return color_aspects
;
1048 /* No special remapping needed for depth & stencil aspects. */
1049 return view_aspects
;
1053 anv_CreateImageView(VkDevice _device
,
1054 const VkImageViewCreateInfo
*pCreateInfo
,
1055 const VkAllocationCallbacks
*pAllocator
,
1058 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1059 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1060 struct anv_image_view
*iview
;
1062 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1063 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1065 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1067 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1069 assert(range
->layerCount
> 0);
1070 assert(range
->baseMipLevel
< image
->levels
);
1072 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1073 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1074 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1075 /* View usage should be a subset of image usage */
1076 assert((view_usage
& ~image
->usage
) == 0);
1077 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1078 VK_IMAGE_USAGE_STORAGE_BIT
|
1079 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1080 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1081 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1083 switch (image
->type
) {
1085 unreachable("bad VkImageType");
1086 case VK_IMAGE_TYPE_1D
:
1087 case VK_IMAGE_TYPE_2D
:
1088 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1090 case VK_IMAGE_TYPE_3D
:
1091 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1092 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1096 /* First expand aspects to the image's ones (for example
1097 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1098 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1099 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1100 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1102 VkImageAspectFlags expanded_aspects
=
1103 anv_image_expand_aspects(image
, range
->aspectMask
);
1105 iview
->image
= image
;
1107 /* Remap the expanded aspects for the image view. For example if only
1108 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1109 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1110 * the image view, it only has a single plane.
1112 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1113 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1114 iview
->vk_format
= pCreateInfo
->format
;
1116 iview
->extent
= (VkExtent3D
) {
1117 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1118 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1119 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1122 /* Now go through the underlying image selected planes (computed in
1123 * expanded_aspects) and map them to planes in the image view.
1125 uint32_t iaspect_bit
, vplane
= 0;
1126 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1128 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1129 VkImageAspectFlags vplane_aspect
=
1130 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1131 struct anv_format_plane format
=
1132 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1133 vplane_aspect
, image
->tiling
);
1135 iview
->planes
[vplane
].image_plane
= iplane
;
1137 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1138 .format
= format
.isl_format
,
1139 .base_level
= range
->baseMipLevel
,
1140 .levels
= anv_get_levelCount(image
, range
),
1141 .base_array_layer
= range
->baseArrayLayer
,
1142 .array_len
= anv_get_layerCount(image
, range
),
1144 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1145 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1146 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1147 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1148 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1149 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1150 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1151 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1155 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1156 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1157 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1160 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1161 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1162 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1164 iview
->planes
[vplane
].isl
.usage
= 0;
1167 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1168 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1169 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1170 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1171 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1173 enum isl_aux_usage general_aux_usage
=
1174 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1175 VK_IMAGE_LAYOUT_GENERAL
);
1176 enum isl_aux_usage optimal_aux_usage
=
1177 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1178 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1180 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1181 &iview
->planes
[vplane
].isl
,
1182 ISL_SURF_USAGE_TEXTURE_BIT
,
1183 optimal_aux_usage
, NULL
,
1184 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1185 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1188 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1189 &iview
->planes
[vplane
].isl
,
1190 ISL_SURF_USAGE_TEXTURE_BIT
,
1191 general_aux_usage
, NULL
,
1193 &iview
->planes
[vplane
].general_sampler_surface_state
,
1197 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1198 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1199 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1200 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1202 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1203 &iview
->planes
[vplane
].isl
,
1204 ISL_SURF_USAGE_STORAGE_BIT
,
1205 ISL_AUX_USAGE_NONE
, NULL
,
1207 &iview
->planes
[vplane
].storage_surface_state
,
1208 &iview
->planes
[vplane
].storage_image_param
);
1210 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1211 &iview
->planes
[vplane
].isl
,
1212 ISL_SURF_USAGE_STORAGE_BIT
,
1213 ISL_AUX_USAGE_NONE
, NULL
,
1214 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1215 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1222 *pView
= anv_image_view_to_handle(iview
);
1228 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1229 const VkAllocationCallbacks
*pAllocator
)
1231 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1232 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1237 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1238 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1239 anv_state_pool_free(&device
->surface_state_pool
,
1240 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1243 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1244 anv_state_pool_free(&device
->surface_state_pool
,
1245 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1248 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1249 anv_state_pool_free(&device
->surface_state_pool
,
1250 iview
->planes
[plane
].storage_surface_state
.state
);
1253 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1254 anv_state_pool_free(&device
->surface_state_pool
,
1255 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1259 vk_free2(&device
->alloc
, pAllocator
, iview
);
1264 anv_CreateBufferView(VkDevice _device
,
1265 const VkBufferViewCreateInfo
*pCreateInfo
,
1266 const VkAllocationCallbacks
*pAllocator
,
1267 VkBufferView
*pView
)
1269 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1270 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1271 struct anv_buffer_view
*view
;
1273 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1274 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1276 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1278 /* TODO: Handle the format swizzle? */
1280 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1281 VK_IMAGE_ASPECT_COLOR_BIT
,
1282 VK_IMAGE_TILING_LINEAR
);
1283 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1284 view
->bo
= buffer
->bo
;
1285 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1286 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1287 pCreateInfo
->range
);
1288 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1290 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1291 view
->surface_state
= alloc_surface_state(device
);
1293 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1295 view
->offset
, view
->range
, format_bs
);
1297 view
->surface_state
= (struct anv_state
){ 0 };
1300 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1301 view
->storage_surface_state
= alloc_surface_state(device
);
1302 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1304 enum isl_format storage_format
=
1305 isl_has_matching_typed_storage_image_format(&device
->info
,
1307 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1310 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1312 view
->offset
, view
->range
,
1313 (storage_format
== ISL_FORMAT_RAW
? 1 :
1314 isl_format_get_layout(storage_format
)->bpb
/ 8));
1316 /* Write-only accesses should use the original format. */
1317 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1319 view
->offset
, view
->range
,
1320 isl_format_get_layout(view
->format
)->bpb
/ 8);
1322 isl_buffer_fill_image_param(&device
->isl_dev
,
1323 &view
->storage_image_param
,
1324 view
->format
, view
->range
);
1326 view
->storage_surface_state
= (struct anv_state
){ 0 };
1327 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1330 *pView
= anv_buffer_view_to_handle(view
);
1336 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1337 const VkAllocationCallbacks
*pAllocator
)
1339 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1340 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1345 if (view
->surface_state
.alloc_size
> 0)
1346 anv_state_pool_free(&device
->surface_state_pool
,
1347 view
->surface_state
);
1349 if (view
->storage_surface_state
.alloc_size
> 0)
1350 anv_state_pool_free(&device
->surface_state_pool
,
1351 view
->storage_surface_state
);
1353 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1354 anv_state_pool_free(&device
->surface_state_pool
,
1355 view
->writeonly_storage_surface_state
);
1357 vk_free2(&device
->alloc
, pAllocator
, view
);
1360 const struct anv_surface
*
1361 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1362 VkImageAspectFlags aspect_mask
)
1364 VkImageAspectFlags sanitized_mask
;
1366 switch (aspect_mask
) {
1367 case VK_IMAGE_ASPECT_COLOR_BIT
:
1368 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1369 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1371 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1372 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1373 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1375 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1376 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1377 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1379 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1380 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1381 * combined depth stencil formats. Specifically, it states:
1383 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1384 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1386 * Image views with both depth and stencil aspects are only valid for
1387 * render target attachments, in which case
1388 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1389 * stencil surfaces from the underlying surface.
1391 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1392 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1394 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1395 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1398 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1399 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1400 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1402 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1403 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1404 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1406 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1407 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1408 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1411 unreachable("image does not have aspect");
1415 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1416 return &image
->planes
[plane
].surface
;