2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
35 #include "util/u_math.h"
37 #include "vk_format_info.h"
39 static isl_surf_usage_flags_t
40 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
41 VkImageUsageFlags vk_usage
,
42 isl_surf_usage_flags_t isl_extra_usage
,
43 VkImageAspectFlagBits aspect
)
45 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
47 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
48 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
50 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
51 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
53 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
54 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
56 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
57 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
59 /* Even if we're only using it for transfer operations, clears to depth and
60 * stencil images happen as depth and stencil so they need the right ISL
61 * usage bits or else things will fall apart.
64 case VK_IMAGE_ASPECT_DEPTH_BIT
:
65 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
67 case VK_IMAGE_ASPECT_STENCIL_BIT
:
68 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
70 case VK_IMAGE_ASPECT_COLOR_BIT
:
71 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
72 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
73 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
76 unreachable("bad VkImageAspect");
79 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
80 /* blorp implements transfers by sampling from the source image. */
81 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
84 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
85 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
86 /* blorp implements transfers by rendering into the destination image.
87 * Only request this with color images, as we deal with depth/stencil
88 * formats differently. */
89 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
95 static isl_tiling_flags_t
96 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
97 const struct isl_drm_modifier_info
*isl_mod_info
,
100 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
101 isl_tiling_flags_t flags
= 0;
103 switch (base_info
->tiling
) {
105 unreachable("bad VkImageTiling");
106 case VK_IMAGE_TILING_OPTIMAL
:
107 flags
= ISL_TILING_ANY_MASK
;
109 case VK_IMAGE_TILING_LINEAR
:
110 flags
= ISL_TILING_LINEAR_BIT
;
114 if (anv_info
->isl_tiling_flags
)
115 flags
&= anv_info
->isl_tiling_flags
;
118 flags
&= ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
;
121 flags
&= 1 << isl_mod_info
->tiling
;
128 static struct anv_surface
*
129 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
131 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
132 return &image
->planes
[plane
].surface
;
136 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
138 assert(surf
->isl
.size_B
> 0); /* isl surface must be initialized */
140 if (image
->disjoint
) {
141 surf
->offset
= align_u32(image
->planes
[plane
].size
,
142 surf
->isl
.alignment_B
);
143 /* Plane offset is always 0 when it's disjoint. */
145 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment_B
);
146 /* Determine plane's offset only once when the first surface is added. */
147 if (image
->planes
[plane
].size
== 0)
148 image
->planes
[plane
].offset
= image
->size
;
151 image
->size
= surf
->offset
+ surf
->isl
.size_B
;
152 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size_B
) - image
->planes
[plane
].offset
;
154 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment_B
);
155 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
156 surf
->isl
.alignment_B
);
161 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
162 const VkImageFormatListCreateInfoKHR
*fmt_list
,
163 struct anv_image
*image
)
165 enum isl_format format
=
166 anv_get_isl_format(devinfo
, image
->vk_format
,
167 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
169 if (!isl_format_supports_ccs_e(devinfo
, format
))
172 if (!(image
->create_flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
175 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
178 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
179 enum isl_format view_format
=
180 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
181 VK_IMAGE_ASPECT_COLOR_BIT
, image
->tiling
);
183 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
191 * For color images that have an auxiliary surface, request allocation for an
192 * additional buffer that mainly stores fast-clear values. Use of this buffer
193 * allows us to access the image's subresources while being aware of their
194 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
195 * which a fast clear has occurred).
197 * In order to avoid having multiple clear colors for a single plane of an
198 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
199 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
200 * 2018), there were no known applications which would benefit from fast-
201 * clearing more than just the first slice.
203 * The fast clear portion of the image is laid out in the following order:
205 * * 1 or 4 dwords (depending on hardware generation) for the clear color
206 * * 1 dword for the anv_fast_clear_type of the clear color
207 * * On gen9+, 1 dword per level and layer of the image (3D levels count
208 * multiple layers) in level-major order for compression state.
210 * For the purpose of discoverability, the algorithm used to manage
211 * compression and fast-clears is described here:
213 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
214 * all of the values in the fast clear portion of the image are initialized
217 * * On fast-clear, the clear value is written into surface state and also
218 * into the buffer and the fast clear type is set appropriately. Both
219 * setting the fast-clear value in the buffer and setting the fast-clear
220 * type happen from the GPU using MI commands.
222 * * Whenever a render or blorp operation is performed with CCS_E, we call
223 * genX(cmd_buffer_mark_image_written) to set the compression state to
224 * true (which is represented by UINT32_MAX).
226 * * On pipeline barrier transitions, the worst-case transition is computed
227 * from the image layouts. The command streamer inspects the fast clear
228 * type and compression state dwords and constructs a predicate. The
229 * worst-case resolve is performed with the given predicate and the fast
230 * clear and compression state is set accordingly.
232 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
233 * details on exactly what is allowed in what layouts.
235 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
236 * In order to deal with this, we have to do some clear color management.
238 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
239 * value from the buffer into the surface state with MI commands.
241 * * For any blorp operations, we pass the address to the clear value into
242 * blorp and it knows to copy the clear color.
245 add_aux_state_tracking_buffer(struct anv_image
*image
,
247 const struct anv_device
*device
)
249 assert(image
&& device
);
250 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 &&
251 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
253 /* Compressed images must be tiled and therefore everything should be 4K
254 * aligned. The CCS has the same alignment requirements. This is good
255 * because we need at least dword-alignment for MI_LOAD/STORE operations.
257 assert(image
->alignment
% 4 == 0);
258 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
260 /* This buffer should be at the very end of the plane. */
261 if (image
->disjoint
) {
262 assert(image
->planes
[plane
].size
==
263 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
265 assert(image
->size
==
266 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
269 const unsigned clear_color_state_size
= device
->info
.gen
>= 10 ?
270 device
->isl_dev
.ss
.clear_color_state_size
:
271 device
->isl_dev
.ss
.clear_value_size
;
273 /* Clear color and fast clear type */
274 unsigned state_size
= clear_color_state_size
+ 4;
276 /* We only need to track compression on CCS_E surfaces. */
277 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
278 if (image
->type
== VK_IMAGE_TYPE_3D
) {
279 for (uint32_t l
= 0; l
< image
->levels
; l
++)
280 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
282 state_size
+= image
->levels
* image
->array_size
* 4;
286 image
->planes
[plane
].fast_clear_state_offset
=
287 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
289 image
->planes
[plane
].size
+= state_size
;
290 image
->size
+= state_size
;
294 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
295 * image's memory requirements (that is, the image's size and alignment).
298 make_surface(const struct anv_device
*dev
,
299 struct anv_image
*image
,
301 isl_tiling_flags_t tiling_flags
,
302 isl_surf_usage_flags_t isl_extra_usage_flags
,
303 VkImageAspectFlagBits aspect
)
307 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
308 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
309 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
310 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
313 image
->extent
= anv_sanitize_image_extent(image
->type
, image
->extent
);
315 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
316 const struct anv_format_plane plane_format
=
317 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
318 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
320 const isl_surf_usage_flags_t usage
=
321 choose_isl_surf_usage(image
->create_flags
, image
->usage
,
322 isl_extra_usage_flags
, aspect
);
324 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
325 * fall back to linear on Broadwell and earlier because we aren't
326 * guaranteed that we can handle offsets correctly. On Sky Lake, the
327 * horizontal and vertical alignments are sufficiently high that we can
328 * just use RENDER_SURFACE_STATE::X/Y Offset.
330 bool needs_shadow
= false;
331 if (dev
->info
.gen
<= 8 &&
332 (image
->create_flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT
) &&
333 image
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
334 assert(isl_format_is_compressed(plane_format
.isl_format
));
335 tiling_flags
= ISL_TILING_LINEAR_BIT
;
339 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
340 .dim
= vk_to_isl_surf_dim
[image
->type
],
341 .format
= plane_format
.isl_format
,
342 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
343 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
344 .depth
= image
->extent
.depth
,
345 .levels
= image
->levels
,
346 .array_len
= image
->array_size
,
347 .samples
= image
->samples
,
348 .min_alignment_B
= 0,
349 .row_pitch_B
= stride
,
351 .tiling_flags
= tiling_flags
);
354 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
356 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
358 add_surface(image
, anv_surf
, plane
);
360 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
361 * create an identical tiled shadow surface for use while texturing so we
362 * don't get garbage performance.
365 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
366 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
368 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
369 .dim
= vk_to_isl_surf_dim
[image
->type
],
370 .format
= plane_format
.isl_format
,
371 .width
= image
->extent
.width
,
372 .height
= image
->extent
.height
,
373 .depth
= image
->extent
.depth
,
374 .levels
= image
->levels
,
375 .array_len
= image
->array_size
,
376 .samples
= image
->samples
,
377 .min_alignment_B
= 0,
378 .row_pitch_B
= stride
,
380 .tiling_flags
= ISL_TILING_ANY_MASK
);
382 /* isl_surf_init() will fail only if provided invalid input. Invalid input
383 * is illegal in Vulkan.
387 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
390 /* Add a HiZ surface to a depth buffer that will be used for rendering.
392 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
393 /* We don't advertise that depth buffers could be used as storage
396 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
398 /* Allow the user to control HiZ enabling. Disable by default on gen7
399 * because resolves are not currently implemented pre-BDW.
401 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
402 /* It will never be used as an attachment, HiZ is pointless. */
403 } else if (dev
->info
.gen
== 7) {
404 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
405 } else if (image
->levels
> 1) {
406 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
407 } else if (image
->array_size
> 1) {
408 anv_perf_warn(dev
->instance
, image
,
409 "Implement multi-arrayLayer HiZ clears and resolves");
410 } else if (dev
->info
.gen
== 8 && image
->samples
> 1) {
411 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
412 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
413 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
414 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
415 &image
->planes
[plane
].surface
.isl
,
416 &image
->planes
[plane
].aux_surface
.isl
);
418 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
419 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
421 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && image
->samples
== 1) {
422 /* TODO: Disallow compression with :
424 * 1) non multiplanar images (We appear to hit a sampler bug with
425 * CCS & R16G16 format. Putting the clear state a page/4096bytes
426 * further fixes the issue).
428 * 2) alias images, because they might be aliases of images
431 * 3) compression disabled by debug
433 const bool allow_compression
=
434 image
->n_planes
== 1 &&
435 (image
->create_flags
& VK_IMAGE_CREATE_ALIAS_BIT
) == 0 &&
436 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
438 if (allow_compression
) {
439 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
440 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
441 &image
->planes
[plane
].surface
.isl
,
442 &image
->planes
[plane
].aux_surface
.isl
, 0);
445 /* Disable CCS when it is not useful (i.e., when you can't render
446 * to the image with CCS enabled).
448 if (!isl_format_supports_rendering(&dev
->info
,
449 plane_format
.isl_format
)) {
450 /* While it may be technically possible to enable CCS for this
451 * image, we currently don't have things hooked up to get it
454 anv_perf_warn(dev
->instance
, image
,
455 "This image format doesn't support rendering. "
456 "Not allocating an CCS buffer.");
457 image
->planes
[plane
].aux_surface
.isl
.size_B
= 0;
461 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
462 add_aux_state_tracking_buffer(image
, plane
, dev
);
464 /* For images created without MUTABLE_FORMAT_BIT set, we know that
465 * they will always be used with the original format. In
466 * particular, they will always be used with a format that
467 * supports color compression. If it's never used as a storage
468 * image, then it will only be used through the sampler or the as
469 * a render target. This means that it's safe to just leave
470 * compression on at all times for these formats.
472 if (!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
473 image
->ccs_e_compatible
) {
474 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
478 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && image
->samples
> 1) {
479 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
480 assert(image
->planes
[plane
].aux_surface
.isl
.size_B
== 0);
481 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
482 &image
->planes
[plane
].surface
.isl
,
483 &image
->planes
[plane
].aux_surface
.isl
);
485 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
486 add_aux_state_tracking_buffer(image
, plane
, dev
);
487 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
491 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
493 /* Upper bound of the last surface should be smaller than the plane's
496 assert((MAX2(image
->planes
[plane
].surface
.offset
,
497 image
->planes
[plane
].aux_surface
.offset
) +
498 (image
->planes
[plane
].aux_surface
.isl
.size_B
> 0 ?
499 image
->planes
[plane
].aux_surface
.isl
.size_B
:
500 image
->planes
[plane
].surface
.isl
.size_B
)) <=
501 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
503 if (image
->planes
[plane
].aux_surface
.isl
.size_B
) {
504 /* assert(image->planes[plane].fast_clear_state_offset == */
505 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
506 assert(image
->planes
[plane
].fast_clear_state_offset
<
507 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
514 score_drm_format_mod(uint64_t modifier
)
517 case DRM_FORMAT_MOD_LINEAR
: return 1;
518 case I915_FORMAT_MOD_X_TILED
: return 2;
519 case I915_FORMAT_MOD_Y_TILED
: return 3;
520 case I915_FORMAT_MOD_Y_TILED_CCS
: return 4;
521 default: unreachable("bad DRM format modifier");
525 static const struct isl_drm_modifier_info
*
526 choose_drm_format_mod(const struct anv_physical_device
*device
,
527 uint32_t modifier_count
, const uint64_t *modifiers
)
529 uint64_t best_mod
= UINT64_MAX
;
530 uint32_t best_score
= 0;
532 for (uint32_t i
= 0; i
< modifier_count
; ++i
) {
533 uint32_t score
= score_drm_format_mod(modifiers
[i
]);
534 if (score
> best_score
) {
535 best_mod
= modifiers
[i
];
541 return isl_drm_modifier_get_info(best_mod
);
547 anv_image_create(VkDevice _device
,
548 const struct anv_image_create_info
*create_info
,
549 const VkAllocationCallbacks
* alloc
,
552 ANV_FROM_HANDLE(anv_device
, device
, _device
);
553 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
554 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
555 struct anv_image
*image
= NULL
;
558 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
560 const struct wsi_image_create_info
*wsi_info
=
561 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
562 if (wsi_info
&& wsi_info
->modifier_count
> 0) {
563 isl_mod_info
= choose_drm_format_mod(&device
->instance
->physicalDevice
,
564 wsi_info
->modifier_count
,
565 wsi_info
->modifiers
);
566 assert(isl_mod_info
);
569 anv_assert(pCreateInfo
->mipLevels
> 0);
570 anv_assert(pCreateInfo
->arrayLayers
> 0);
571 anv_assert(pCreateInfo
->samples
> 0);
572 anv_assert(pCreateInfo
->extent
.width
> 0);
573 anv_assert(pCreateInfo
->extent
.height
> 0);
574 anv_assert(pCreateInfo
->extent
.depth
> 0);
576 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
577 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
579 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
581 image
->type
= pCreateInfo
->imageType
;
582 image
->extent
= pCreateInfo
->extent
;
583 image
->vk_format
= pCreateInfo
->format
;
584 image
->format
= anv_get_format(pCreateInfo
->format
);
585 image
->aspects
= vk_format_aspects(image
->vk_format
);
586 image
->levels
= pCreateInfo
->mipLevels
;
587 image
->array_size
= pCreateInfo
->arrayLayers
;
588 image
->samples
= pCreateInfo
->samples
;
589 image
->usage
= pCreateInfo
->usage
;
590 image
->create_flags
= pCreateInfo
->flags
;
591 image
->tiling
= pCreateInfo
->tiling
;
592 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT
;
593 image
->needs_set_tiling
= wsi_info
&& wsi_info
->scanout
;
594 image
->drm_format_mod
= isl_mod_info
? isl_mod_info
->modifier
:
595 DRM_FORMAT_MOD_INVALID
;
597 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
598 assert(format
!= NULL
);
600 const isl_tiling_flags_t isl_tiling_flags
=
601 choose_isl_tiling_flags(create_info
, isl_mod_info
,
602 image
->needs_set_tiling
);
604 image
->n_planes
= format
->n_planes
;
606 const VkImageFormatListCreateInfoKHR
*fmt_list
=
607 vk_find_struct_const(pCreateInfo
->pNext
,
608 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
610 image
->ccs_e_compatible
=
611 all_formats_ccs_e_compatible(&device
->info
, fmt_list
, image
);
614 for_each_bit(b
, image
->aspects
) {
615 r
= make_surface(device
, image
, create_info
->stride
, isl_tiling_flags
,
616 create_info
->isl_extra_usage_flags
, (1 << b
));
621 *pImage
= anv_image_to_handle(image
);
627 vk_free2(&device
->alloc
, alloc
, image
);
633 anv_CreateImage(VkDevice device
,
634 const VkImageCreateInfo
*pCreateInfo
,
635 const VkAllocationCallbacks
*pAllocator
,
638 const VkNativeBufferANDROID
*gralloc_info
=
639 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
642 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
645 return anv_image_create(device
,
646 &(struct anv_image_create_info
) {
647 .vk_info
= pCreateInfo
,
654 anv_DestroyImage(VkDevice _device
, VkImage _image
,
655 const VkAllocationCallbacks
*pAllocator
)
657 ANV_FROM_HANDLE(anv_device
, device
, _device
);
658 ANV_FROM_HANDLE(anv_image
, image
, _image
);
663 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
664 if (image
->planes
[p
].bo_is_owned
) {
665 assert(image
->planes
[p
].address
.bo
!= NULL
);
666 anv_bo_cache_release(device
, &device
->bo_cache
,
667 image
->planes
[p
].address
.bo
);
671 vk_free2(&device
->alloc
, pAllocator
, image
);
674 static void anv_image_bind_memory_plane(struct anv_device
*device
,
675 struct anv_image
*image
,
677 struct anv_device_memory
*memory
,
678 uint32_t memory_offset
)
680 assert(!image
->planes
[plane
].bo_is_owned
);
683 image
->planes
[plane
].address
= ANV_NULL_ADDRESS
;
687 image
->planes
[plane
].address
= (struct anv_address
) {
689 .offset
= memory_offset
,
693 VkResult
anv_BindImageMemory(
696 VkDeviceMemory _memory
,
697 VkDeviceSize memoryOffset
)
699 ANV_FROM_HANDLE(anv_device
, device
, _device
);
700 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
701 ANV_FROM_HANDLE(anv_image
, image
, _image
);
704 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
706 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
707 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
713 VkResult
anv_BindImageMemory2(
715 uint32_t bindInfoCount
,
716 const VkBindImageMemoryInfo
* pBindInfos
)
718 ANV_FROM_HANDLE(anv_device
, device
, _device
);
720 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
721 const VkBindImageMemoryInfo
*bind_info
= &pBindInfos
[i
];
722 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
723 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
724 VkImageAspectFlags aspects
= image
->aspects
;
726 vk_foreach_struct_const(s
, bind_info
->pNext
) {
728 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO
: {
729 const VkBindImagePlaneMemoryInfo
*plane_info
=
730 (const VkBindImagePlaneMemoryInfo
*) s
;
732 aspects
= plane_info
->planeAspect
;
736 anv_debug_ignored_stype(s
->sType
);
742 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
744 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
745 anv_image_bind_memory_plane(device
, image
, plane
,
746 mem
, bind_info
->memoryOffset
);
753 void anv_GetImageSubresourceLayout(
756 const VkImageSubresource
* subresource
,
757 VkSubresourceLayout
* layout
)
759 ANV_FROM_HANDLE(anv_image
, image
, _image
);
761 const struct anv_surface
*surface
;
762 if (subresource
->aspectMask
== VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
&&
763 image
->drm_format_mod
!= DRM_FORMAT_MOD_INVALID
&&
764 isl_drm_modifier_has_aux(image
->drm_format_mod
))
765 surface
= &image
->planes
[0].aux_surface
;
767 surface
= get_surface(image
, subresource
->aspectMask
);
769 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
771 layout
->offset
= surface
->offset
;
772 layout
->rowPitch
= surface
->isl
.row_pitch_B
;
773 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
774 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
776 if (subresource
->mipLevel
> 0 || subresource
->arrayLayer
> 0) {
777 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
780 isl_surf_get_image_offset_B_tile_sa(&surface
->isl
,
781 subresource
->mipLevel
,
782 subresource
->arrayLayer
,
783 0 /* logical_z_offset_px */,
784 &offset_B
, NULL
, NULL
);
785 layout
->offset
+= offset_B
;
786 layout
->size
= layout
->rowPitch
* anv_minify(image
->extent
.height
,
787 subresource
->mipLevel
);
789 layout
->size
= surface
->isl
.size_B
;
794 * This function determines the optimal buffer to use for a given
795 * VkImageLayout and other pieces of information needed to make that
796 * determination. This does not determine the optimal buffer to use
797 * during a resolve operation.
799 * @param devinfo The device information of the Intel GPU.
800 * @param image The image that may contain a collection of buffers.
801 * @param aspect The aspect of the image to be accessed.
802 * @param layout The current layout of the image aspect(s).
804 * @return The primary buffer that should be used for the given layout.
807 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
808 const struct anv_image
* const image
,
809 const VkImageAspectFlagBits aspect
,
810 const VkImageLayout layout
)
812 /* Validate the inputs. */
814 /* The devinfo is needed as the optimal buffer varies across generations. */
815 assert(devinfo
!= NULL
);
817 /* The layout of a NULL image is not properly defined. */
818 assert(image
!= NULL
);
820 /* The aspect must be exactly one of the image aspects. */
821 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
823 /* Determine the optimal buffer. */
825 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
827 /* If there is no auxiliary surface allocated, we must use the one and only
830 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
831 return ISL_AUX_USAGE_NONE
;
833 /* All images that use an auxiliary surface are required to be tiled. */
834 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
836 /* Stencil has no aux */
837 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
841 /* Invalid Layouts */
842 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
843 case VK_IMAGE_LAYOUT_MAX_ENUM
:
844 unreachable("Invalid image layout.");
848 * The pre-initialized layout is equivalent to the undefined layout for
849 * optimally-tiled images. We can only do color compression (CCS or HiZ)
852 case VK_IMAGE_LAYOUT_UNDEFINED
:
853 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
854 return ISL_AUX_USAGE_NONE
;
859 case VK_IMAGE_LAYOUT_GENERAL
:
860 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
861 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
862 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
863 /* This buffer could be a depth buffer used in a transfer operation.
864 * BLORP currently doesn't use HiZ for transfer operations so we must
865 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
867 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
868 return ISL_AUX_USAGE_NONE
;
870 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
871 return image
->planes
[plane
].aux_usage
;
875 /* Sampling Layouts */
876 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
877 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
:
878 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
880 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
881 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
882 if (anv_can_sample_with_hiz(devinfo
, image
))
883 return ISL_AUX_USAGE_HIZ
;
885 return ISL_AUX_USAGE_NONE
;
887 return image
->planes
[plane
].aux_usage
;
891 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
892 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
894 /* When handing the image off to the presentation engine, we need to
895 * ensure that things are properly resolved. For images with no
896 * modifier, we assume that they follow the old rules and always need
897 * a full resolve because the PE doesn't understand any form of
898 * compression. For images with modifiers, we use the aux usage from
901 const struct isl_drm_modifier_info
*mod_info
=
902 isl_drm_modifier_get_info(image
->drm_format_mod
);
903 return mod_info
? mod_info
->aux_usage
: ISL_AUX_USAGE_NONE
;
907 /* Rendering Layouts */
908 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
909 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
910 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
911 assert(image
->samples
== 1);
912 return ISL_AUX_USAGE_CCS_D
;
914 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
915 return image
->planes
[plane
].aux_usage
;
918 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
919 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL
:
920 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
921 return ISL_AUX_USAGE_HIZ
;
923 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
924 unreachable("VK_KHR_shared_presentable_image is unsupported");
926 case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT
:
927 unreachable("VK_EXT_fragment_density_map is unsupported");
929 case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV
:
930 unreachable("VK_NV_shading_rate_image is unsupported");
933 /* If the layout isn't recognized in the exhaustive switch above, the
934 * VkImageLayout value is not defined in vulkan.h.
936 unreachable("layout is not a VkImageLayout enumeration member.");
940 * This function returns the level of unresolved fast-clear support of the
941 * given image in the given VkImageLayout.
943 * @param devinfo The device information of the Intel GPU.
944 * @param image The image that may contain a collection of buffers.
945 * @param aspect The aspect of the image to be accessed.
946 * @param layout The current layout of the image aspect(s).
948 enum anv_fast_clear_type
949 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
950 const struct anv_image
* const image
,
951 const VkImageAspectFlagBits aspect
,
952 const VkImageLayout layout
)
954 /* The aspect must be exactly one of the image aspects. */
955 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
957 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
959 /* If there is no auxiliary surface allocated, there are no fast-clears */
960 if (image
->planes
[plane
].aux_surface
.isl
.size_B
== 0)
961 return ANV_FAST_CLEAR_NONE
;
963 /* All images that use an auxiliary surface are required to be tiled. */
964 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
966 /* Stencil has no aux */
967 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
969 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
970 /* For depth images (with HiZ), the layout supports fast-clears if and
971 * only if it supports HiZ. However, we only support fast-clears to the
972 * default depth value.
974 enum isl_aux_usage aux_usage
=
975 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
976 return aux_usage
== ISL_AUX_USAGE_HIZ
?
977 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
980 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
982 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
983 * lack the MI ALU which we need to determine the predicates.
985 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&& image
->samples
> 1)
986 return ANV_FAST_CLEAR_NONE
;
989 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
990 return ANV_FAST_CLEAR_ANY
;
992 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
: {
993 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
995 /* We do not yet support any modifiers which support clear color so we
996 * just always return NONE. One day, this will change.
998 const struct isl_drm_modifier_info
*mod_info
=
999 isl_drm_modifier_get_info(image
->drm_format_mod
);
1000 assert(!mod_info
|| !mod_info
->supports_clear_color
);
1002 return ANV_FAST_CLEAR_NONE
;
1006 /* If the image has MCS or CCS_E enabled all the time then we can use
1007 * fast-clear as long as the clear color is the default value of zero
1008 * since this is the default value we program into every surface state
1009 * used for texturing.
1011 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_MCS
||
1012 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
1013 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
1015 return ANV_FAST_CLEAR_NONE
;
1020 static struct anv_state
1021 alloc_surface_state(struct anv_device
*device
)
1023 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
1026 static enum isl_channel_select
1027 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
1028 struct isl_swizzle format_swizzle
)
1030 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
1031 swizzle
= component
;
1034 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
1035 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
1036 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
1037 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
1038 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
1039 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
1041 unreachable("Invalid swizzle");
1046 anv_image_fill_surface_state(struct anv_device
*device
,
1047 const struct anv_image
*image
,
1048 VkImageAspectFlagBits aspect
,
1049 const struct isl_view
*view_in
,
1050 isl_surf_usage_flags_t view_usage
,
1051 enum isl_aux_usage aux_usage
,
1052 const union isl_color_value
*clear_color
,
1053 enum anv_image_view_state_flags flags
,
1054 struct anv_surface_state
*state_inout
,
1055 struct brw_image_param
*image_param_out
)
1057 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1059 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
1060 *aux_surface
= &image
->planes
[plane
].aux_surface
;
1062 struct isl_view view
= *view_in
;
1063 view
.usage
|= view_usage
;
1065 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1066 * compressed surface with a shadow surface, we use the shadow instead of
1067 * the primary surface. The shadow surface will be tiled, unlike the main
1068 * surface, so it should get significantly better performance.
1070 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1071 isl_format_is_compressed(view
.format
) &&
1072 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
1073 assert(isl_format_is_compressed(surface
->isl
.format
));
1074 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1075 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1076 surface
= &image
->planes
[plane
].shadow_surface
;
1079 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1080 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1082 /* If this is a HiZ buffer we can sample from with a programmable clear
1083 * value (SKL+), define the clear value to the optimal constant.
1085 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1086 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1087 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1089 clear_color
= &default_clear_color
;
1091 const struct anv_address address
=
1092 anv_address_add(image
->planes
[plane
].address
, surface
->offset
);
1094 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1095 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1096 !isl_has_matching_typed_storage_image_format(&device
->info
,
1098 /* In this case, we are a writeable storage buffer which needs to be
1099 * lowered to linear. All tiling and offset calculations will be done in
1102 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1103 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1104 .address
= anv_address_physical(address
),
1105 .size_B
= surface
->isl
.size_B
,
1106 .format
= ISL_FORMAT_RAW
,
1108 .mocs
= anv_mocs_for_bo(device
, address
.bo
));
1109 state_inout
->address
= address
,
1110 state_inout
->aux_address
= ANV_NULL_ADDRESS
;
1111 state_inout
->clear_address
= ANV_NULL_ADDRESS
;
1113 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1114 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1115 /* Typed surface reads support a very limited subset of the shader
1116 * image formats. Translate it into the closest format the hardware
1119 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1120 view
.format
= isl_lower_storage_image_format(&device
->info
,
1124 const struct isl_surf
*isl_surf
= &surface
->isl
;
1126 struct isl_surf tmp_surf
;
1127 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1128 if (isl_format_is_compressed(surface
->isl
.format
) &&
1129 !isl_format_is_compressed(view
.format
)) {
1130 /* We're creating an uncompressed view of a compressed surface. This
1131 * is allowed but only for a single level/layer.
1133 assert(surface
->isl
.samples
== 1);
1134 assert(view
.levels
== 1);
1135 assert(view
.array_len
== 1);
1137 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1139 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1140 0 : view
.base_array_layer
,
1141 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1142 view
.base_array_layer
: 0,
1144 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1146 /* The newly created image represents the one subimage we're
1147 * referencing with this view so it only has one array slice and
1150 view
.base_array_layer
= 0;
1151 view
.base_level
= 0;
1153 /* We're making an uncompressed view here. The image dimensions need
1154 * to be scaled down by the block size.
1156 const struct isl_format_layout
*fmtl
=
1157 isl_format_get_layout(surface
->isl
.format
);
1158 tmp_surf
.format
= view
.format
;
1159 tmp_surf
.logical_level0_px
.width
=
1160 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1161 tmp_surf
.logical_level0_px
.height
=
1162 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1163 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1164 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1165 tile_x_sa
/= fmtl
->bw
;
1166 tile_y_sa
/= fmtl
->bh
;
1168 isl_surf
= &tmp_surf
;
1170 if (device
->info
.gen
<= 8) {
1171 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1172 assert(tile_x_sa
== 0);
1173 assert(tile_y_sa
== 0);
1177 state_inout
->address
= anv_address_add(address
, offset_B
);
1179 struct anv_address aux_address
= ANV_NULL_ADDRESS
;
1180 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
1181 aux_address
= anv_address_add(image
->planes
[plane
].address
,
1182 aux_surface
->offset
);
1184 state_inout
->aux_address
= aux_address
;
1186 struct anv_address clear_address
= ANV_NULL_ADDRESS
;
1187 if (device
->info
.gen
>= 10 && aux_usage
!= ISL_AUX_USAGE_NONE
) {
1188 if (aux_usage
== ISL_AUX_USAGE_HIZ
) {
1189 clear_address
= (struct anv_address
) {
1190 .bo
= &device
->hiz_clear_bo
,
1194 clear_address
= anv_image_get_clear_color_addr(device
, image
, aspect
);
1197 state_inout
->clear_address
= clear_address
;
1199 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1202 .address
= anv_address_physical(state_inout
->address
),
1203 .clear_color
= *clear_color
,
1204 .aux_surf
= &aux_surface
->isl
,
1205 .aux_usage
= aux_usage
,
1206 .aux_address
= anv_address_physical(aux_address
),
1207 .clear_address
= anv_address_physical(clear_address
),
1208 .use_clear_address
= !anv_address_is_null(clear_address
),
1209 .mocs
= anv_mocs_for_bo(device
,
1210 state_inout
->address
.bo
),
1211 .x_offset_sa
= tile_x_sa
,
1212 .y_offset_sa
= tile_y_sa
);
1214 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1215 * are used to store other information. This should be ok, however,
1216 * because the surface buffer addresses are always 4K page aligned.
1218 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1219 device
->isl_dev
.ss
.aux_addr_offset
;
1220 assert((aux_address
.offset
& 0xfff) == 0);
1221 state_inout
->aux_address
.offset
|= *aux_addr_dw
& 0xfff;
1223 if (device
->info
.gen
>= 10 && clear_address
.bo
) {
1224 uint32_t *clear_addr_dw
= state_inout
->state
.map
+
1225 device
->isl_dev
.ss
.clear_color_state_offset
;
1226 assert((clear_address
.offset
& 0x3f) == 0);
1227 state_inout
->clear_address
.offset
|= *clear_addr_dw
& 0x3f;
1231 anv_state_flush(device
, state_inout
->state
);
1233 if (image_param_out
) {
1234 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1235 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1236 &surface
->isl
, &view
);
1240 static VkImageAspectFlags
1241 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1243 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1244 if (util_bitcount(view_aspects
) == 1)
1245 return VK_IMAGE_ASPECT_COLOR_BIT
;
1247 VkImageAspectFlags color_aspects
= 0;
1248 for (uint32_t i
= 0; i
< util_bitcount(view_aspects
); i
++)
1249 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT
<< i
;
1250 return color_aspects
;
1252 /* No special remapping needed for depth & stencil aspects. */
1253 return view_aspects
;
1257 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask
)
1259 uint32_t planes
= 0;
1261 if (aspect_mask
& (VK_IMAGE_ASPECT_COLOR_BIT
|
1262 VK_IMAGE_ASPECT_DEPTH_BIT
|
1263 VK_IMAGE_ASPECT_STENCIL_BIT
|
1264 VK_IMAGE_ASPECT_PLANE_0_BIT
))
1266 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_1_BIT
)
1268 if (aspect_mask
& VK_IMAGE_ASPECT_PLANE_2_BIT
)
1271 if ((aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) != 0 &&
1272 (aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) != 0)
1279 anv_CreateImageView(VkDevice _device
,
1280 const VkImageViewCreateInfo
*pCreateInfo
,
1281 const VkAllocationCallbacks
*pAllocator
,
1284 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1285 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1286 struct anv_image_view
*iview
;
1288 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1289 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1291 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1293 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1295 assert(range
->layerCount
> 0);
1296 assert(range
->baseMipLevel
< image
->levels
);
1298 const VkImageViewUsageCreateInfo
*usage_info
=
1299 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO
);
1300 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1301 /* View usage should be a subset of image usage */
1302 assert((view_usage
& ~image
->usage
) == 0);
1303 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1304 VK_IMAGE_USAGE_STORAGE_BIT
|
1305 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1306 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1307 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1309 switch (image
->type
) {
1311 unreachable("bad VkImageType");
1312 case VK_IMAGE_TYPE_1D
:
1313 case VK_IMAGE_TYPE_2D
:
1314 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1316 case VK_IMAGE_TYPE_3D
:
1317 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1318 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1322 /* First expand aspects to the image's ones (for example
1323 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1324 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1325 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1326 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1328 VkImageAspectFlags expanded_aspects
=
1329 anv_image_expand_aspects(image
, range
->aspectMask
);
1331 iview
->image
= image
;
1333 /* Remap the expanded aspects for the image view. For example if only
1334 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1335 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1336 * the image view, it only has a single plane.
1338 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1339 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1340 iview
->vk_format
= pCreateInfo
->format
;
1342 iview
->extent
= (VkExtent3D
) {
1343 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1344 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1345 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1348 /* Now go through the underlying image selected planes (computed in
1349 * expanded_aspects) and map them to planes in the image view.
1351 uint32_t iaspect_bit
, vplane
= 0;
1352 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1354 anv_image_aspect_to_plane(image
->aspects
, 1UL << iaspect_bit
);
1355 VkImageAspectFlags vplane_aspect
=
1356 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1357 struct anv_format_plane format
=
1358 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1359 vplane_aspect
, image
->tiling
);
1361 iview
->planes
[vplane
].image_plane
= iplane
;
1363 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1364 .format
= format
.isl_format
,
1365 .base_level
= range
->baseMipLevel
,
1366 .levels
= anv_get_levelCount(image
, range
),
1367 .base_array_layer
= range
->baseArrayLayer
,
1368 .array_len
= anv_get_layerCount(image
, range
),
1370 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1371 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1372 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1373 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1374 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1375 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1376 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1377 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1381 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1382 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1383 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1386 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1387 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1388 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1390 iview
->planes
[vplane
].isl
.usage
= 0;
1393 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1394 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1395 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1396 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1397 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1399 enum isl_aux_usage general_aux_usage
=
1400 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1401 VK_IMAGE_LAYOUT_GENERAL
);
1402 enum isl_aux_usage optimal_aux_usage
=
1403 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1404 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1406 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1407 &iview
->planes
[vplane
].isl
,
1408 ISL_SURF_USAGE_TEXTURE_BIT
,
1409 optimal_aux_usage
, NULL
,
1410 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1411 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1414 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1415 &iview
->planes
[vplane
].isl
,
1416 ISL_SURF_USAGE_TEXTURE_BIT
,
1417 general_aux_usage
, NULL
,
1419 &iview
->planes
[vplane
].general_sampler_surface_state
,
1423 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1424 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1425 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1426 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1428 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1429 &iview
->planes
[vplane
].isl
,
1430 ISL_SURF_USAGE_STORAGE_BIT
,
1431 ISL_AUX_USAGE_NONE
, NULL
,
1433 &iview
->planes
[vplane
].storage_surface_state
,
1434 &iview
->planes
[vplane
].storage_image_param
);
1436 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1437 &iview
->planes
[vplane
].isl
,
1438 ISL_SURF_USAGE_STORAGE_BIT
,
1439 ISL_AUX_USAGE_NONE
, NULL
,
1440 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1441 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1448 *pView
= anv_image_view_to_handle(iview
);
1454 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1455 const VkAllocationCallbacks
*pAllocator
)
1457 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1458 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1463 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1464 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1465 anv_state_pool_free(&device
->surface_state_pool
,
1466 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1469 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1470 anv_state_pool_free(&device
->surface_state_pool
,
1471 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1474 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1475 anv_state_pool_free(&device
->surface_state_pool
,
1476 iview
->planes
[plane
].storage_surface_state
.state
);
1479 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1480 anv_state_pool_free(&device
->surface_state_pool
,
1481 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1485 vk_free2(&device
->alloc
, pAllocator
, iview
);
1490 anv_CreateBufferView(VkDevice _device
,
1491 const VkBufferViewCreateInfo
*pCreateInfo
,
1492 const VkAllocationCallbacks
*pAllocator
,
1493 VkBufferView
*pView
)
1495 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1496 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1497 struct anv_buffer_view
*view
;
1499 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1500 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1502 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1504 /* TODO: Handle the format swizzle? */
1506 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1507 VK_IMAGE_ASPECT_COLOR_BIT
,
1508 VK_IMAGE_TILING_LINEAR
);
1509 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1510 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1511 pCreateInfo
->range
);
1512 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1514 view
->address
= anv_address_add(buffer
->address
, pCreateInfo
->offset
);
1516 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1517 view
->surface_state
= alloc_surface_state(device
);
1519 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1521 view
->address
, view
->range
, format_bs
);
1523 view
->surface_state
= (struct anv_state
){ 0 };
1526 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1527 view
->storage_surface_state
= alloc_surface_state(device
);
1528 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1530 enum isl_format storage_format
=
1531 isl_has_matching_typed_storage_image_format(&device
->info
,
1533 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1536 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1538 view
->address
, view
->range
,
1539 (storage_format
== ISL_FORMAT_RAW
? 1 :
1540 isl_format_get_layout(storage_format
)->bpb
/ 8));
1542 /* Write-only accesses should use the original format. */
1543 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1545 view
->address
, view
->range
,
1546 isl_format_get_layout(view
->format
)->bpb
/ 8);
1548 isl_buffer_fill_image_param(&device
->isl_dev
,
1549 &view
->storage_image_param
,
1550 view
->format
, view
->range
);
1552 view
->storage_surface_state
= (struct anv_state
){ 0 };
1553 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1556 *pView
= anv_buffer_view_to_handle(view
);
1562 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1563 const VkAllocationCallbacks
*pAllocator
)
1565 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1566 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1571 if (view
->surface_state
.alloc_size
> 0)
1572 anv_state_pool_free(&device
->surface_state_pool
,
1573 view
->surface_state
);
1575 if (view
->storage_surface_state
.alloc_size
> 0)
1576 anv_state_pool_free(&device
->surface_state_pool
,
1577 view
->storage_surface_state
);
1579 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1580 anv_state_pool_free(&device
->surface_state_pool
,
1581 view
->writeonly_storage_surface_state
);
1583 vk_free2(&device
->alloc
, pAllocator
, view
);
1586 const struct anv_surface
*
1587 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1588 VkImageAspectFlags aspect_mask
)
1590 VkImageAspectFlags sanitized_mask
;
1592 switch (aspect_mask
) {
1593 case VK_IMAGE_ASPECT_COLOR_BIT
:
1594 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1595 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1597 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1598 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1599 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1601 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1602 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1603 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1605 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1606 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1607 * combined depth stencil formats. Specifically, it states:
1609 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1610 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1612 * Image views with both depth and stencil aspects are only valid for
1613 * render target attachments, in which case
1614 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1615 * stencil surfaces from the underlying surface.
1617 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1618 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1620 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1621 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1624 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1625 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1626 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT
;
1628 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1629 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1630 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT
;
1632 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1633 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1634 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT
;
1637 unreachable("image does not have aspect");
1641 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1642 return &image
->planes
[plane
].surface
;