anv: Add a layout_to_aux_state helper
[mesa.git] / src / intel / vulkan / anv_image.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26 #include <string.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29 #include <sys/mman.h>
30 #include "drm-uapi/drm_fourcc.h"
31
32 #include "anv_private.h"
33 #include "util/debug.h"
34 #include "vk_util.h"
35 #include "util/u_math.h"
36
37 #include "common/gen_aux_map.h"
38
39 #include "vk_format_info.h"
40
41 static isl_surf_usage_flags_t
42 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
43 VkImageUsageFlags vk_usage,
44 isl_surf_usage_flags_t isl_extra_usage,
45 VkImageAspectFlagBits aspect)
46 {
47 isl_surf_usage_flags_t isl_usage = isl_extra_usage;
48
49 if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
50 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
51
52 if (vk_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)
53 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
54
55 if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
56 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
57
58 if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
59 isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
60
61 /* Even if we're only using it for transfer operations, clears to depth and
62 * stencil images happen as depth and stencil so they need the right ISL
63 * usage bits or else things will fall apart.
64 */
65 switch (aspect) {
66 case VK_IMAGE_ASPECT_DEPTH_BIT:
67 isl_usage |= ISL_SURF_USAGE_DEPTH_BIT;
68 break;
69 case VK_IMAGE_ASPECT_STENCIL_BIT:
70 isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
71 break;
72 case VK_IMAGE_ASPECT_COLOR_BIT:
73 case VK_IMAGE_ASPECT_PLANE_0_BIT:
74 case VK_IMAGE_ASPECT_PLANE_1_BIT:
75 case VK_IMAGE_ASPECT_PLANE_2_BIT:
76 break;
77 default:
78 unreachable("bad VkImageAspect");
79 }
80
81 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_SRC_BIT) {
82 /* blorp implements transfers by sampling from the source image. */
83 isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
84 }
85
86 if (vk_usage & VK_IMAGE_USAGE_TRANSFER_DST_BIT &&
87 aspect == VK_IMAGE_ASPECT_COLOR_BIT) {
88 /* blorp implements transfers by rendering into the destination image.
89 * Only request this with color images, as we deal with depth/stencil
90 * formats differently. */
91 isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
92 }
93
94 return isl_usage;
95 }
96
97 static isl_tiling_flags_t
98 choose_isl_tiling_flags(const struct anv_image_create_info *anv_info,
99 const struct isl_drm_modifier_info *isl_mod_info,
100 bool legacy_scanout)
101 {
102 const VkImageCreateInfo *base_info = anv_info->vk_info;
103 isl_tiling_flags_t flags = 0;
104
105 switch (base_info->tiling) {
106 default:
107 unreachable("bad VkImageTiling");
108 case VK_IMAGE_TILING_OPTIMAL:
109 flags = ISL_TILING_ANY_MASK;
110 break;
111 case VK_IMAGE_TILING_LINEAR:
112 flags = ISL_TILING_LINEAR_BIT;
113 break;
114 case VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT:
115 assert(isl_mod_info);
116 flags = 1 << isl_mod_info->tiling;
117 }
118
119 if (anv_info->isl_tiling_flags)
120 flags &= anv_info->isl_tiling_flags;
121
122 if (legacy_scanout)
123 flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT;
124
125 assert(flags);
126
127 return flags;
128 }
129
130 static struct anv_surface *
131 get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
132 {
133 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
134 return &image->planes[plane].surface;
135 }
136
137 static void
138 add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
139 {
140 assert(surf->isl.size_B > 0); /* isl surface must be initialized */
141
142 if (image->disjoint) {
143 surf->offset = align_u32(image->planes[plane].size,
144 surf->isl.alignment_B);
145 /* Plane offset is always 0 when it's disjoint. */
146 } else {
147 surf->offset = align_u32(image->size, surf->isl.alignment_B);
148 /* Determine plane's offset only once when the first surface is added. */
149 if (image->planes[plane].size == 0)
150 image->planes[plane].offset = image->size;
151 }
152
153 image->size = surf->offset + surf->isl.size_B;
154 image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
155
156 image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
157 image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
158 surf->isl.alignment_B);
159 }
160
161
162 bool
163 anv_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
164 VkImageCreateFlags create_flags,
165 VkFormat vk_format,
166 VkImageTiling vk_tiling,
167 const VkImageFormatListCreateInfoKHR *fmt_list)
168 {
169 enum isl_format format =
170 anv_get_isl_format(devinfo, vk_format,
171 VK_IMAGE_ASPECT_COLOR_BIT, vk_tiling);
172
173 if (!isl_format_supports_ccs_e(devinfo, format))
174 return false;
175
176 if (!(create_flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT))
177 return true;
178
179 if (!fmt_list || fmt_list->viewFormatCount == 0)
180 return false;
181
182 for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) {
183 enum isl_format view_format =
184 anv_get_isl_format(devinfo, fmt_list->pViewFormats[i],
185 VK_IMAGE_ASPECT_COLOR_BIT, vk_tiling);
186
187 if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format))
188 return false;
189 }
190
191 return true;
192 }
193
194 /**
195 * For color images that have an auxiliary surface, request allocation for an
196 * additional buffer that mainly stores fast-clear values. Use of this buffer
197 * allows us to access the image's subresources while being aware of their
198 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
199 * which a fast clear has occurred).
200 *
201 * In order to avoid having multiple clear colors for a single plane of an
202 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
203 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
204 * 2018), there were no known applications which would benefit from fast-
205 * clearing more than just the first slice.
206 *
207 * The fast clear portion of the image is laid out in the following order:
208 *
209 * * 1 or 4 dwords (depending on hardware generation) for the clear color
210 * * 1 dword for the anv_fast_clear_type of the clear color
211 * * On gen9+, 1 dword per level and layer of the image (3D levels count
212 * multiple layers) in level-major order for compression state.
213 *
214 * For the purpose of discoverability, the algorithm used to manage
215 * compression and fast-clears is described here:
216 *
217 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
218 * all of the values in the fast clear portion of the image are initialized
219 * to default values.
220 *
221 * * On fast-clear, the clear value is written into surface state and also
222 * into the buffer and the fast clear type is set appropriately. Both
223 * setting the fast-clear value in the buffer and setting the fast-clear
224 * type happen from the GPU using MI commands.
225 *
226 * * Whenever a render or blorp operation is performed with CCS_E, we call
227 * genX(cmd_buffer_mark_image_written) to set the compression state to
228 * true (which is represented by UINT32_MAX).
229 *
230 * * On pipeline barrier transitions, the worst-case transition is computed
231 * from the image layouts. The command streamer inspects the fast clear
232 * type and compression state dwords and constructs a predicate. The
233 * worst-case resolve is performed with the given predicate and the fast
234 * clear and compression state is set accordingly.
235 *
236 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
237 * details on exactly what is allowed in what layouts.
238 *
239 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
240 * In order to deal with this, we have to do some clear color management.
241 *
242 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
243 * value from the buffer into the surface state with MI commands.
244 *
245 * * For any blorp operations, we pass the address to the clear value into
246 * blorp and it knows to copy the clear color.
247 */
248 static void
249 add_aux_state_tracking_buffer(struct anv_image *image,
250 uint32_t plane,
251 const struct anv_device *device)
252 {
253 assert(image && device);
254 assert(image->planes[plane].aux_surface.isl.size_B > 0 &&
255 image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
256
257 /* Compressed images must be tiled and therefore everything should be 4K
258 * aligned. The CCS has the same alignment requirements. This is good
259 * because we need at least dword-alignment for MI_LOAD/STORE operations.
260 */
261 assert(image->alignment % 4 == 0);
262 assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0);
263
264 /* This buffer should be at the very end of the plane. */
265 if (image->disjoint) {
266 assert(image->planes[plane].size ==
267 (image->planes[plane].offset + image->planes[plane].size));
268 } else {
269 assert(image->size ==
270 (image->planes[plane].offset + image->planes[plane].size));
271 }
272
273 const unsigned clear_color_state_size = device->info.gen >= 10 ?
274 device->isl_dev.ss.clear_color_state_size :
275 device->isl_dev.ss.clear_value_size;
276
277 /* Clear color and fast clear type */
278 unsigned state_size = clear_color_state_size + 4;
279
280 /* We only need to track compression on CCS_E surfaces. */
281 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
282 if (image->type == VK_IMAGE_TYPE_3D) {
283 for (uint32_t l = 0; l < image->levels; l++)
284 state_size += anv_minify(image->extent.depth, l) * 4;
285 } else {
286 state_size += image->levels * image->array_size * 4;
287 }
288 }
289
290 /* Add some padding to make sure the fast clear color state buffer starts at
291 * a 4K alignment. We believe that 256B might be enough, but due to lack of
292 * testing we will leave this as 4K for now.
293 */
294 image->planes[plane].size = ALIGN(image->planes[plane].size, 4096);
295 image->size = ALIGN(image->size, 4096);
296
297 assert(image->planes[plane].offset % 4096 == 0);
298
299 image->planes[plane].fast_clear_state_offset =
300 image->planes[plane].offset + image->planes[plane].size;
301
302 image->planes[plane].size += state_size;
303 image->size += state_size;
304 }
305
306 /**
307 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
308 * image's memory requirements (that is, the image's size and alignment).
309 */
310 static VkResult
311 make_surface(struct anv_device *dev,
312 struct anv_image *image,
313 uint32_t stride,
314 isl_tiling_flags_t tiling_flags,
315 isl_surf_usage_flags_t isl_extra_usage_flags,
316 VkImageAspectFlagBits aspect)
317 {
318 bool ok;
319
320 static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
321 [VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
322 [VK_IMAGE_TYPE_2D] = ISL_SURF_DIM_2D,
323 [VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
324 };
325
326 image->extent = anv_sanitize_image_extent(image->type, image->extent);
327
328 const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect);
329 const struct anv_format_plane plane_format =
330 anv_get_format_plane(&dev->info, image->vk_format, aspect, image->tiling);
331 struct anv_surface *anv_surf = &image->planes[plane].surface;
332
333 const isl_surf_usage_flags_t usage =
334 choose_isl_surf_usage(image->create_flags, image->usage,
335 isl_extra_usage_flags, aspect);
336
337 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
338 * fall back to linear on Broadwell and earlier because we aren't
339 * guaranteed that we can handle offsets correctly. On Sky Lake, the
340 * horizontal and vertical alignments are sufficiently high that we can
341 * just use RENDER_SURFACE_STATE::X/Y Offset.
342 */
343 bool needs_shadow = false;
344 isl_surf_usage_flags_t shadow_usage = 0;
345 if (dev->info.gen <= 8 &&
346 (image->create_flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
347 image->tiling == VK_IMAGE_TILING_OPTIMAL) {
348 assert(isl_format_is_compressed(plane_format.isl_format));
349 tiling_flags = ISL_TILING_LINEAR_BIT;
350 needs_shadow = true;
351 shadow_usage = ISL_SURF_USAGE_TEXTURE_BIT |
352 (usage & ISL_SURF_USAGE_CUBE_BIT);
353 }
354
355 if (dev->info.gen <= 7 &&
356 aspect == VK_IMAGE_ASPECT_STENCIL_BIT &&
357 (image->stencil_usage & VK_IMAGE_USAGE_SAMPLED_BIT)) {
358 needs_shadow = true;
359 shadow_usage = ISL_SURF_USAGE_TEXTURE_BIT |
360 (usage & ISL_SURF_USAGE_CUBE_BIT);
361 }
362
363 ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
364 .dim = vk_to_isl_surf_dim[image->type],
365 .format = plane_format.isl_format,
366 .width = image->extent.width / plane_format.denominator_scales[0],
367 .height = image->extent.height / plane_format.denominator_scales[1],
368 .depth = image->extent.depth,
369 .levels = image->levels,
370 .array_len = image->array_size,
371 .samples = image->samples,
372 .min_alignment_B = 0,
373 .row_pitch_B = stride,
374 .usage = usage,
375 .tiling_flags = tiling_flags);
376
377 if (!ok)
378 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
379
380 image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
381
382 add_surface(image, anv_surf, plane);
383
384 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
385 * create an identical tiled shadow surface for use while texturing so we
386 * don't get garbage performance. If we're on gen7 and the image contains
387 * stencil, then we need to maintain a shadow because we can't texture from
388 * W-tiled images.
389 */
390 if (needs_shadow) {
391 ok = isl_surf_init(&dev->isl_dev, &image->planes[plane].shadow_surface.isl,
392 .dim = vk_to_isl_surf_dim[image->type],
393 .format = plane_format.isl_format,
394 .width = image->extent.width,
395 .height = image->extent.height,
396 .depth = image->extent.depth,
397 .levels = image->levels,
398 .array_len = image->array_size,
399 .samples = image->samples,
400 .min_alignment_B = 0,
401 .row_pitch_B = stride,
402 .usage = shadow_usage,
403 .tiling_flags = ISL_TILING_ANY_MASK);
404
405 /* isl_surf_init() will fail only if provided invalid input. Invalid input
406 * is illegal in Vulkan.
407 */
408 assert(ok);
409
410 add_surface(image, &image->planes[plane].shadow_surface, plane);
411 }
412
413 /* Add a HiZ surface to a depth buffer that will be used for rendering.
414 */
415 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
416 /* We don't advertise that depth buffers could be used as storage
417 * images.
418 */
419 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
420
421 /* Allow the user to control HiZ enabling. Disable by default on gen7
422 * because resolves are not currently implemented pre-BDW.
423 */
424 if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
425 /* It will never be used as an attachment, HiZ is pointless. */
426 } else if (dev->info.gen == 7) {
427 anv_perf_warn(dev, image, "Implement gen7 HiZ");
428 } else if (image->levels > 1) {
429 anv_perf_warn(dev, image, "Enable multi-LOD HiZ");
430 } else if (image->array_size > 1) {
431 anv_perf_warn(dev, image,
432 "Implement multi-arrayLayer HiZ clears and resolves");
433 } else if (dev->info.gen == 8 && image->samples > 1) {
434 anv_perf_warn(dev, image, "Enable gen8 multisampled HiZ");
435 } else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
436 assert(image->planes[plane].aux_surface.isl.size_B == 0);
437 ok = isl_surf_get_hiz_surf(&dev->isl_dev,
438 &image->planes[plane].surface.isl,
439 &image->planes[plane].aux_surface.isl);
440 assert(ok);
441 add_surface(image, &image->planes[plane].aux_surface, plane);
442 image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
443 }
444 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples == 1) {
445 /* TODO: Disallow compression with :
446 *
447 * 1) non multiplanar images (We appear to hit a sampler bug with
448 * CCS & R16G16 format. Putting the clear state a page/4096bytes
449 * further fixes the issue).
450 *
451 * 2) alias images, because they might be aliases of images
452 * described in 1)
453 *
454 * 3) compression disabled by debug
455 */
456 const bool allow_compression =
457 image->n_planes == 1 &&
458 (image->create_flags & VK_IMAGE_CREATE_ALIAS_BIT) == 0 &&
459 likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
460
461 if (allow_compression) {
462 assert(image->planes[plane].aux_surface.isl.size_B == 0);
463 ok = isl_surf_get_ccs_surf(&dev->isl_dev,
464 &image->planes[plane].surface.isl,
465 &image->planes[plane].aux_surface.isl,
466 NULL, 0);
467 if (ok) {
468
469 /* Disable CCS when it is not useful (i.e., when you can't render
470 * to the image with CCS enabled).
471 */
472 if (!isl_format_supports_rendering(&dev->info,
473 plane_format.isl_format)) {
474 /* While it may be technically possible to enable CCS for this
475 * image, we currently don't have things hooked up to get it
476 * working.
477 */
478 anv_perf_warn(dev, image,
479 "This image format doesn't support rendering. "
480 "Not allocating an CCS buffer.");
481 image->planes[plane].aux_surface.isl.size_B = 0;
482 return VK_SUCCESS;
483 }
484
485 /* For images created without MUTABLE_FORMAT_BIT set, we know that
486 * they will always be used with the original format. In
487 * particular, they will always be used with a format that
488 * supports color compression. If it's never used as a storage
489 * image, then it will only be used through the sampler or the as
490 * a render target. This means that it's safe to just leave
491 * compression on at all times for these formats.
492 */
493 if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
494 image->ccs_e_compatible) {
495 image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E;
496 } else if (dev->info.gen >= 12) {
497 anv_perf_warn(dev, image,
498 "The CCS_D aux mode is not yet handled on "
499 "Gen12+. Not allocating a CCS buffer.");
500 image->planes[plane].aux_surface.isl.size_B = 0;
501 return VK_SUCCESS;
502 }
503
504 add_surface(image, &image->planes[plane].aux_surface, plane);
505 add_aux_state_tracking_buffer(image, plane, dev);
506 }
507 }
508 } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples > 1) {
509 assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
510 assert(image->planes[plane].aux_surface.isl.size_B == 0);
511 ok = isl_surf_get_mcs_surf(&dev->isl_dev,
512 &image->planes[plane].surface.isl,
513 &image->planes[plane].aux_surface.isl);
514 if (ok) {
515 add_surface(image, &image->planes[plane].aux_surface, plane);
516 add_aux_state_tracking_buffer(image, plane, dev);
517 image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
518 }
519 }
520
521 assert((image->planes[plane].offset + image->planes[plane].size) == image->size);
522
523 /* Upper bound of the last surface should be smaller than the plane's
524 * size.
525 */
526 assert((MAX2(image->planes[plane].surface.offset,
527 image->planes[plane].aux_surface.offset) +
528 (image->planes[plane].aux_surface.isl.size_B > 0 ?
529 image->planes[plane].aux_surface.isl.size_B :
530 image->planes[plane].surface.isl.size_B)) <=
531 (image->planes[plane].offset + image->planes[plane].size));
532
533 if (image->planes[plane].aux_surface.isl.size_B) {
534 /* assert(image->planes[plane].fast_clear_state_offset == */
535 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
536 assert(image->planes[plane].fast_clear_state_offset <
537 (image->planes[plane].offset + image->planes[plane].size));
538 }
539
540 return VK_SUCCESS;
541 }
542
543 static uint32_t
544 score_drm_format_mod(uint64_t modifier)
545 {
546 switch (modifier) {
547 case DRM_FORMAT_MOD_LINEAR: return 1;
548 case I915_FORMAT_MOD_X_TILED: return 2;
549 case I915_FORMAT_MOD_Y_TILED: return 3;
550 case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
551 default: unreachable("bad DRM format modifier");
552 }
553 }
554
555 static const struct isl_drm_modifier_info *
556 choose_drm_format_mod(const struct anv_physical_device *device,
557 uint32_t modifier_count, const uint64_t *modifiers)
558 {
559 uint64_t best_mod = UINT64_MAX;
560 uint32_t best_score = 0;
561
562 for (uint32_t i = 0; i < modifier_count; ++i) {
563 uint32_t score = score_drm_format_mod(modifiers[i]);
564 if (score > best_score) {
565 best_mod = modifiers[i];
566 best_score = score;
567 }
568 }
569
570 if (best_score > 0)
571 return isl_drm_modifier_get_info(best_mod);
572 else
573 return NULL;
574 }
575
576 VkResult
577 anv_image_create(VkDevice _device,
578 const struct anv_image_create_info *create_info,
579 const VkAllocationCallbacks* alloc,
580 VkImage *pImage)
581 {
582 ANV_FROM_HANDLE(anv_device, device, _device);
583 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
584 const struct isl_drm_modifier_info *isl_mod_info = NULL;
585 struct anv_image *image = NULL;
586 VkResult r;
587
588 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
589
590 const struct wsi_image_create_info *wsi_info =
591 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
592
593 if (pCreateInfo->tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT) {
594 const VkImageDrmFormatModifierListCreateInfoEXT *mod_info =
595 vk_find_struct_const(pCreateInfo->pNext,
596 IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT);
597 isl_mod_info = choose_drm_format_mod(device->physical,
598 mod_info->drmFormatModifierCount,
599 mod_info->pDrmFormatModifiers);
600 assert(isl_mod_info);
601 }
602
603 anv_assert(pCreateInfo->mipLevels > 0);
604 anv_assert(pCreateInfo->arrayLayers > 0);
605 anv_assert(pCreateInfo->samples > 0);
606 anv_assert(pCreateInfo->extent.width > 0);
607 anv_assert(pCreateInfo->extent.height > 0);
608 anv_assert(pCreateInfo->extent.depth > 0);
609
610 image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
611 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
612 if (!image)
613 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
614
615 image->type = pCreateInfo->imageType;
616 image->extent = pCreateInfo->extent;
617 image->vk_format = pCreateInfo->format;
618 image->format = anv_get_format(pCreateInfo->format);
619 image->aspects = vk_format_aspects(image->vk_format);
620 image->levels = pCreateInfo->mipLevels;
621 image->array_size = pCreateInfo->arrayLayers;
622 image->samples = pCreateInfo->samples;
623 image->usage = pCreateInfo->usage;
624 image->create_flags = pCreateInfo->flags;
625 image->tiling = pCreateInfo->tiling;
626 image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT;
627 image->needs_set_tiling = wsi_info && wsi_info->scanout;
628 image->drm_format_mod = isl_mod_info ? isl_mod_info->modifier :
629 DRM_FORMAT_MOD_INVALID;
630
631 if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
632 image->stencil_usage = pCreateInfo->usage;
633 const VkImageStencilUsageCreateInfoEXT *stencil_usage_info =
634 vk_find_struct_const(pCreateInfo->pNext,
635 IMAGE_STENCIL_USAGE_CREATE_INFO_EXT);
636 if (stencil_usage_info)
637 image->stencil_usage = stencil_usage_info->stencilUsage;
638 }
639
640 /* In case of external format, We don't know format yet,
641 * so skip the rest for now.
642 */
643 if (create_info->external_format) {
644 image->external_format = true;
645 *pImage = anv_image_to_handle(image);
646 return VK_SUCCESS;
647 }
648
649 const struct anv_format *format = anv_get_format(image->vk_format);
650 assert(format != NULL);
651
652 const isl_tiling_flags_t isl_tiling_flags =
653 choose_isl_tiling_flags(create_info, isl_mod_info,
654 image->needs_set_tiling);
655
656 image->n_planes = format->n_planes;
657
658 const VkImageFormatListCreateInfoKHR *fmt_list =
659 vk_find_struct_const(pCreateInfo->pNext,
660 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
661
662 image->ccs_e_compatible =
663 anv_formats_ccs_e_compatible(&device->info, image->create_flags,
664 image->vk_format, image->tiling, fmt_list);
665
666 uint32_t b;
667 for_each_bit(b, image->aspects) {
668 r = make_surface(device, image, create_info->stride, isl_tiling_flags,
669 create_info->isl_extra_usage_flags, (1 << b));
670 if (r != VK_SUCCESS)
671 goto fail;
672 }
673
674 *pImage = anv_image_to_handle(image);
675
676 return VK_SUCCESS;
677
678 fail:
679 if (image)
680 vk_free2(&device->alloc, alloc, image);
681
682 return r;
683 }
684
685 static struct anv_image *
686 anv_swapchain_get_image(VkSwapchainKHR swapchain,
687 uint32_t index)
688 {
689 uint32_t n_images = index + 1;
690 VkImage *images = malloc(sizeof(*images) * n_images);
691 VkResult result = wsi_common_get_images(swapchain, &n_images, images);
692
693 if (result != VK_SUCCESS && result != VK_INCOMPLETE) {
694 free(images);
695 return NULL;
696 }
697
698 ANV_FROM_HANDLE(anv_image, image, images[index]);
699 free(images);
700
701 return image;
702 }
703
704 static VkResult
705 anv_image_from_swapchain(VkDevice device,
706 const VkImageCreateInfo *pCreateInfo,
707 const VkImageSwapchainCreateInfoKHR *swapchain_info,
708 const VkAllocationCallbacks *pAllocator,
709 VkImage *pImage)
710 {
711 struct anv_image *swapchain_image = anv_swapchain_get_image(swapchain_info->swapchain, 0);
712 assert(swapchain_image);
713
714 assert(swapchain_image->type == pCreateInfo->imageType);
715 assert(swapchain_image->vk_format == pCreateInfo->format);
716 assert(swapchain_image->extent.width == pCreateInfo->extent.width);
717 assert(swapchain_image->extent.height == pCreateInfo->extent.height);
718 assert(swapchain_image->extent.depth == pCreateInfo->extent.depth);
719 assert(swapchain_image->array_size == pCreateInfo->arrayLayers);
720 /* Color attachment is added by the wsi code. */
721 assert(swapchain_image->usage == (pCreateInfo->usage | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT));
722
723 VkImageCreateInfo local_create_info;
724 local_create_info = *pCreateInfo;
725 local_create_info.pNext = NULL;
726 /* The following parameters are implictly selected by the wsi code. */
727 local_create_info.tiling = VK_IMAGE_TILING_OPTIMAL;
728 local_create_info.samples = VK_SAMPLE_COUNT_1_BIT;
729 local_create_info.usage |= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
730
731 /* If the image has a particular modifier, specify that modifier. */
732 VkImageDrmFormatModifierListCreateInfoEXT local_modifier_info = {
733 .sType = VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT,
734 .drmFormatModifierCount = 1,
735 .pDrmFormatModifiers = &swapchain_image->drm_format_mod,
736 };
737 if (swapchain_image->drm_format_mod != DRM_FORMAT_MOD_INVALID)
738 __vk_append_struct(&local_create_info, &local_modifier_info);
739
740 return anv_image_create(device,
741 &(struct anv_image_create_info) {
742 .vk_info = &local_create_info,
743 .external_format = swapchain_image->external_format,
744 },
745 pAllocator,
746 pImage);
747 }
748
749 VkResult
750 anv_CreateImage(VkDevice device,
751 const VkImageCreateInfo *pCreateInfo,
752 const VkAllocationCallbacks *pAllocator,
753 VkImage *pImage)
754 {
755 const VkExternalMemoryImageCreateInfo *create_info =
756 vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_MEMORY_IMAGE_CREATE_INFO);
757
758 if (create_info && (create_info->handleTypes &
759 VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))
760 return anv_image_from_external(device, pCreateInfo, create_info,
761 pAllocator, pImage);
762
763 bool use_external_format = false;
764 const VkExternalFormatANDROID *ext_format =
765 vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_FORMAT_ANDROID);
766
767 /* "If externalFormat is zero, the effect is as if the
768 * VkExternalFormatANDROID structure was not present. Otherwise, the image
769 * will have the specified external format."
770 */
771 if (ext_format && ext_format->externalFormat != 0)
772 use_external_format = true;
773
774 const VkNativeBufferANDROID *gralloc_info =
775 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
776 if (gralloc_info)
777 return anv_image_from_gralloc(device, pCreateInfo, gralloc_info,
778 pAllocator, pImage);
779
780 const VkImageSwapchainCreateInfoKHR *swapchain_info =
781 vk_find_struct_const(pCreateInfo->pNext, IMAGE_SWAPCHAIN_CREATE_INFO_KHR);
782 if (swapchain_info && swapchain_info->swapchain != VK_NULL_HANDLE)
783 return anv_image_from_swapchain(device, pCreateInfo, swapchain_info,
784 pAllocator, pImage);
785
786 return anv_image_create(device,
787 &(struct anv_image_create_info) {
788 .vk_info = pCreateInfo,
789 .external_format = use_external_format,
790 },
791 pAllocator,
792 pImage);
793 }
794
795 void
796 anv_DestroyImage(VkDevice _device, VkImage _image,
797 const VkAllocationCallbacks *pAllocator)
798 {
799 ANV_FROM_HANDLE(anv_device, device, _device);
800 ANV_FROM_HANDLE(anv_image, image, _image);
801
802 if (!image)
803 return;
804
805 for (uint32_t p = 0; p < image->n_planes; ++p) {
806 if (anv_image_plane_uses_aux_map(device, image, p) &&
807 image->planes[p].address.bo) {
808 gen_aux_map_unmap_range(device->aux_map_ctx,
809 image->planes[p].aux_map_surface_address,
810 image->planes[p].surface.isl.size_B);
811 }
812 if (image->planes[p].bo_is_owned) {
813 assert(image->planes[p].address.bo != NULL);
814 anv_device_release_bo(device, image->planes[p].address.bo);
815 }
816 }
817
818 vk_free2(&device->alloc, pAllocator, image);
819 }
820
821 static void anv_image_bind_memory_plane(struct anv_device *device,
822 struct anv_image *image,
823 uint32_t plane,
824 struct anv_device_memory *memory,
825 uint32_t memory_offset)
826 {
827 assert(!image->planes[plane].bo_is_owned);
828
829 if (!memory) {
830 if (anv_image_plane_uses_aux_map(device, image, plane) &&
831 image->planes[plane].address.bo) {
832 gen_aux_map_unmap_range(device->aux_map_ctx,
833 image->planes[plane].aux_map_surface_address,
834 image->planes[plane].surface.isl.size_B);
835 }
836 image->planes[plane].address = ANV_NULL_ADDRESS;
837 return;
838 }
839
840 image->planes[plane].address = (struct anv_address) {
841 .bo = memory->bo,
842 .offset = memory_offset,
843 };
844
845 if (anv_image_plane_uses_aux_map(device, image, plane)) {
846 image->planes[plane].aux_map_surface_address =
847 anv_address_physical(
848 anv_address_add(image->planes[plane].address,
849 image->planes[plane].surface.offset));
850
851 gen_aux_map_add_image(device->aux_map_ctx,
852 &image->planes[plane].surface.isl,
853 image->planes[plane].aux_map_surface_address,
854 anv_address_physical(
855 anv_address_add(image->planes[plane].address,
856 image->planes[plane].aux_surface.offset)));
857 }
858 }
859
860 /* We are binding AHardwareBuffer. Get a description, resolve the
861 * format and prepare anv_image properly.
862 */
863 static void
864 resolve_ahw_image(struct anv_device *device,
865 struct anv_image *image,
866 struct anv_device_memory *mem)
867 {
868 #if defined(ANDROID) && ANDROID_API_LEVEL >= 26
869 assert(mem->ahw);
870 AHardwareBuffer_Desc desc;
871 AHardwareBuffer_describe(mem->ahw, &desc);
872
873 /* Check tiling. */
874 int i915_tiling = anv_gem_get_tiling(device, mem->bo->gem_handle);
875 VkImageTiling vk_tiling;
876 isl_tiling_flags_t isl_tiling_flags = 0;
877
878 switch (i915_tiling) {
879 case I915_TILING_NONE:
880 vk_tiling = VK_IMAGE_TILING_LINEAR;
881 isl_tiling_flags = ISL_TILING_LINEAR_BIT;
882 break;
883 case I915_TILING_X:
884 vk_tiling = VK_IMAGE_TILING_OPTIMAL;
885 isl_tiling_flags = ISL_TILING_X_BIT;
886 break;
887 case I915_TILING_Y:
888 vk_tiling = VK_IMAGE_TILING_OPTIMAL;
889 isl_tiling_flags = ISL_TILING_Y0_BIT;
890 break;
891 case -1:
892 default:
893 unreachable("Invalid tiling flags.");
894 }
895
896 assert(vk_tiling == VK_IMAGE_TILING_LINEAR ||
897 vk_tiling == VK_IMAGE_TILING_OPTIMAL);
898
899 /* Check format. */
900 VkFormat vk_format = vk_format_from_android(desc.format, desc.usage);
901 enum isl_format isl_fmt = anv_get_isl_format(&device->info,
902 vk_format,
903 VK_IMAGE_ASPECT_COLOR_BIT,
904 vk_tiling);
905 assert(isl_fmt != ISL_FORMAT_UNSUPPORTED);
906
907 /* Handle RGB(X)->RGBA fallback. */
908 switch (desc.format) {
909 case AHARDWAREBUFFER_FORMAT_R8G8B8_UNORM:
910 case AHARDWAREBUFFER_FORMAT_R8G8B8X8_UNORM:
911 if (isl_format_is_rgb(isl_fmt))
912 isl_fmt = isl_format_rgb_to_rgba(isl_fmt);
913 break;
914 }
915
916 /* Now we are able to fill anv_image fields properly and create
917 * isl_surface for it.
918 */
919 image->vk_format = vk_format;
920 image->format = anv_get_format(vk_format);
921 image->aspects = vk_format_aspects(image->vk_format);
922 image->n_planes = image->format->n_planes;
923 image->ccs_e_compatible = false;
924
925 uint32_t stride = desc.stride *
926 (isl_format_get_layout(isl_fmt)->bpb / 8);
927
928 uint32_t b;
929 for_each_bit(b, image->aspects) {
930 VkResult r = make_surface(device, image, stride, isl_tiling_flags,
931 ISL_SURF_USAGE_DISABLE_AUX_BIT, (1 << b));
932 assert(r == VK_SUCCESS);
933 }
934 #endif
935 }
936
937 VkResult anv_BindImageMemory(
938 VkDevice _device,
939 VkImage _image,
940 VkDeviceMemory _memory,
941 VkDeviceSize memoryOffset)
942 {
943 ANV_FROM_HANDLE(anv_device, device, _device);
944 ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
945 ANV_FROM_HANDLE(anv_image, image, _image);
946
947 if (mem->ahw)
948 resolve_ahw_image(device, image, mem);
949
950 uint32_t aspect_bit;
951 anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) {
952 uint32_t plane =
953 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
954 anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset);
955 }
956
957 return VK_SUCCESS;
958 }
959
960 VkResult anv_BindImageMemory2(
961 VkDevice _device,
962 uint32_t bindInfoCount,
963 const VkBindImageMemoryInfo* pBindInfos)
964 {
965 ANV_FROM_HANDLE(anv_device, device, _device);
966
967 for (uint32_t i = 0; i < bindInfoCount; i++) {
968 const VkBindImageMemoryInfo *bind_info = &pBindInfos[i];
969 ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory);
970 ANV_FROM_HANDLE(anv_image, image, bind_info->image);
971
972 /* Resolve will alter the image's aspects, do this first. */
973 if (mem && mem->ahw)
974 resolve_ahw_image(device, image, mem);
975
976 VkImageAspectFlags aspects = image->aspects;
977 vk_foreach_struct_const(s, bind_info->pNext) {
978 switch (s->sType) {
979 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO: {
980 const VkBindImagePlaneMemoryInfo *plane_info =
981 (const VkBindImagePlaneMemoryInfo *) s;
982
983 aspects = plane_info->planeAspect;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_SWAPCHAIN_INFO_KHR: {
987 const VkBindImageMemorySwapchainInfoKHR *swapchain_info =
988 (const VkBindImageMemorySwapchainInfoKHR *) s;
989 struct anv_image *swapchain_image =
990 anv_swapchain_get_image(swapchain_info->swapchain,
991 swapchain_info->imageIndex);
992 assert(swapchain_image);
993 assert(image->aspects == swapchain_image->aspects);
994 assert(mem == NULL);
995
996 uint32_t aspect_bit;
997 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
998 uint32_t plane =
999 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
1000 struct anv_device_memory mem = {
1001 .bo = swapchain_image->planes[plane].address.bo,
1002 };
1003 anv_image_bind_memory_plane(device, image, plane,
1004 &mem, bind_info->memoryOffset);
1005 }
1006 break;
1007 }
1008 default:
1009 anv_debug_ignored_stype(s->sType);
1010 break;
1011 }
1012 }
1013
1014 /* VkBindImageMemorySwapchainInfoKHR requires memory to be
1015 * VK_NULL_HANDLE. In such case, just carry one with the next bind
1016 * item.
1017 */
1018 if (!mem)
1019 continue;
1020
1021 uint32_t aspect_bit;
1022 anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
1023 uint32_t plane =
1024 anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
1025 anv_image_bind_memory_plane(device, image, plane,
1026 mem, bind_info->memoryOffset);
1027 }
1028 }
1029
1030 return VK_SUCCESS;
1031 }
1032
1033 void anv_GetImageSubresourceLayout(
1034 VkDevice device,
1035 VkImage _image,
1036 const VkImageSubresource* subresource,
1037 VkSubresourceLayout* layout)
1038 {
1039 ANV_FROM_HANDLE(anv_image, image, _image);
1040
1041 const struct anv_surface *surface;
1042 if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT &&
1043 image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
1044 isl_drm_modifier_has_aux(image->drm_format_mod))
1045 surface = &image->planes[0].aux_surface;
1046 else
1047 surface = get_surface(image, subresource->aspectMask);
1048
1049 assert(__builtin_popcount(subresource->aspectMask) == 1);
1050
1051 layout->offset = surface->offset;
1052 layout->rowPitch = surface->isl.row_pitch_B;
1053 layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
1054 layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
1055
1056 if (subresource->mipLevel > 0 || subresource->arrayLayer > 0) {
1057 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1058
1059 uint32_t offset_B;
1060 isl_surf_get_image_offset_B_tile_sa(&surface->isl,
1061 subresource->mipLevel,
1062 subresource->arrayLayer,
1063 0 /* logical_z_offset_px */,
1064 &offset_B, NULL, NULL);
1065 layout->offset += offset_B;
1066 layout->size = layout->rowPitch * anv_minify(image->extent.height,
1067 subresource->mipLevel);
1068 } else {
1069 layout->size = surface->isl.size_B;
1070 }
1071 }
1072
1073 VkResult anv_GetImageDrmFormatModifierPropertiesEXT(
1074 VkDevice device,
1075 VkImage _image,
1076 VkImageDrmFormatModifierPropertiesEXT* pProperties)
1077 {
1078 ANV_FROM_HANDLE(anv_image, image, _image);
1079
1080 assert(pProperties->sType ==
1081 VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT);
1082
1083 pProperties->drmFormatModifier = image->drm_format_mod;
1084
1085 return VK_SUCCESS;
1086 }
1087
1088 /**
1089 * This function returns the assumed isl_aux_state for a given VkImageLayout.
1090 * Because Vulkan image layouts don't map directly to isl_aux_state enums, the
1091 * returned enum is the assumed worst case.
1092 *
1093 * @param devinfo The device information of the Intel GPU.
1094 * @param image The image that may contain a collection of buffers.
1095 * @param aspect The aspect of the image to be accessed.
1096 * @param layout The current layout of the image aspect(s).
1097 *
1098 * @return The primary buffer that should be used for the given layout.
1099 */
1100 enum isl_aux_state
1101 anv_layout_to_aux_state(const struct gen_device_info * const devinfo,
1102 const struct anv_image * const image,
1103 const VkImageAspectFlagBits aspect,
1104 const VkImageLayout layout)
1105 {
1106 /* Validate the inputs. */
1107
1108 /* The devinfo is needed as the optimal buffer varies across generations. */
1109 assert(devinfo != NULL);
1110
1111 /* The layout of a NULL image is not properly defined. */
1112 assert(image != NULL);
1113
1114 /* The aspect must be exactly one of the image aspects. */
1115 assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
1116
1117 /* Determine the optimal buffer. */
1118
1119 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1120
1121 /* If we don't have an aux buffer then aux state makes no sense */
1122 assert(image->planes[plane].aux_surface.isl.size_B > 0);
1123
1124 /* All images that use an auxiliary surface are required to be tiled. */
1125 assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
1126
1127 /* Stencil has no aux */
1128 assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
1129
1130 switch (layout) {
1131 /* Invalid layouts */
1132 case VK_IMAGE_LAYOUT_RANGE_SIZE:
1133 case VK_IMAGE_LAYOUT_MAX_ENUM:
1134 unreachable("Invalid image layout.");
1135
1136 /* Undefined layouts
1137 *
1138 * The pre-initialized layout is equivalent to the undefined layout for
1139 * optimally-tiled images. We can only do color compression (CCS or HiZ)
1140 * on tiled images.
1141 */
1142 case VK_IMAGE_LAYOUT_UNDEFINED:
1143 case VK_IMAGE_LAYOUT_PREINITIALIZED:
1144 return ISL_AUX_STATE_AUX_INVALID;
1145
1146 /* Transfer layouts */
1147 case VK_IMAGE_LAYOUT_GENERAL:
1148 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
1149 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1150 /* This buffer could be a depth buffer used in a transfer operation.
1151 * BLORP currently doesn't use HiZ for transfer operations so we must
1152 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
1153 */
1154 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ);
1155 return ISL_AUX_STATE_AUX_INVALID;
1156 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
1157 return ISL_AUX_STATE_PASS_THROUGH;
1158 } else {
1159 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_D);
1160 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1161 }
1162
1163 /* Sampling layouts */
1164 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR:
1165 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
1166 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL:
1167 assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
1168 /* Fall-through */
1169 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
1170 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
1171 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1172 if (anv_can_sample_with_hiz(devinfo, image))
1173 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1174 else
1175 return ISL_AUX_STATE_RESOLVED;
1176 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
1177 return ISL_AUX_STATE_PASS_THROUGH;
1178 } else {
1179 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1180 }
1181
1182 case VK_IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL_KHR:
1183 return ISL_AUX_STATE_RESOLVED;
1184
1185 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
1186 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1187
1188 /* When handing the image off to the presentation engine, we need to
1189 * ensure that things are properly resolved. For images with no
1190 * modifier, we assume that they follow the old rules and always need
1191 * a full resolve because the PE doesn't understand any form of
1192 * compression. For images with modifiers, we use the aux usage from
1193 * the modifier.
1194 */
1195 const struct isl_drm_modifier_info *mod_info =
1196 isl_drm_modifier_get_info(image->drm_format_mod);
1197 if (mod_info && mod_info->aux_usage != ISL_AUX_USAGE_NONE) {
1198 assert(mod_info->aux_usage == ISL_AUX_USAGE_CCS_E);
1199 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E);
1200 /* We do not yet support any modifiers which support clear color so
1201 * we just always return COMPRESSED_NO_CLEAR. One day, this will
1202 * change.
1203 */
1204 assert(!mod_info->supports_clear_color);
1205 return ISL_AUX_STATE_COMPRESSED_NO_CLEAR;
1206 } else {
1207 return ISL_AUX_STATE_PASS_THROUGH;
1208 }
1209 }
1210
1211 /* Rendering layouts */
1212 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
1213 assert(aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1214 /* fall-through */
1215 case VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR:
1216 if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
1217 assert(image->samples == 1);
1218 return ISL_AUX_STATE_PARTIAL_CLEAR;
1219 } else {
1220 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_D);
1221 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1222 }
1223
1224 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR:
1225 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
1226 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL:
1227 assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
1228 return ISL_AUX_STATE_COMPRESSED_CLEAR;
1229
1230 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
1231 unreachable("VK_KHR_shared_presentable_image is unsupported");
1232
1233 case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT:
1234 unreachable("VK_EXT_fragment_density_map is unsupported");
1235
1236 case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV:
1237 unreachable("VK_NV_shading_rate_image is unsupported");
1238 }
1239
1240 unreachable("layout is not a VkImageLayout enumeration member.");
1241 }
1242
1243 /**
1244 * This function determines the optimal buffer to use for a given
1245 * VkImageLayout and other pieces of information needed to make that
1246 * determination. This does not determine the optimal buffer to use
1247 * during a resolve operation.
1248 *
1249 * @param devinfo The device information of the Intel GPU.
1250 * @param image The image that may contain a collection of buffers.
1251 * @param aspect The aspect of the image to be accessed.
1252 * @param layout The current layout of the image aspect(s).
1253 *
1254 * @return The primary buffer that should be used for the given layout.
1255 */
1256 enum isl_aux_usage
1257 anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
1258 const struct anv_image * const image,
1259 const VkImageAspectFlagBits aspect,
1260 const VkImageLayout layout)
1261 {
1262 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1263
1264 /* If there is no auxiliary surface allocated, we must use the one and only
1265 * main buffer.
1266 */
1267 if (image->planes[plane].aux_surface.isl.size_B == 0)
1268 return ISL_AUX_USAGE_NONE;
1269
1270 enum isl_aux_state aux_state =
1271 anv_layout_to_aux_state(devinfo, image, aspect, layout);
1272
1273 switch (aux_state) {
1274 case ISL_AUX_STATE_CLEAR:
1275 unreachable("We never use this state");
1276
1277 case ISL_AUX_STATE_PARTIAL_CLEAR:
1278 assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
1279 assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE);
1280 assert(image->samples == 1);
1281 return ISL_AUX_USAGE_CCS_D;
1282
1283 case ISL_AUX_STATE_COMPRESSED_CLEAR:
1284 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
1285 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1286 return ISL_AUX_USAGE_HIZ;
1287 } else {
1288 assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE);
1289 return image->planes[plane].aux_usage;
1290 }
1291
1292 case ISL_AUX_STATE_RESOLVED:
1293 case ISL_AUX_STATE_PASS_THROUGH:
1294 case ISL_AUX_STATE_AUX_INVALID:
1295 return ISL_AUX_USAGE_NONE;
1296 }
1297
1298 unreachable("Invalid isl_aux_state");
1299 }
1300
1301 /**
1302 * This function returns the level of unresolved fast-clear support of the
1303 * given image in the given VkImageLayout.
1304 *
1305 * @param devinfo The device information of the Intel GPU.
1306 * @param image The image that may contain a collection of buffers.
1307 * @param aspect The aspect of the image to be accessed.
1308 * @param layout The current layout of the image aspect(s).
1309 */
1310 enum anv_fast_clear_type
1311 anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
1312 const struct anv_image * const image,
1313 const VkImageAspectFlagBits aspect,
1314 const VkImageLayout layout)
1315 {
1316 if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
1317 return ANV_FAST_CLEAR_NONE;
1318
1319 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1320
1321 /* If there is no auxiliary surface allocated, there are no fast-clears */
1322 if (image->planes[plane].aux_surface.isl.size_B == 0)
1323 return ANV_FAST_CLEAR_NONE;
1324
1325 /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
1326 * lack the MI ALU which we need to determine the predicates.
1327 */
1328 if (devinfo->gen == 7 && !devinfo->is_haswell && image->samples > 1)
1329 return ANV_FAST_CLEAR_NONE;
1330
1331 enum isl_aux_state aux_state =
1332 anv_layout_to_aux_state(devinfo, image, aspect, layout);
1333
1334 switch (aux_state) {
1335 case ISL_AUX_STATE_CLEAR:
1336 unreachable("We never use this state");
1337
1338 case ISL_AUX_STATE_PARTIAL_CLEAR:
1339 case ISL_AUX_STATE_COMPRESSED_CLEAR:
1340 if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
1341 return ANV_FAST_CLEAR_DEFAULT_VALUE;
1342 } else if (layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
1343 /* When we're in a render pass we have the clear color data from the
1344 * VkRenderPassBeginInfo and we can use arbitrary clear colors. They
1345 * must get partially resolved before we leave the render pass.
1346 */
1347 return ANV_FAST_CLEAR_ANY;
1348 } else if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
1349 image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
1350 /* If the image has MCS or CCS_E enabled all the time then we can use
1351 * fast-clear as long as the clear color is the default value of zero
1352 * since this is the default value we program into every surface
1353 * state used for texturing.
1354 */
1355 return ANV_FAST_CLEAR_DEFAULT_VALUE;
1356 } else {
1357 return ANV_FAST_CLEAR_NONE;
1358 }
1359
1360 case ISL_AUX_STATE_COMPRESSED_NO_CLEAR:
1361 case ISL_AUX_STATE_RESOLVED:
1362 case ISL_AUX_STATE_PASS_THROUGH:
1363 case ISL_AUX_STATE_AUX_INVALID:
1364 return ANV_FAST_CLEAR_NONE;
1365 }
1366
1367 unreachable("Invalid isl_aux_state");
1368 }
1369
1370
1371 static struct anv_state
1372 alloc_surface_state(struct anv_device *device)
1373 {
1374 return anv_state_pool_alloc(&device->surface_state_pool, 64, 64);
1375 }
1376
1377 static enum isl_channel_select
1378 remap_swizzle(VkComponentSwizzle swizzle, VkComponentSwizzle component,
1379 struct isl_swizzle format_swizzle)
1380 {
1381 if (swizzle == VK_COMPONENT_SWIZZLE_IDENTITY)
1382 swizzle = component;
1383
1384 switch (swizzle) {
1385 case VK_COMPONENT_SWIZZLE_ZERO: return ISL_CHANNEL_SELECT_ZERO;
1386 case VK_COMPONENT_SWIZZLE_ONE: return ISL_CHANNEL_SELECT_ONE;
1387 case VK_COMPONENT_SWIZZLE_R: return format_swizzle.r;
1388 case VK_COMPONENT_SWIZZLE_G: return format_swizzle.g;
1389 case VK_COMPONENT_SWIZZLE_B: return format_swizzle.b;
1390 case VK_COMPONENT_SWIZZLE_A: return format_swizzle.a;
1391 default:
1392 unreachable("Invalid swizzle");
1393 }
1394 }
1395
1396 void
1397 anv_image_fill_surface_state(struct anv_device *device,
1398 const struct anv_image *image,
1399 VkImageAspectFlagBits aspect,
1400 const struct isl_view *view_in,
1401 isl_surf_usage_flags_t view_usage,
1402 enum isl_aux_usage aux_usage,
1403 const union isl_color_value *clear_color,
1404 enum anv_image_view_state_flags flags,
1405 struct anv_surface_state *state_inout,
1406 struct brw_image_param *image_param_out)
1407 {
1408 uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
1409
1410 const struct anv_surface *surface = &image->planes[plane].surface,
1411 *aux_surface = &image->planes[plane].aux_surface;
1412
1413 struct isl_view view = *view_in;
1414 view.usage |= view_usage;
1415
1416 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
1417 * compressed surface with a shadow surface, we use the shadow instead of
1418 * the primary surface. The shadow surface will be tiled, unlike the main
1419 * surface, so it should get significantly better performance.
1420 */
1421 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
1422 isl_format_is_compressed(view.format) &&
1423 (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
1424 assert(isl_format_is_compressed(surface->isl.format));
1425 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1426 assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
1427 surface = &image->planes[plane].shadow_surface;
1428 }
1429
1430 /* For texturing from stencil on gen7, we have to sample from a shadow
1431 * surface because we don't support W-tiling in the sampler.
1432 */
1433 if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
1434 aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
1435 assert(device->info.gen == 7);
1436 assert(view_usage & ISL_SURF_USAGE_TEXTURE_BIT);
1437 surface = &image->planes[plane].shadow_surface;
1438 }
1439
1440 if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
1441 view.swizzle = anv_swizzle_for_render(view.swizzle);
1442
1443 /* On Ivy Bridge and Bay Trail we do the swizzle in the shader */
1444 if (device->info.gen == 7 && !device->info.is_haswell)
1445 view.swizzle = ISL_SWIZZLE_IDENTITY;
1446
1447 /* If this is a HiZ buffer we can sample from with a programmable clear
1448 * value (SKL+), define the clear value to the optimal constant.
1449 */
1450 union isl_color_value default_clear_color = { .u32 = { 0, } };
1451 if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ)
1452 default_clear_color.f32[0] = ANV_HZ_FC_VAL;
1453 if (!clear_color)
1454 clear_color = &default_clear_color;
1455
1456 const struct anv_address address =
1457 anv_address_add(image->planes[plane].address, surface->offset);
1458
1459 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1460 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
1461 !isl_has_matching_typed_storage_image_format(&device->info,
1462 view.format)) {
1463 /* In this case, we are a writeable storage buffer which needs to be
1464 * lowered to linear. All tiling and offset calculations will be done in
1465 * the shader.
1466 */
1467 assert(aux_usage == ISL_AUX_USAGE_NONE);
1468 isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
1469 .address = anv_address_physical(address),
1470 .size_B = surface->isl.size_B,
1471 .format = ISL_FORMAT_RAW,
1472 .swizzle = ISL_SWIZZLE_IDENTITY,
1473 .stride_B = 1,
1474 .mocs = anv_mocs_for_bo(device, address.bo));
1475 state_inout->address = address,
1476 state_inout->aux_address = ANV_NULL_ADDRESS;
1477 state_inout->clear_address = ANV_NULL_ADDRESS;
1478 } else {
1479 if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
1480 !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
1481 /* Typed surface reads support a very limited subset of the shader
1482 * image formats. Translate it into the closest format the hardware
1483 * supports.
1484 */
1485 assert(aux_usage == ISL_AUX_USAGE_NONE);
1486 view.format = isl_lower_storage_image_format(&device->info,
1487 view.format);
1488 }
1489
1490 const struct isl_surf *isl_surf = &surface->isl;
1491
1492 struct isl_surf tmp_surf;
1493 uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
1494 if (isl_format_is_compressed(surface->isl.format) &&
1495 !isl_format_is_compressed(view.format)) {
1496 /* We're creating an uncompressed view of a compressed surface. This
1497 * is allowed but only for a single level/layer.
1498 */
1499 assert(surface->isl.samples == 1);
1500 assert(view.levels == 1);
1501 assert(view.array_len == 1);
1502
1503 isl_surf_get_image_surf(&device->isl_dev, isl_surf,
1504 view.base_level,
1505 surface->isl.dim == ISL_SURF_DIM_3D ?
1506 0 : view.base_array_layer,
1507 surface->isl.dim == ISL_SURF_DIM_3D ?
1508 view.base_array_layer : 0,
1509 &tmp_surf,
1510 &offset_B, &tile_x_sa, &tile_y_sa);
1511
1512 /* The newly created image represents the one subimage we're
1513 * referencing with this view so it only has one array slice and
1514 * miplevel.
1515 */
1516 view.base_array_layer = 0;
1517 view.base_level = 0;
1518
1519 /* We're making an uncompressed view here. The image dimensions need
1520 * to be scaled down by the block size.
1521 */
1522 const struct isl_format_layout *fmtl =
1523 isl_format_get_layout(surface->isl.format);
1524 tmp_surf.logical_level0_px =
1525 isl_surf_get_logical_level0_el(&tmp_surf);
1526 tmp_surf.phys_level0_sa = isl_surf_get_phys_level0_el(&tmp_surf);
1527 tmp_surf.format = view.format;
1528 tile_x_sa /= fmtl->bw;
1529 tile_y_sa /= fmtl->bh;
1530
1531 isl_surf = &tmp_surf;
1532
1533 if (device->info.gen <= 8) {
1534 assert(surface->isl.tiling == ISL_TILING_LINEAR);
1535 assert(tile_x_sa == 0);
1536 assert(tile_y_sa == 0);
1537 }
1538 }
1539
1540 state_inout->address = anv_address_add(address, offset_B);
1541
1542 struct anv_address aux_address = ANV_NULL_ADDRESS;
1543 if (aux_usage != ISL_AUX_USAGE_NONE) {
1544 aux_address = anv_address_add(image->planes[plane].address,
1545 aux_surface->offset);
1546 }
1547 state_inout->aux_address = aux_address;
1548
1549 struct anv_address clear_address = ANV_NULL_ADDRESS;
1550 if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
1551 if (aux_usage == ISL_AUX_USAGE_HIZ) {
1552 clear_address = (struct anv_address) {
1553 .bo = device->hiz_clear_bo,
1554 .offset = 0,
1555 };
1556 } else {
1557 clear_address = anv_image_get_clear_color_addr(device, image, aspect);
1558 }
1559 }
1560 state_inout->clear_address = clear_address;
1561
1562 isl_surf_fill_state(&device->isl_dev, state_inout->state.map,
1563 .surf = isl_surf,
1564 .view = &view,
1565 .address = anv_address_physical(state_inout->address),
1566 .clear_color = *clear_color,
1567 .aux_surf = &aux_surface->isl,
1568 .aux_usage = aux_usage,
1569 .aux_address = anv_address_physical(aux_address),
1570 .clear_address = anv_address_physical(clear_address),
1571 .use_clear_address = !anv_address_is_null(clear_address),
1572 .mocs = anv_mocs_for_bo(device,
1573 state_inout->address.bo),
1574 .x_offset_sa = tile_x_sa,
1575 .y_offset_sa = tile_y_sa);
1576
1577 /* With the exception of gen8, the bottom 12 bits of the MCS base address
1578 * are used to store other information. This should be ok, however,
1579 * because the surface buffer addresses are always 4K page aligned.
1580 */
1581 uint32_t *aux_addr_dw = state_inout->state.map +
1582 device->isl_dev.ss.aux_addr_offset;
1583 assert((aux_address.offset & 0xfff) == 0);
1584 state_inout->aux_address.offset |= *aux_addr_dw & 0xfff;
1585
1586 if (device->info.gen >= 10 && clear_address.bo) {
1587 uint32_t *clear_addr_dw = state_inout->state.map +
1588 device->isl_dev.ss.clear_color_state_offset;
1589 assert((clear_address.offset & 0x3f) == 0);
1590 state_inout->clear_address.offset |= *clear_addr_dw & 0x3f;
1591 }
1592 }
1593
1594 if (image_param_out) {
1595 assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT);
1596 isl_surf_fill_image_param(&device->isl_dev, image_param_out,
1597 &surface->isl, &view);
1598 }
1599 }
1600
1601 static VkImageAspectFlags
1602 remap_aspect_flags(VkImageAspectFlags view_aspects)
1603 {
1604 if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
1605 if (util_bitcount(view_aspects) == 1)
1606 return VK_IMAGE_ASPECT_COLOR_BIT;
1607
1608 VkImageAspectFlags color_aspects = 0;
1609 for (uint32_t i = 0; i < util_bitcount(view_aspects); i++)
1610 color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT << i;
1611 return color_aspects;
1612 }
1613 /* No special remapping needed for depth & stencil aspects. */
1614 return view_aspects;
1615 }
1616
1617 static uint32_t
1618 anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
1619 {
1620 uint32_t planes = 0;
1621
1622 if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
1623 VK_IMAGE_ASPECT_DEPTH_BIT |
1624 VK_IMAGE_ASPECT_STENCIL_BIT |
1625 VK_IMAGE_ASPECT_PLANE_0_BIT))
1626 planes++;
1627 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
1628 planes++;
1629 if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
1630 planes++;
1631
1632 if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
1633 (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
1634 planes++;
1635
1636 return planes;
1637 }
1638
1639 VkResult
1640 anv_CreateImageView(VkDevice _device,
1641 const VkImageViewCreateInfo *pCreateInfo,
1642 const VkAllocationCallbacks *pAllocator,
1643 VkImageView *pView)
1644 {
1645 ANV_FROM_HANDLE(anv_device, device, _device);
1646 ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
1647 struct anv_image_view *iview;
1648
1649 iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
1650 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1651 if (iview == NULL)
1652 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1653
1654 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1655
1656 assert(range->layerCount > 0);
1657 assert(range->baseMipLevel < image->levels);
1658
1659 /* Check if a conversion info was passed. */
1660 const struct anv_format *conv_format = NULL;
1661 const VkSamplerYcbcrConversionInfo *conv_info =
1662 vk_find_struct_const(pCreateInfo->pNext, SAMPLER_YCBCR_CONVERSION_INFO);
1663
1664 /* If image has an external format, the pNext chain must contain an instance of
1665 * VKSamplerYcbcrConversionInfo with a conversion object created with the same
1666 * external format as image."
1667 */
1668 assert(!image->external_format || conv_info);
1669
1670 if (conv_info) {
1671 ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion, conv_info->conversion);
1672 conv_format = conversion->format;
1673 }
1674
1675 VkImageUsageFlags image_usage = 0;
1676 if (range->aspectMask & ~VK_IMAGE_ASPECT_STENCIL_BIT)
1677 image_usage |= image->usage;
1678 if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT)
1679 image_usage |= image->stencil_usage;
1680
1681 const VkImageViewUsageCreateInfo *usage_info =
1682 vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO);
1683 VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image_usage;
1684
1685 /* View usage should be a subset of image usage */
1686 assert((view_usage & ~image_usage) == 0);
1687 assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
1688 VK_IMAGE_USAGE_STORAGE_BIT |
1689 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
1690 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
1691 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
1692
1693 switch (image->type) {
1694 default:
1695 unreachable("bad VkImageType");
1696 case VK_IMAGE_TYPE_1D:
1697 case VK_IMAGE_TYPE_2D:
1698 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1 <= image->array_size);
1699 break;
1700 case VK_IMAGE_TYPE_3D:
1701 assert(range->baseArrayLayer + anv_get_layerCount(image, range) - 1
1702 <= anv_minify(image->extent.depth, range->baseMipLevel));
1703 break;
1704 }
1705
1706 /* First expand aspects to the image's ones (for example
1707 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1708 * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
1709 * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
1710 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.
1711 */
1712 VkImageAspectFlags expanded_aspects =
1713 anv_image_expand_aspects(image, range->aspectMask);
1714
1715 iview->image = image;
1716
1717 /* Remap the expanded aspects for the image view. For example if only
1718 * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
1719 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1720 * the image view, it only has a single plane.
1721 */
1722 iview->aspect_mask = remap_aspect_flags(expanded_aspects);
1723 iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask);
1724 iview->vk_format = pCreateInfo->format;
1725
1726 /* "If image has an external format, format must be VK_FORMAT_UNDEFINED." */
1727 assert(!image->external_format || pCreateInfo->format == VK_FORMAT_UNDEFINED);
1728
1729 /* Format is undefined, this can happen when using external formats. Set
1730 * view format from the passed conversion info.
1731 */
1732 if (iview->vk_format == VK_FORMAT_UNDEFINED && conv_format)
1733 iview->vk_format = conv_format->vk_format;
1734
1735 iview->extent = (VkExtent3D) {
1736 .width = anv_minify(image->extent.width , range->baseMipLevel),
1737 .height = anv_minify(image->extent.height, range->baseMipLevel),
1738 .depth = anv_minify(image->extent.depth , range->baseMipLevel),
1739 };
1740
1741 /* Now go through the underlying image selected planes (computed in
1742 * expanded_aspects) and map them to planes in the image view.
1743 */
1744 uint32_t iaspect_bit, vplane = 0;
1745 anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) {
1746 uint32_t iplane =
1747 anv_image_aspect_to_plane(image->aspects, 1UL << iaspect_bit);
1748 VkImageAspectFlags vplane_aspect =
1749 anv_plane_to_aspect(iview->aspect_mask, vplane);
1750 struct anv_format_plane format =
1751 anv_get_format_plane(&device->info, iview->vk_format,
1752 vplane_aspect, image->tiling);
1753
1754 iview->planes[vplane].image_plane = iplane;
1755
1756 iview->planes[vplane].isl = (struct isl_view) {
1757 .format = format.isl_format,
1758 .base_level = range->baseMipLevel,
1759 .levels = anv_get_levelCount(image, range),
1760 .base_array_layer = range->baseArrayLayer,
1761 .array_len = anv_get_layerCount(image, range),
1762 .swizzle = {
1763 .r = remap_swizzle(pCreateInfo->components.r,
1764 VK_COMPONENT_SWIZZLE_R, format.swizzle),
1765 .g = remap_swizzle(pCreateInfo->components.g,
1766 VK_COMPONENT_SWIZZLE_G, format.swizzle),
1767 .b = remap_swizzle(pCreateInfo->components.b,
1768 VK_COMPONENT_SWIZZLE_B, format.swizzle),
1769 .a = remap_swizzle(pCreateInfo->components.a,
1770 VK_COMPONENT_SWIZZLE_A, format.swizzle),
1771 },
1772 };
1773
1774 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
1775 iview->planes[vplane].isl.base_array_layer = 0;
1776 iview->planes[vplane].isl.array_len = iview->extent.depth;
1777 }
1778
1779 if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
1780 pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
1781 iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT;
1782 } else {
1783 iview->planes[vplane].isl.usage = 0;
1784 }
1785
1786 if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
1787 (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
1788 !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
1789 iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device);
1790 iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device);
1791
1792 enum isl_aux_usage general_aux_usage =
1793 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1794 VK_IMAGE_LAYOUT_GENERAL);
1795 enum isl_aux_usage optimal_aux_usage =
1796 anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
1797 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
1798
1799 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1800 &iview->planes[vplane].isl,
1801 ISL_SURF_USAGE_TEXTURE_BIT,
1802 optimal_aux_usage, NULL,
1803 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL,
1804 &iview->planes[vplane].optimal_sampler_surface_state,
1805 NULL);
1806
1807 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1808 &iview->planes[vplane].isl,
1809 ISL_SURF_USAGE_TEXTURE_BIT,
1810 general_aux_usage, NULL,
1811 0,
1812 &iview->planes[vplane].general_sampler_surface_state,
1813 NULL);
1814 }
1815
1816 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1817 if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
1818 iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device);
1819 iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device);
1820
1821 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1822 &iview->planes[vplane].isl,
1823 ISL_SURF_USAGE_STORAGE_BIT,
1824 ISL_AUX_USAGE_NONE, NULL,
1825 0,
1826 &iview->planes[vplane].storage_surface_state,
1827 &iview->planes[vplane].storage_image_param);
1828
1829 anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
1830 &iview->planes[vplane].isl,
1831 ISL_SURF_USAGE_STORAGE_BIT,
1832 ISL_AUX_USAGE_NONE, NULL,
1833 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY,
1834 &iview->planes[vplane].writeonly_storage_surface_state,
1835 NULL);
1836 }
1837
1838 vplane++;
1839 }
1840
1841 *pView = anv_image_view_to_handle(iview);
1842
1843 return VK_SUCCESS;
1844 }
1845
1846 void
1847 anv_DestroyImageView(VkDevice _device, VkImageView _iview,
1848 const VkAllocationCallbacks *pAllocator)
1849 {
1850 ANV_FROM_HANDLE(anv_device, device, _device);
1851 ANV_FROM_HANDLE(anv_image_view, iview, _iview);
1852
1853 if (!iview)
1854 return;
1855
1856 for (uint32_t plane = 0; plane < iview->n_planes; plane++) {
1857 if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) {
1858 anv_state_pool_free(&device->surface_state_pool,
1859 iview->planes[plane].optimal_sampler_surface_state.state);
1860 }
1861
1862 if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) {
1863 anv_state_pool_free(&device->surface_state_pool,
1864 iview->planes[plane].general_sampler_surface_state.state);
1865 }
1866
1867 if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) {
1868 anv_state_pool_free(&device->surface_state_pool,
1869 iview->planes[plane].storage_surface_state.state);
1870 }
1871
1872 if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) {
1873 anv_state_pool_free(&device->surface_state_pool,
1874 iview->planes[plane].writeonly_storage_surface_state.state);
1875 }
1876 }
1877
1878 vk_free2(&device->alloc, pAllocator, iview);
1879 }
1880
1881
1882 VkResult
1883 anv_CreateBufferView(VkDevice _device,
1884 const VkBufferViewCreateInfo *pCreateInfo,
1885 const VkAllocationCallbacks *pAllocator,
1886 VkBufferView *pView)
1887 {
1888 ANV_FROM_HANDLE(anv_device, device, _device);
1889 ANV_FROM_HANDLE(anv_buffer, buffer, pCreateInfo->buffer);
1890 struct anv_buffer_view *view;
1891
1892 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1893 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1894 if (!view)
1895 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1896
1897 /* TODO: Handle the format swizzle? */
1898
1899 view->format = anv_get_isl_format(&device->info, pCreateInfo->format,
1900 VK_IMAGE_ASPECT_COLOR_BIT,
1901 VK_IMAGE_TILING_LINEAR);
1902 const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
1903 view->range = anv_buffer_get_range(buffer, pCreateInfo->offset,
1904 pCreateInfo->range);
1905 view->range = align_down_npot_u32(view->range, format_bs);
1906
1907 view->address = anv_address_add(buffer->address, pCreateInfo->offset);
1908
1909 if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
1910 view->surface_state = alloc_surface_state(device);
1911
1912 anv_fill_buffer_surface_state(device, view->surface_state,
1913 view->format,
1914 view->address, view->range, format_bs);
1915 } else {
1916 view->surface_state = (struct anv_state){ 0 };
1917 }
1918
1919 if (buffer->usage & VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT) {
1920 view->storage_surface_state = alloc_surface_state(device);
1921 view->writeonly_storage_surface_state = alloc_surface_state(device);
1922
1923 enum isl_format storage_format =
1924 isl_has_matching_typed_storage_image_format(&device->info,
1925 view->format) ?
1926 isl_lower_storage_image_format(&device->info, view->format) :
1927 ISL_FORMAT_RAW;
1928
1929 anv_fill_buffer_surface_state(device, view->storage_surface_state,
1930 storage_format,
1931 view->address, view->range,
1932 (storage_format == ISL_FORMAT_RAW ? 1 :
1933 isl_format_get_layout(storage_format)->bpb / 8));
1934
1935 /* Write-only accesses should use the original format. */
1936 anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
1937 view->format,
1938 view->address, view->range,
1939 isl_format_get_layout(view->format)->bpb / 8);
1940
1941 isl_buffer_fill_image_param(&device->isl_dev,
1942 &view->storage_image_param,
1943 view->format, view->range);
1944 } else {
1945 view->storage_surface_state = (struct anv_state){ 0 };
1946 view->writeonly_storage_surface_state = (struct anv_state){ 0 };
1947 }
1948
1949 *pView = anv_buffer_view_to_handle(view);
1950
1951 return VK_SUCCESS;
1952 }
1953
1954 void
1955 anv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1956 const VkAllocationCallbacks *pAllocator)
1957 {
1958 ANV_FROM_HANDLE(anv_device, device, _device);
1959 ANV_FROM_HANDLE(anv_buffer_view, view, bufferView);
1960
1961 if (!view)
1962 return;
1963
1964 if (view->surface_state.alloc_size > 0)
1965 anv_state_pool_free(&device->surface_state_pool,
1966 view->surface_state);
1967
1968 if (view->storage_surface_state.alloc_size > 0)
1969 anv_state_pool_free(&device->surface_state_pool,
1970 view->storage_surface_state);
1971
1972 if (view->writeonly_storage_surface_state.alloc_size > 0)
1973 anv_state_pool_free(&device->surface_state_pool,
1974 view->writeonly_storage_surface_state);
1975
1976 vk_free2(&device->alloc, pAllocator, view);
1977 }
1978
1979 const struct anv_surface *
1980 anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
1981 VkImageAspectFlags aspect_mask)
1982 {
1983 VkImageAspectFlags sanitized_mask;
1984
1985 switch (aspect_mask) {
1986 case VK_IMAGE_ASPECT_COLOR_BIT:
1987 assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
1988 sanitized_mask = VK_IMAGE_ASPECT_COLOR_BIT;
1989 break;
1990 case VK_IMAGE_ASPECT_DEPTH_BIT:
1991 assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
1992 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
1993 break;
1994 case VK_IMAGE_ASPECT_STENCIL_BIT:
1995 assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
1996 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
1997 break;
1998 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1999 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
2000 * combined depth stencil formats. Specifically, it states:
2001 *
2002 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
2003 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
2004 *
2005 * Image views with both depth and stencil aspects are only valid for
2006 * render target attachments, in which case
2007 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
2008 * stencil surfaces from the underlying surface.
2009 */
2010 if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
2011 sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
2012 } else {
2013 assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
2014 sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
2015 }
2016 break;
2017 case VK_IMAGE_ASPECT_PLANE_0_BIT:
2018 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
2019 sanitized_mask = VK_IMAGE_ASPECT_PLANE_0_BIT;
2020 break;
2021 case VK_IMAGE_ASPECT_PLANE_1_BIT:
2022 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
2023 sanitized_mask = VK_IMAGE_ASPECT_PLANE_1_BIT;
2024 break;
2025 case VK_IMAGE_ASPECT_PLANE_2_BIT:
2026 assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
2027 sanitized_mask = VK_IMAGE_ASPECT_PLANE_2_BIT;
2028 break;
2029 default:
2030 unreachable("image does not have aspect");
2031 return NULL;
2032 }
2033
2034 uint32_t plane = anv_image_aspect_to_plane(image->aspects, sanitized_mask);
2035 return &image->planes[plane].surface;
2036 }