2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <drm_fourcc.h>
32 #include "anv_private.h"
33 #include "util/debug.h"
36 #include "vk_format_info.h"
38 static isl_surf_usage_flags_t
39 choose_isl_surf_usage(VkImageCreateFlags vk_create_flags
,
40 VkImageUsageFlags vk_usage
,
41 isl_surf_usage_flags_t isl_extra_usage
,
42 VkImageAspectFlagBits aspect
)
44 isl_surf_usage_flags_t isl_usage
= isl_extra_usage
;
46 if (vk_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
)
47 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
49 if (vk_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
50 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
52 if (vk_usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
53 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
55 if (vk_create_flags
& VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT
)
56 isl_usage
|= ISL_SURF_USAGE_CUBE_BIT
;
58 /* Even if we're only using it for transfer operations, clears to depth and
59 * stencil images happen as depth and stencil so they need the right ISL
60 * usage bits or else things will fall apart.
63 case VK_IMAGE_ASPECT_DEPTH_BIT
:
64 isl_usage
|= ISL_SURF_USAGE_DEPTH_BIT
;
66 case VK_IMAGE_ASPECT_STENCIL_BIT
:
67 isl_usage
|= ISL_SURF_USAGE_STENCIL_BIT
;
69 case VK_IMAGE_ASPECT_COLOR_BIT
:
70 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
71 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
72 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
75 unreachable("bad VkImageAspect");
78 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_SRC_BIT
) {
79 /* blorp implements transfers by sampling from the source image. */
80 isl_usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
83 if (vk_usage
& VK_IMAGE_USAGE_TRANSFER_DST_BIT
&&
84 aspect
== VK_IMAGE_ASPECT_COLOR_BIT
) {
85 /* blorp implements transfers by rendering into the destination image.
86 * Only request this with color images, as we deal with depth/stencil
87 * formats differently. */
88 isl_usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
94 static isl_tiling_flags_t
95 choose_isl_tiling_flags(const struct anv_image_create_info
*anv_info
,
96 const struct isl_drm_modifier_info
*isl_mod_info
,
99 const VkImageCreateInfo
*base_info
= anv_info
->vk_info
;
100 isl_tiling_flags_t flags
= 0;
102 switch (base_info
->tiling
) {
104 unreachable("bad VkImageTiling");
105 case VK_IMAGE_TILING_OPTIMAL
:
106 flags
= ISL_TILING_ANY_MASK
;
108 case VK_IMAGE_TILING_LINEAR
:
109 flags
= ISL_TILING_LINEAR_BIT
;
113 if (anv_info
->isl_tiling_flags
)
114 flags
&= anv_info
->isl_tiling_flags
;
117 flags
&= ISL_TILING_LINEAR_BIT
| ISL_TILING_X_BIT
;
120 flags
&= 1 << isl_mod_info
->tiling
;
127 static struct anv_surface
*
128 get_surface(struct anv_image
*image
, VkImageAspectFlagBits aspect
)
130 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
131 return &image
->planes
[plane
].surface
;
135 add_surface(struct anv_image
*image
, struct anv_surface
*surf
, uint32_t plane
)
137 assert(surf
->isl
.size
> 0); /* isl surface must be initialized */
139 if (image
->disjoint
) {
140 surf
->offset
= align_u32(image
->planes
[plane
].size
, surf
->isl
.alignment
);
141 /* Plane offset is always 0 when it's disjoint. */
143 surf
->offset
= align_u32(image
->size
, surf
->isl
.alignment
);
144 /* Determine plane's offset only once when the first surface is added. */
145 if (image
->planes
[plane
].size
== 0)
146 image
->planes
[plane
].offset
= image
->size
;
149 image
->size
= surf
->offset
+ surf
->isl
.size
;
150 image
->planes
[plane
].size
= (surf
->offset
+ surf
->isl
.size
) - image
->planes
[plane
].offset
;
152 image
->alignment
= MAX2(image
->alignment
, surf
->isl
.alignment
);
153 image
->planes
[plane
].alignment
= MAX2(image
->planes
[plane
].alignment
,
154 surf
->isl
.alignment
);
159 all_formats_ccs_e_compatible(const struct gen_device_info
*devinfo
,
160 const struct VkImageCreateInfo
*vk_info
)
162 enum isl_format format
=
163 anv_get_isl_format(devinfo
, vk_info
->format
,
164 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
166 if (!isl_format_supports_ccs_e(devinfo
, format
))
169 if (!(vk_info
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
))
172 const VkImageFormatListCreateInfoKHR
*fmt_list
=
173 vk_find_struct_const(vk_info
->pNext
, IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
175 if (!fmt_list
|| fmt_list
->viewFormatCount
== 0)
178 for (uint32_t i
= 0; i
< fmt_list
->viewFormatCount
; i
++) {
179 enum isl_format view_format
=
180 anv_get_isl_format(devinfo
, fmt_list
->pViewFormats
[i
],
181 VK_IMAGE_ASPECT_COLOR_BIT
, vk_info
->tiling
);
183 if (!isl_formats_are_ccs_e_compatible(devinfo
, format
, view_format
))
191 * For color images that have an auxiliary surface, request allocation for an
192 * additional buffer that mainly stores fast-clear values. Use of this buffer
193 * allows us to access the image's subresources while being aware of their
194 * fast-clear values in non-trivial cases (e.g., outside of a render pass in
195 * which a fast clear has occurred).
197 * In order to avoid having multiple clear colors for a single plane of an
198 * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
199 * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
200 * 2018), there were no known applications which would benefit from fast-
201 * clearing more than just the first slice.
203 * The fast clear portion of the image is laid out in the following order:
205 * * 1 or 4 dwords (depending on hardware generation) for the clear color
206 * * 1 dword for the anv_fast_clear_type of the clear color
207 * * On gen9+, 1 dword per level and layer of the image (3D levels count
208 * multiple layers) in level-major order for compression state.
210 * For the purpose of discoverability, the algorithm used to manage
211 * compression and fast-clears is described here:
213 * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
214 * all of the values in the fast clear portion of the image are initialized
217 * * On fast-clear, the clear value is written into surface state and also
218 * into the buffer and the fast clear type is set appropriately. Both
219 * setting the fast-clear value in the buffer and setting the fast-clear
220 * type happen from the GPU using MI commands.
222 * * Whenever a render or blorp operation is performed with CCS_E, we call
223 * genX(cmd_buffer_mark_image_written) to set the compression state to
224 * true (which is represented by UINT32_MAX).
226 * * On pipeline barrier transitions, the worst-case transition is computed
227 * from the image layouts. The command streamer inspects the fast clear
228 * type and compression state dwords and constructs a predicate. The
229 * worst-case resolve is performed with the given predicate and the fast
230 * clear and compression state is set accordingly.
232 * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
233 * details on exactly what is allowed in what layouts.
235 * On gen7-9, we do not have a concept of indirect clear colors in hardware.
236 * In order to deal with this, we have to do some clear color management.
238 * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
239 * value from the buffer into the surface state with MI commands.
241 * * For any blorp operations, we pass the address to the clear value into
242 * blorp and it knows to copy the clear color.
245 add_aux_state_tracking_buffer(struct anv_image
*image
,
246 VkImageAspectFlagBits aspect
,
248 const struct anv_device
*device
)
250 assert(image
&& device
);
251 assert(image
->planes
[plane
].aux_surface
.isl
.size
> 0 &&
252 image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
254 /* Compressed images must be tiled and therefore everything should be 4K
255 * aligned. The CCS has the same alignment requirements. This is good
256 * because we need at least dword-alignment for MI_LOAD/STORE operations.
258 assert(image
->alignment
% 4 == 0);
259 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) % 4 == 0);
261 /* This buffer should be at the very end of the plane. */
262 if (image
->disjoint
) {
263 assert(image
->planes
[plane
].size
==
264 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
266 assert(image
->size
==
267 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
270 /* Clear color and fast clear type */
271 unsigned state_size
= device
->isl_dev
.ss
.clear_value_size
+ 4;
273 /* We only need to track compression on CCS_E surfaces. */
274 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
275 if (image
->type
== VK_IMAGE_TYPE_3D
) {
276 for (uint32_t l
= 0; l
< image
->levels
; l
++)
277 state_size
+= anv_minify(image
->extent
.depth
, l
) * 4;
279 state_size
+= image
->levels
* image
->array_size
* 4;
283 image
->planes
[plane
].fast_clear_state_offset
=
284 image
->planes
[plane
].offset
+ image
->planes
[plane
].size
;
286 image
->planes
[plane
].size
+= state_size
;
287 image
->size
+= state_size
;
291 * Initialize the anv_image::*_surface selected by \a aspect. Then update the
292 * image's memory requirements (that is, the image's size and alignment).
295 make_surface(const struct anv_device
*dev
,
296 struct anv_image
*image
,
297 const struct anv_image_create_info
*anv_info
,
298 isl_tiling_flags_t tiling_flags
,
299 VkImageAspectFlagBits aspect
)
301 const VkImageCreateInfo
*vk_info
= anv_info
->vk_info
;
304 static const enum isl_surf_dim vk_to_isl_surf_dim
[] = {
305 [VK_IMAGE_TYPE_1D
] = ISL_SURF_DIM_1D
,
306 [VK_IMAGE_TYPE_2D
] = ISL_SURF_DIM_2D
,
307 [VK_IMAGE_TYPE_3D
] = ISL_SURF_DIM_3D
,
310 image
->extent
= anv_sanitize_image_extent(vk_info
->imageType
,
313 const unsigned plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
314 const struct anv_format_plane plane_format
=
315 anv_get_format_plane(&dev
->info
, image
->vk_format
, aspect
, image
->tiling
);
316 struct anv_surface
*anv_surf
= &image
->planes
[plane
].surface
;
318 const isl_surf_usage_flags_t usage
=
319 choose_isl_surf_usage(vk_info
->flags
, image
->usage
,
320 anv_info
->isl_extra_usage_flags
, aspect
);
322 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
323 * fall back to linear on Broadwell and earlier because we aren't
324 * guaranteed that we can handle offsets correctly. On Sky Lake, the
325 * horizontal and vertical alignments are sufficiently high that we can
326 * just use RENDER_SURFACE_STATE::X/Y Offset.
328 bool needs_shadow
= false;
329 if (dev
->info
.gen
<= 8 &&
330 (vk_info
->flags
& VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR
) &&
331 vk_info
->tiling
== VK_IMAGE_TILING_OPTIMAL
) {
332 assert(isl_format_is_compressed(plane_format
.isl_format
));
333 tiling_flags
= ISL_TILING_LINEAR_BIT
;
337 ok
= isl_surf_init(&dev
->isl_dev
, &anv_surf
->isl
,
338 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
339 .format
= plane_format
.isl_format
,
340 .width
= image
->extent
.width
/ plane_format
.denominator_scales
[0],
341 .height
= image
->extent
.height
/ plane_format
.denominator_scales
[1],
342 .depth
= image
->extent
.depth
,
343 .levels
= vk_info
->mipLevels
,
344 .array_len
= vk_info
->arrayLayers
,
345 .samples
= vk_info
->samples
,
347 .row_pitch
= anv_info
->stride
,
349 .tiling_flags
= tiling_flags
);
352 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
354 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_NONE
;
356 add_surface(image
, anv_surf
, plane
);
358 /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
359 * create an identical tiled shadow surface for use while texturing so we
360 * don't get garbage performance.
363 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
364 assert(tiling_flags
== ISL_TILING_LINEAR_BIT
);
366 ok
= isl_surf_init(&dev
->isl_dev
, &image
->planes
[plane
].shadow_surface
.isl
,
367 .dim
= vk_to_isl_surf_dim
[vk_info
->imageType
],
368 .format
= plane_format
.isl_format
,
369 .width
= image
->extent
.width
,
370 .height
= image
->extent
.height
,
371 .depth
= image
->extent
.depth
,
372 .levels
= vk_info
->mipLevels
,
373 .array_len
= vk_info
->arrayLayers
,
374 .samples
= vk_info
->samples
,
376 .row_pitch
= anv_info
->stride
,
378 .tiling_flags
= ISL_TILING_ANY_MASK
);
380 /* isl_surf_init() will fail only if provided invalid input. Invalid input
381 * is illegal in Vulkan.
385 add_surface(image
, &image
->planes
[plane
].shadow_surface
, plane
);
388 /* Add a HiZ surface to a depth buffer that will be used for rendering.
390 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
391 /* We don't advertise that depth buffers could be used as storage
394 assert(!(image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
396 /* Allow the user to control HiZ enabling. Disable by default on gen7
397 * because resolves are not currently implemented pre-BDW.
399 if (!(image
->usage
& VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
)) {
400 /* It will never be used as an attachment, HiZ is pointless. */
401 } else if (dev
->info
.gen
== 7) {
402 anv_perf_warn(dev
->instance
, image
, "Implement gen7 HiZ");
403 } else if (vk_info
->mipLevels
> 1) {
404 anv_perf_warn(dev
->instance
, image
, "Enable multi-LOD HiZ");
405 } else if (vk_info
->arrayLayers
> 1) {
406 anv_perf_warn(dev
->instance
, image
,
407 "Implement multi-arrayLayer HiZ clears and resolves");
408 } else if (dev
->info
.gen
== 8 && vk_info
->samples
> 1) {
409 anv_perf_warn(dev
->instance
, image
, "Enable gen8 multisampled HiZ");
410 } else if (!unlikely(INTEL_DEBUG
& DEBUG_NO_HIZ
)) {
411 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
412 ok
= isl_surf_get_hiz_surf(&dev
->isl_dev
,
413 &image
->planes
[plane
].surface
.isl
,
414 &image
->planes
[plane
].aux_surface
.isl
);
416 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
417 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_HIZ
;
419 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
== 1) {
420 /* TODO: Disallow compression with :
422 * 1) non multiplanar images (We appear to hit a sampler bug with
423 * CCS & R16G16 format. Putting the clear state a page/4096bytes
424 * further fixes the issue).
426 * 2) alias images, because they might be aliases of images
429 * 3) compression disabled by debug
431 const bool allow_compression
=
432 image
->n_planes
== 1 &&
433 (vk_info
->flags
& VK_IMAGE_CREATE_ALIAS_BIT_KHR
) == 0 &&
434 likely((INTEL_DEBUG
& DEBUG_NO_RBC
) == 0);
436 if (allow_compression
) {
437 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
438 ok
= isl_surf_get_ccs_surf(&dev
->isl_dev
,
439 &image
->planes
[plane
].surface
.isl
,
440 &image
->planes
[plane
].aux_surface
.isl
, 0);
443 /* Disable CCS when it is not useful (i.e., when you can't render
444 * to the image with CCS enabled).
446 if (!isl_format_supports_rendering(&dev
->info
,
447 plane_format
.isl_format
)) {
448 /* While it may be technically possible to enable CCS for this
449 * image, we currently don't have things hooked up to get it
452 anv_perf_warn(dev
->instance
, image
,
453 "This image format doesn't support rendering. "
454 "Not allocating an CCS buffer.");
455 image
->planes
[plane
].aux_surface
.isl
.size
= 0;
459 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
460 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
462 /* For images created without MUTABLE_FORMAT_BIT set, we know that
463 * they will always be used with the original format. In
464 * particular, they will always be used with a format that
465 * supports color compression. If it's never used as a storage
466 * image, then it will only be used through the sampler or the as
467 * a render target. This means that it's safe to just leave
468 * compression on at all times for these formats.
470 if (!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) &&
471 all_formats_ccs_e_compatible(&dev
->info
, vk_info
)) {
472 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_CCS_E
;
476 } else if ((aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) && vk_info
->samples
> 1) {
477 assert(!(vk_info
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
));
478 assert(image
->planes
[plane
].aux_surface
.isl
.size
== 0);
479 ok
= isl_surf_get_mcs_surf(&dev
->isl_dev
,
480 &image
->planes
[plane
].surface
.isl
,
481 &image
->planes
[plane
].aux_surface
.isl
);
483 add_surface(image
, &image
->planes
[plane
].aux_surface
, plane
);
484 add_aux_state_tracking_buffer(image
, aspect
, plane
, dev
);
485 image
->planes
[plane
].aux_usage
= ISL_AUX_USAGE_MCS
;
489 assert((image
->planes
[plane
].offset
+ image
->planes
[plane
].size
) == image
->size
);
491 /* Upper bound of the last surface should be smaller than the plane's
494 assert((MAX2(image
->planes
[plane
].surface
.offset
,
495 image
->planes
[plane
].aux_surface
.offset
) +
496 (image
->planes
[plane
].aux_surface
.isl
.size
> 0 ?
497 image
->planes
[plane
].aux_surface
.isl
.size
:
498 image
->planes
[plane
].surface
.isl
.size
)) <=
499 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
501 if (image
->planes
[plane
].aux_surface
.isl
.size
) {
502 /* assert(image->planes[plane].fast_clear_state_offset == */
503 /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
504 assert(image
->planes
[plane
].fast_clear_state_offset
<
505 (image
->planes
[plane
].offset
+ image
->planes
[plane
].size
));
512 anv_image_create(VkDevice _device
,
513 const struct anv_image_create_info
*create_info
,
514 const VkAllocationCallbacks
* alloc
,
517 ANV_FROM_HANDLE(anv_device
, device
, _device
);
518 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
519 const struct isl_drm_modifier_info
*isl_mod_info
= NULL
;
520 struct anv_image
*image
= NULL
;
523 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
525 const struct wsi_image_create_info
*wsi_info
=
526 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
528 anv_assert(pCreateInfo
->mipLevels
> 0);
529 anv_assert(pCreateInfo
->arrayLayers
> 0);
530 anv_assert(pCreateInfo
->samples
> 0);
531 anv_assert(pCreateInfo
->extent
.width
> 0);
532 anv_assert(pCreateInfo
->extent
.height
> 0);
533 anv_assert(pCreateInfo
->extent
.depth
> 0);
535 image
= vk_zalloc2(&device
->alloc
, alloc
, sizeof(*image
), 8,
536 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
538 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
540 image
->type
= pCreateInfo
->imageType
;
541 image
->extent
= pCreateInfo
->extent
;
542 image
->vk_format
= pCreateInfo
->format
;
543 image
->format
= anv_get_format(pCreateInfo
->format
);
544 image
->aspects
= vk_format_aspects(image
->vk_format
);
545 image
->levels
= pCreateInfo
->mipLevels
;
546 image
->array_size
= pCreateInfo
->arrayLayers
;
547 image
->samples
= pCreateInfo
->samples
;
548 image
->usage
= pCreateInfo
->usage
;
549 image
->tiling
= pCreateInfo
->tiling
;
550 image
->disjoint
= pCreateInfo
->flags
& VK_IMAGE_CREATE_DISJOINT_BIT_KHR
;
551 image
->needs_set_tiling
= wsi_info
&& wsi_info
->scanout
;
553 const struct anv_format
*format
= anv_get_format(image
->vk_format
);
554 assert(format
!= NULL
);
556 const isl_tiling_flags_t isl_tiling_flags
=
557 choose_isl_tiling_flags(create_info
, isl_mod_info
,
558 image
->needs_set_tiling
);
560 image
->n_planes
= format
->n_planes
;
563 for_each_bit(b
, image
->aspects
) {
564 r
= make_surface(device
, image
, create_info
, isl_tiling_flags
,
570 *pImage
= anv_image_to_handle(image
);
576 vk_free2(&device
->alloc
, alloc
, image
);
582 anv_CreateImage(VkDevice device
,
583 const VkImageCreateInfo
*pCreateInfo
,
584 const VkAllocationCallbacks
*pAllocator
,
588 const VkNativeBufferANDROID
*gralloc_info
=
589 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
592 return anv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
596 return anv_image_create(device
,
597 &(struct anv_image_create_info
) {
598 .vk_info
= pCreateInfo
,
605 anv_DestroyImage(VkDevice _device
, VkImage _image
,
606 const VkAllocationCallbacks
*pAllocator
)
608 ANV_FROM_HANDLE(anv_device
, device
, _device
);
609 ANV_FROM_HANDLE(anv_image
, image
, _image
);
614 for (uint32_t p
= 0; p
< image
->n_planes
; ++p
) {
615 if (image
->planes
[p
].bo_is_owned
) {
616 assert(image
->planes
[p
].bo
!= NULL
);
617 anv_bo_cache_release(device
, &device
->bo_cache
, image
->planes
[p
].bo
);
621 vk_free2(&device
->alloc
, pAllocator
, image
);
624 static void anv_image_bind_memory_plane(struct anv_device
*device
,
625 struct anv_image
*image
,
627 struct anv_device_memory
*memory
,
628 uint32_t memory_offset
)
630 assert(!image
->planes
[plane
].bo_is_owned
);
633 image
->planes
[plane
].bo
= NULL
;
634 image
->planes
[plane
].bo_offset
= 0;
638 image
->planes
[plane
].bo
= memory
->bo
;
639 image
->planes
[plane
].bo_offset
= memory_offset
;
642 VkResult
anv_BindImageMemory(
645 VkDeviceMemory _memory
,
646 VkDeviceSize memoryOffset
)
648 ANV_FROM_HANDLE(anv_device
, device
, _device
);
649 ANV_FROM_HANDLE(anv_device_memory
, mem
, _memory
);
650 ANV_FROM_HANDLE(anv_image
, image
, _image
);
653 anv_foreach_image_aspect_bit(aspect_bit
, image
, image
->aspects
) {
655 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
656 anv_image_bind_memory_plane(device
, image
, plane
, mem
, memoryOffset
);
662 VkResult
anv_BindImageMemory2KHR(
664 uint32_t bindInfoCount
,
665 const VkBindImageMemoryInfoKHR
* pBindInfos
)
667 ANV_FROM_HANDLE(anv_device
, device
, _device
);
669 for (uint32_t i
= 0; i
< bindInfoCount
; i
++) {
670 const VkBindImageMemoryInfoKHR
*bind_info
= &pBindInfos
[i
];
671 ANV_FROM_HANDLE(anv_device_memory
, mem
, bind_info
->memory
);
672 ANV_FROM_HANDLE(anv_image
, image
, bind_info
->image
);
673 VkImageAspectFlags aspects
= image
->aspects
;
675 vk_foreach_struct_const(s
, bind_info
->pNext
) {
677 case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR
: {
678 const VkBindImagePlaneMemoryInfoKHR
*plane_info
=
679 (const VkBindImagePlaneMemoryInfoKHR
*) s
;
681 aspects
= plane_info
->planeAspect
;
685 anv_debug_ignored_stype(s
->sType
);
691 anv_foreach_image_aspect_bit(aspect_bit
, image
, aspects
) {
693 anv_image_aspect_to_plane(image
->aspects
, 1UL << aspect_bit
);
694 anv_image_bind_memory_plane(device
, image
, plane
,
695 mem
, bind_info
->memoryOffset
);
702 void anv_GetImageSubresourceLayout(
705 const VkImageSubresource
* subresource
,
706 VkSubresourceLayout
* layout
)
708 ANV_FROM_HANDLE(anv_image
, image
, _image
);
709 const struct anv_surface
*surface
=
710 get_surface(image
, subresource
->aspectMask
);
712 assert(__builtin_popcount(subresource
->aspectMask
) == 1);
714 /* If we are on a non-zero mip level or array slice, we need to
715 * calculate a real offset.
717 anv_assert(subresource
->mipLevel
== 0);
718 anv_assert(subresource
->arrayLayer
== 0);
720 layout
->offset
= surface
->offset
;
721 layout
->rowPitch
= surface
->isl
.row_pitch
;
722 layout
->depthPitch
= isl_surf_get_array_pitch(&surface
->isl
);
723 layout
->arrayPitch
= isl_surf_get_array_pitch(&surface
->isl
);
724 layout
->size
= surface
->isl
.size
;
728 * This function determines the optimal buffer to use for a given
729 * VkImageLayout and other pieces of information needed to make that
730 * determination. This does not determine the optimal buffer to use
731 * during a resolve operation.
733 * @param devinfo The device information of the Intel GPU.
734 * @param image The image that may contain a collection of buffers.
735 * @param aspect The aspect of the image to be accessed.
736 * @param layout The current layout of the image aspect(s).
738 * @return The primary buffer that should be used for the given layout.
741 anv_layout_to_aux_usage(const struct gen_device_info
* const devinfo
,
742 const struct anv_image
* const image
,
743 const VkImageAspectFlagBits aspect
,
744 const VkImageLayout layout
)
746 /* Validate the inputs. */
748 /* The devinfo is needed as the optimal buffer varies across generations. */
749 assert(devinfo
!= NULL
);
751 /* The layout of a NULL image is not properly defined. */
752 assert(image
!= NULL
);
754 /* The aspect must be exactly one of the image aspects. */
755 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
757 /* Determine the optimal buffer. */
759 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
761 /* If there is no auxiliary surface allocated, we must use the one and only
764 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
765 return ISL_AUX_USAGE_NONE
;
767 /* All images that use an auxiliary surface are required to be tiled. */
768 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
770 /* Stencil has no aux */
771 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
775 /* Invalid Layouts */
776 case VK_IMAGE_LAYOUT_RANGE_SIZE
:
777 case VK_IMAGE_LAYOUT_MAX_ENUM
:
778 unreachable("Invalid image layout.");
782 * The pre-initialized layout is equivalent to the undefined layout for
783 * optimally-tiled images. We can only do color compression (CCS or HiZ)
786 case VK_IMAGE_LAYOUT_UNDEFINED
:
787 case VK_IMAGE_LAYOUT_PREINITIALIZED
:
788 return ISL_AUX_USAGE_NONE
;
793 case VK_IMAGE_LAYOUT_GENERAL
:
794 case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
:
795 case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
:
796 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
797 /* This buffer could be a depth buffer used in a transfer operation.
798 * BLORP currently doesn't use HiZ for transfer operations so we must
799 * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
801 assert(image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_HIZ
);
802 return ISL_AUX_USAGE_NONE
;
804 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
805 return image
->planes
[plane
].aux_usage
;
809 /* Sampling Layouts */
810 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
811 case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR
:
812 assert((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
814 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
815 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
816 if (anv_can_sample_with_hiz(devinfo
, image
))
817 return ISL_AUX_USAGE_HIZ
;
819 return ISL_AUX_USAGE_NONE
;
821 return image
->planes
[plane
].aux_usage
;
825 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
826 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
828 /* On SKL+, the render buffer can be decompressed by the presentation
829 * engine. Support for this feature has not yet landed in the wider
830 * ecosystem. TODO: Update this code when support lands.
832 * From the BDW PRM, Vol 7, Render Target Resolve:
834 * If the MCS is enabled on a non-multisampled render target, the
835 * render target must be resolved before being used for other
836 * purposes (display, texture, CPU lock) The clear value from
837 * SURFACE_STATE is written into pixels in the render target
838 * indicated as clear in the MCS.
840 * Pre-SKL, the render buffer must be resolved before being used for
841 * presentation. We can infer that the auxiliary buffer is not used.
843 return ISL_AUX_USAGE_NONE
;
846 /* Rendering Layouts */
847 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
848 assert(aspect
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
849 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
) {
850 assert(image
->samples
== 1);
851 return ISL_AUX_USAGE_CCS_D
;
853 assert(image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_D
);
854 return image
->planes
[plane
].aux_usage
;
857 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
858 case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR
:
859 assert(aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
);
860 return ISL_AUX_USAGE_HIZ
;
862 case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR
:
863 unreachable("VK_KHR_shared_presentable_image is unsupported");
866 /* If the layout isn't recognized in the exhaustive switch above, the
867 * VkImageLayout value is not defined in vulkan.h.
869 unreachable("layout is not a VkImageLayout enumeration member.");
873 * This function returns the level of unresolved fast-clear support of the
874 * given image in the given VkImageLayout.
876 * @param devinfo The device information of the Intel GPU.
877 * @param image The image that may contain a collection of buffers.
878 * @param aspect The aspect of the image to be accessed.
879 * @param layout The current layout of the image aspect(s).
881 enum anv_fast_clear_type
882 anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo
,
883 const struct anv_image
* const image
,
884 const VkImageAspectFlagBits aspect
,
885 const VkImageLayout layout
)
887 /* The aspect must be exactly one of the image aspects. */
888 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
890 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
892 /* If there is no auxiliary surface allocated, there are no fast-clears */
893 if (image
->planes
[plane
].aux_surface
.isl
.size
== 0)
894 return ANV_FAST_CLEAR_NONE
;
896 /* All images that use an auxiliary surface are required to be tiled. */
897 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
899 /* Stencil has no aux */
900 assert(aspect
!= VK_IMAGE_ASPECT_STENCIL_BIT
);
902 if (aspect
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
903 /* For depth images (with HiZ), the layout supports fast-clears if and
904 * only if it supports HiZ. However, we only support fast-clears to the
905 * default depth value.
907 enum isl_aux_usage aux_usage
=
908 anv_layout_to_aux_usage(devinfo
, image
, aspect
, layout
);
909 return aux_usage
== ISL_AUX_USAGE_HIZ
?
910 ANV_FAST_CLEAR_DEFAULT_VALUE
: ANV_FAST_CLEAR_NONE
;
913 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
915 /* Multisample fast-clear is not yet supported. */
916 if (image
->samples
> 1)
917 return ANV_FAST_CLEAR_NONE
;
920 case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
:
921 return ANV_FAST_CLEAR_ANY
;
923 case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR
:
924 return ANV_FAST_CLEAR_NONE
;
927 /* If the image has CCS_E enabled all the time then we can use
928 * fast-clear as long as the clear color is the default value of zero
929 * since this is the default value we program into every surface state
930 * used for texturing.
932 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
)
933 return ANV_FAST_CLEAR_DEFAULT_VALUE
;
935 return ANV_FAST_CLEAR_NONE
;
940 static struct anv_state
941 alloc_surface_state(struct anv_device
*device
)
943 return anv_state_pool_alloc(&device
->surface_state_pool
, 64, 64);
946 static enum isl_channel_select
947 remap_swizzle(VkComponentSwizzle swizzle
, VkComponentSwizzle component
,
948 struct isl_swizzle format_swizzle
)
950 if (swizzle
== VK_COMPONENT_SWIZZLE_IDENTITY
)
954 case VK_COMPONENT_SWIZZLE_ZERO
: return ISL_CHANNEL_SELECT_ZERO
;
955 case VK_COMPONENT_SWIZZLE_ONE
: return ISL_CHANNEL_SELECT_ONE
;
956 case VK_COMPONENT_SWIZZLE_R
: return format_swizzle
.r
;
957 case VK_COMPONENT_SWIZZLE_G
: return format_swizzle
.g
;
958 case VK_COMPONENT_SWIZZLE_B
: return format_swizzle
.b
;
959 case VK_COMPONENT_SWIZZLE_A
: return format_swizzle
.a
;
961 unreachable("Invalid swizzle");
966 anv_image_fill_surface_state(struct anv_device
*device
,
967 const struct anv_image
*image
,
968 VkImageAspectFlagBits aspect
,
969 const struct isl_view
*view_in
,
970 isl_surf_usage_flags_t view_usage
,
971 enum isl_aux_usage aux_usage
,
972 const union isl_color_value
*clear_color
,
973 enum anv_image_view_state_flags flags
,
974 struct anv_surface_state
*state_inout
,
975 struct brw_image_param
*image_param_out
)
977 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
979 const struct anv_surface
*surface
= &image
->planes
[plane
].surface
,
980 *aux_surface
= &image
->planes
[plane
].aux_surface
;
982 struct isl_view view
= *view_in
;
983 view
.usage
|= view_usage
;
985 /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
986 * compressed surface with a shadow surface, we use the shadow instead of
987 * the primary surface. The shadow surface will be tiled, unlike the main
988 * surface, so it should get significantly better performance.
990 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
991 isl_format_is_compressed(view
.format
) &&
992 (flags
& ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
)) {
993 assert(isl_format_is_compressed(surface
->isl
.format
));
994 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
995 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
996 surface
= &image
->planes
[plane
].shadow_surface
;
999 if (view_usage
== ISL_SURF_USAGE_RENDER_TARGET_BIT
)
1000 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
1002 /* If this is a HiZ buffer we can sample from with a programmable clear
1003 * value (SKL+), define the clear value to the optimal constant.
1005 union isl_color_value default_clear_color
= { .u32
= { 0, } };
1006 if (device
->info
.gen
>= 9 && aux_usage
== ISL_AUX_USAGE_HIZ
)
1007 default_clear_color
.f32
[0] = ANV_HZ_FC_VAL
;
1009 clear_color
= &default_clear_color
;
1011 const uint64_t address
= image
->planes
[plane
].bo_offset
+ surface
->offset
;
1012 const uint64_t aux_address
= aux_usage
== ISL_AUX_USAGE_NONE
?
1013 0 : (image
->planes
[plane
].bo_offset
+ aux_surface
->offset
);
1015 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1016 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
) &&
1017 !isl_has_matching_typed_storage_image_format(&device
->info
,
1019 /* In this case, we are a writeable storage buffer which needs to be
1020 * lowered to linear. All tiling and offset calculations will be done in
1023 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1024 isl_buffer_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1026 .size
= surface
->isl
.size
,
1027 .format
= ISL_FORMAT_RAW
,
1029 .mocs
= device
->default_mocs
);
1030 state_inout
->address
= address
,
1031 state_inout
->aux_address
= 0;
1033 if (view_usage
== ISL_SURF_USAGE_STORAGE_BIT
&&
1034 !(flags
& ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
)) {
1035 /* Typed surface reads support a very limited subset of the shader
1036 * image formats. Translate it into the closest format the hardware
1039 assert(aux_usage
== ISL_AUX_USAGE_NONE
);
1040 view
.format
= isl_lower_storage_image_format(&device
->info
,
1044 const struct isl_surf
*isl_surf
= &surface
->isl
;
1046 struct isl_surf tmp_surf
;
1047 uint32_t offset_B
= 0, tile_x_sa
= 0, tile_y_sa
= 0;
1048 if (isl_format_is_compressed(surface
->isl
.format
) &&
1049 !isl_format_is_compressed(view
.format
)) {
1050 /* We're creating an uncompressed view of a compressed surface. This
1051 * is allowed but only for a single level/layer.
1053 assert(surface
->isl
.samples
== 1);
1054 assert(view
.levels
== 1);
1055 assert(view
.array_len
== 1);
1057 isl_surf_get_image_surf(&device
->isl_dev
, isl_surf
,
1059 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1060 0 : view
.base_array_layer
,
1061 surface
->isl
.dim
== ISL_SURF_DIM_3D
?
1062 view
.base_array_layer
: 0,
1064 &offset_B
, &tile_x_sa
, &tile_y_sa
);
1066 /* The newly created image represents the one subimage we're
1067 * referencing with this view so it only has one array slice and
1070 view
.base_array_layer
= 0;
1071 view
.base_level
= 0;
1073 /* We're making an uncompressed view here. The image dimensions need
1074 * to be scaled down by the block size.
1076 const struct isl_format_layout
*fmtl
=
1077 isl_format_get_layout(surface
->isl
.format
);
1078 tmp_surf
.format
= view
.format
;
1079 tmp_surf
.logical_level0_px
.width
=
1080 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.width
, fmtl
->bw
);
1081 tmp_surf
.logical_level0_px
.height
=
1082 DIV_ROUND_UP(tmp_surf
.logical_level0_px
.height
, fmtl
->bh
);
1083 tmp_surf
.phys_level0_sa
.width
/= fmtl
->bw
;
1084 tmp_surf
.phys_level0_sa
.height
/= fmtl
->bh
;
1085 tile_x_sa
/= fmtl
->bw
;
1086 tile_y_sa
/= fmtl
->bh
;
1088 isl_surf
= &tmp_surf
;
1090 if (device
->info
.gen
<= 8) {
1091 assert(surface
->isl
.tiling
== ISL_TILING_LINEAR
);
1092 assert(tile_x_sa
== 0);
1093 assert(tile_y_sa
== 0);
1097 isl_surf_fill_state(&device
->isl_dev
, state_inout
->state
.map
,
1100 .address
= address
+ offset_B
,
1101 .clear_color
= *clear_color
,
1102 .aux_surf
= &aux_surface
->isl
,
1103 .aux_usage
= aux_usage
,
1104 .aux_address
= aux_address
,
1105 .mocs
= device
->default_mocs
,
1106 .x_offset_sa
= tile_x_sa
,
1107 .y_offset_sa
= tile_y_sa
);
1108 state_inout
->address
= address
+ offset_B
;
1109 if (device
->info
.gen
>= 8) {
1110 state_inout
->aux_address
= aux_address
;
1112 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
1113 * used to store other information. This should be ok, however,
1114 * because surface buffer addresses are always 4K page alinged.
1116 uint32_t *aux_addr_dw
= state_inout
->state
.map
+
1117 device
->isl_dev
.ss
.aux_addr_offset
;
1118 assert((aux_address
& 0xfff) == 0);
1119 assert(aux_address
== (*aux_addr_dw
& 0xfffff000));
1120 state_inout
->aux_address
= *aux_addr_dw
;
1124 anv_state_flush(device
, state_inout
->state
);
1126 if (image_param_out
) {
1127 assert(view_usage
== ISL_SURF_USAGE_STORAGE_BIT
);
1128 isl_surf_fill_image_param(&device
->isl_dev
, image_param_out
,
1129 &surface
->isl
, &view
);
1133 static VkImageAspectFlags
1134 remap_aspect_flags(VkImageAspectFlags view_aspects
)
1136 if (view_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1137 if (_mesa_bitcount(view_aspects
) == 1)
1138 return VK_IMAGE_ASPECT_COLOR_BIT
;
1140 VkImageAspectFlags color_aspects
= 0;
1141 for (uint32_t i
= 0; i
< _mesa_bitcount(view_aspects
); i
++)
1142 color_aspects
|= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
<< i
;
1143 return color_aspects
;
1145 /* No special remapping needed for depth & stencil aspects. */
1146 return view_aspects
;
1150 anv_CreateImageView(VkDevice _device
,
1151 const VkImageViewCreateInfo
*pCreateInfo
,
1152 const VkAllocationCallbacks
*pAllocator
,
1155 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1156 ANV_FROM_HANDLE(anv_image
, image
, pCreateInfo
->image
);
1157 struct anv_image_view
*iview
;
1159 iview
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*iview
), 8,
1160 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1162 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1164 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1166 assert(range
->layerCount
> 0);
1167 assert(range
->baseMipLevel
< image
->levels
);
1169 const VkImageViewUsageCreateInfoKHR
*usage_info
=
1170 vk_find_struct_const(pCreateInfo
, IMAGE_VIEW_USAGE_CREATE_INFO_KHR
);
1171 VkImageUsageFlags view_usage
= usage_info
? usage_info
->usage
: image
->usage
;
1172 /* View usage should be a subset of image usage */
1173 assert((view_usage
& ~image
->usage
) == 0);
1174 assert(view_usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
1175 VK_IMAGE_USAGE_STORAGE_BIT
|
1176 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
|
1177 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
|
1178 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
));
1180 switch (image
->type
) {
1182 unreachable("bad VkImageType");
1183 case VK_IMAGE_TYPE_1D
:
1184 case VK_IMAGE_TYPE_2D
:
1185 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1 <= image
->array_size
);
1187 case VK_IMAGE_TYPE_3D
:
1188 assert(range
->baseArrayLayer
+ anv_get_layerCount(image
, range
) - 1
1189 <= anv_minify(image
->extent
.depth
, range
->baseMipLevel
));
1193 /* First expand aspects to the image's ones (for example
1194 * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
1195 * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
1196 * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
1197 * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
1199 VkImageAspectFlags expanded_aspects
=
1200 anv_image_expand_aspects(image
, range
->aspectMask
);
1202 iview
->image
= image
;
1204 /* Remap the expanded aspects for the image view. For example if only
1205 * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
1206 * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
1207 * the image view, it only has a single plane.
1209 iview
->aspect_mask
= remap_aspect_flags(expanded_aspects
);
1210 iview
->n_planes
= anv_image_aspect_get_planes(iview
->aspect_mask
);
1211 iview
->vk_format
= pCreateInfo
->format
;
1213 iview
->extent
= (VkExtent3D
) {
1214 .width
= anv_minify(image
->extent
.width
, range
->baseMipLevel
),
1215 .height
= anv_minify(image
->extent
.height
, range
->baseMipLevel
),
1216 .depth
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
),
1219 /* Now go through the underlying image selected planes (computed in
1220 * expanded_aspects) and map them to planes in the image view.
1222 uint32_t iaspect_bit
, vplane
= 0;
1223 anv_foreach_image_aspect_bit(iaspect_bit
, image
, expanded_aspects
) {
1225 anv_image_aspect_to_plane(expanded_aspects
, 1UL << iaspect_bit
);
1226 VkImageAspectFlags vplane_aspect
=
1227 anv_plane_to_aspect(iview
->aspect_mask
, vplane
);
1228 struct anv_format_plane format
=
1229 anv_get_format_plane(&device
->info
, pCreateInfo
->format
,
1230 vplane_aspect
, image
->tiling
);
1232 iview
->planes
[vplane
].image_plane
= iplane
;
1234 iview
->planes
[vplane
].isl
= (struct isl_view
) {
1235 .format
= format
.isl_format
,
1236 .base_level
= range
->baseMipLevel
,
1237 .levels
= anv_get_levelCount(image
, range
),
1238 .base_array_layer
= range
->baseArrayLayer
,
1239 .array_len
= anv_get_layerCount(image
, range
),
1241 .r
= remap_swizzle(pCreateInfo
->components
.r
,
1242 VK_COMPONENT_SWIZZLE_R
, format
.swizzle
),
1243 .g
= remap_swizzle(pCreateInfo
->components
.g
,
1244 VK_COMPONENT_SWIZZLE_G
, format
.swizzle
),
1245 .b
= remap_swizzle(pCreateInfo
->components
.b
,
1246 VK_COMPONENT_SWIZZLE_B
, format
.swizzle
),
1247 .a
= remap_swizzle(pCreateInfo
->components
.a
,
1248 VK_COMPONENT_SWIZZLE_A
, format
.swizzle
),
1252 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_3D
) {
1253 iview
->planes
[vplane
].isl
.base_array_layer
= 0;
1254 iview
->planes
[vplane
].isl
.array_len
= iview
->extent
.depth
;
1257 if (pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE
||
1258 pCreateInfo
->viewType
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
) {
1259 iview
->planes
[vplane
].isl
.usage
= ISL_SURF_USAGE_CUBE_BIT
;
1261 iview
->planes
[vplane
].isl
.usage
= 0;
1264 if (view_usage
& VK_IMAGE_USAGE_SAMPLED_BIT
||
1265 (view_usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
&&
1266 !(iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
))) {
1267 iview
->planes
[vplane
].optimal_sampler_surface_state
.state
= alloc_surface_state(device
);
1268 iview
->planes
[vplane
].general_sampler_surface_state
.state
= alloc_surface_state(device
);
1270 enum isl_aux_usage general_aux_usage
=
1271 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1272 VK_IMAGE_LAYOUT_GENERAL
);
1273 enum isl_aux_usage optimal_aux_usage
=
1274 anv_layout_to_aux_usage(&device
->info
, image
, 1UL << iaspect_bit
,
1275 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
1277 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1278 &iview
->planes
[vplane
].isl
,
1279 ISL_SURF_USAGE_TEXTURE_BIT
,
1280 optimal_aux_usage
, NULL
,
1281 ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL
,
1282 &iview
->planes
[vplane
].optimal_sampler_surface_state
,
1285 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1286 &iview
->planes
[vplane
].isl
,
1287 ISL_SURF_USAGE_TEXTURE_BIT
,
1288 general_aux_usage
, NULL
,
1290 &iview
->planes
[vplane
].general_sampler_surface_state
,
1294 /* NOTE: This one needs to go last since it may stomp isl_view.format */
1295 if (view_usage
& VK_IMAGE_USAGE_STORAGE_BIT
) {
1296 iview
->planes
[vplane
].storage_surface_state
.state
= alloc_surface_state(device
);
1297 iview
->planes
[vplane
].writeonly_storage_surface_state
.state
= alloc_surface_state(device
);
1299 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1300 &iview
->planes
[vplane
].isl
,
1301 ISL_SURF_USAGE_STORAGE_BIT
,
1302 ISL_AUX_USAGE_NONE
, NULL
,
1304 &iview
->planes
[vplane
].storage_surface_state
,
1305 &iview
->planes
[vplane
].storage_image_param
);
1307 anv_image_fill_surface_state(device
, image
, 1ULL << iaspect_bit
,
1308 &iview
->planes
[vplane
].isl
,
1309 ISL_SURF_USAGE_STORAGE_BIT
,
1310 ISL_AUX_USAGE_NONE
, NULL
,
1311 ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY
,
1312 &iview
->planes
[vplane
].writeonly_storage_surface_state
,
1319 *pView
= anv_image_view_to_handle(iview
);
1325 anv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1326 const VkAllocationCallbacks
*pAllocator
)
1328 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1329 ANV_FROM_HANDLE(anv_image_view
, iview
, _iview
);
1334 for (uint32_t plane
= 0; plane
< iview
->n_planes
; plane
++) {
1335 if (iview
->planes
[plane
].optimal_sampler_surface_state
.state
.alloc_size
> 0) {
1336 anv_state_pool_free(&device
->surface_state_pool
,
1337 iview
->planes
[plane
].optimal_sampler_surface_state
.state
);
1340 if (iview
->planes
[plane
].general_sampler_surface_state
.state
.alloc_size
> 0) {
1341 anv_state_pool_free(&device
->surface_state_pool
,
1342 iview
->planes
[plane
].general_sampler_surface_state
.state
);
1345 if (iview
->planes
[plane
].storage_surface_state
.state
.alloc_size
> 0) {
1346 anv_state_pool_free(&device
->surface_state_pool
,
1347 iview
->planes
[plane
].storage_surface_state
.state
);
1350 if (iview
->planes
[plane
].writeonly_storage_surface_state
.state
.alloc_size
> 0) {
1351 anv_state_pool_free(&device
->surface_state_pool
,
1352 iview
->planes
[plane
].writeonly_storage_surface_state
.state
);
1356 vk_free2(&device
->alloc
, pAllocator
, iview
);
1361 anv_CreateBufferView(VkDevice _device
,
1362 const VkBufferViewCreateInfo
*pCreateInfo
,
1363 const VkAllocationCallbacks
*pAllocator
,
1364 VkBufferView
*pView
)
1366 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1367 ANV_FROM_HANDLE(anv_buffer
, buffer
, pCreateInfo
->buffer
);
1368 struct anv_buffer_view
*view
;
1370 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1371 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1373 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1375 /* TODO: Handle the format swizzle? */
1377 view
->format
= anv_get_isl_format(&device
->info
, pCreateInfo
->format
,
1378 VK_IMAGE_ASPECT_COLOR_BIT
,
1379 VK_IMAGE_TILING_LINEAR
);
1380 const uint32_t format_bs
= isl_format_get_layout(view
->format
)->bpb
/ 8;
1381 view
->bo
= buffer
->bo
;
1382 view
->offset
= buffer
->offset
+ pCreateInfo
->offset
;
1383 view
->range
= anv_buffer_get_range(buffer
, pCreateInfo
->offset
,
1384 pCreateInfo
->range
);
1385 view
->range
= align_down_npot_u32(view
->range
, format_bs
);
1387 if (buffer
->usage
& VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT
) {
1388 view
->surface_state
= alloc_surface_state(device
);
1390 anv_fill_buffer_surface_state(device
, view
->surface_state
,
1392 view
->offset
, view
->range
, format_bs
);
1394 view
->surface_state
= (struct anv_state
){ 0 };
1397 if (buffer
->usage
& VK_BUFFER_USAGE_STORAGE_TEXEL_BUFFER_BIT
) {
1398 view
->storage_surface_state
= alloc_surface_state(device
);
1399 view
->writeonly_storage_surface_state
= alloc_surface_state(device
);
1401 enum isl_format storage_format
=
1402 isl_has_matching_typed_storage_image_format(&device
->info
,
1404 isl_lower_storage_image_format(&device
->info
, view
->format
) :
1407 anv_fill_buffer_surface_state(device
, view
->storage_surface_state
,
1409 view
->offset
, view
->range
,
1410 (storage_format
== ISL_FORMAT_RAW
? 1 :
1411 isl_format_get_layout(storage_format
)->bpb
/ 8));
1413 /* Write-only accesses should use the original format. */
1414 anv_fill_buffer_surface_state(device
, view
->writeonly_storage_surface_state
,
1416 view
->offset
, view
->range
,
1417 isl_format_get_layout(view
->format
)->bpb
/ 8);
1419 isl_buffer_fill_image_param(&device
->isl_dev
,
1420 &view
->storage_image_param
,
1421 view
->format
, view
->range
);
1423 view
->storage_surface_state
= (struct anv_state
){ 0 };
1424 view
->writeonly_storage_surface_state
= (struct anv_state
){ 0 };
1427 *pView
= anv_buffer_view_to_handle(view
);
1433 anv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1434 const VkAllocationCallbacks
*pAllocator
)
1436 ANV_FROM_HANDLE(anv_device
, device
, _device
);
1437 ANV_FROM_HANDLE(anv_buffer_view
, view
, bufferView
);
1442 if (view
->surface_state
.alloc_size
> 0)
1443 anv_state_pool_free(&device
->surface_state_pool
,
1444 view
->surface_state
);
1446 if (view
->storage_surface_state
.alloc_size
> 0)
1447 anv_state_pool_free(&device
->surface_state_pool
,
1448 view
->storage_surface_state
);
1450 if (view
->writeonly_storage_surface_state
.alloc_size
> 0)
1451 anv_state_pool_free(&device
->surface_state_pool
,
1452 view
->writeonly_storage_surface_state
);
1454 vk_free2(&device
->alloc
, pAllocator
, view
);
1457 const struct anv_surface
*
1458 anv_image_get_surface_for_aspect_mask(const struct anv_image
*image
,
1459 VkImageAspectFlags aspect_mask
)
1461 VkImageAspectFlags sanitized_mask
;
1463 switch (aspect_mask
) {
1464 case VK_IMAGE_ASPECT_COLOR_BIT
:
1465 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1466 sanitized_mask
= VK_IMAGE_ASPECT_COLOR_BIT
;
1468 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1469 assert(image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
1470 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1472 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1473 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
1474 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1476 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1477 /* FINISHME: The Vulkan spec (git a511ba2) requires support for
1478 * combined depth stencil formats. Specifically, it states:
1480 * At least one of ename:VK_FORMAT_D24_UNORM_S8_UINT or
1481 * ename:VK_FORMAT_D32_SFLOAT_S8_UINT must be supported.
1483 * Image views with both depth and stencil aspects are only valid for
1484 * render target attachments, in which case
1485 * cmd_buffer_emit_depth_stencil() will pick out both the depth and
1486 * stencil surfaces from the underlying surface.
1488 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1489 sanitized_mask
= VK_IMAGE_ASPECT_DEPTH_BIT
;
1491 assert(image
->aspects
== VK_IMAGE_ASPECT_STENCIL_BIT
);
1492 sanitized_mask
= VK_IMAGE_ASPECT_STENCIL_BIT
;
1495 case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
:
1496 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1497 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR
;
1499 case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
:
1500 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1501 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_1_BIT_KHR
;
1503 case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
:
1504 assert((image
->aspects
& ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0);
1505 sanitized_mask
= VK_IMAGE_ASPECT_PLANE_2_BIT_KHR
;
1508 unreachable("image does not have aspect");
1512 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, sanitized_mask
);
1513 return &image
->planes
[plane
].surface
;